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13 commits

Author SHA1 Message Date
Rafaël Carré
ffefe0c08b Put TIMER_FREQ definition in CPU-specific config, and remove timer-target.h 
Note : SH has TIMER_FREQ defined to CPU_FREQ, so any code wanting it must include #config.h before #cpu.h

git-svn-id: svn://svn.rockbox.org/rockbox/trunk@21560 a1c6a512-1295-4272-9138-f99709370657
 2009-06-29 14:30:12 +00:00
Daniel Stenberg
2acc0ac542 Updated our source code header to explicitly mention that we are GPL v2 or 
later. We still need to hunt down snippets used that are not. 1324 modified
files...
http://www.rockbox.org/mail/archive/rockbox-dev-archive-2008-06/0060.shtml


git-svn-id: svn://svn.rockbox.org/rockbox/trunk@17847 a1c6a512-1295-4272-9138-f99709370657
 2008-06-28 18:10:04 +00:00
Jens Arnold
83aded979f H300: (1) Use DMA for LCD updates, with auto-aligned line reads. Speeds up LCD updates by ~ 75% at 11MHz and 45MHz. Only ~ 11% speedup at 124MHz due to (2). (2) Less aggressive LCD transfer timing at 124MHz. With the previous timing, slightly corrupted display contents was reported, and with DMA transfers at least 4 waitstates are needed to make updates work at all. * A table in system-iriver.c shows settings for all integer multiples of the base clock frequency (info for developers, not yet complete). 
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@11418 a1c6a512-1295-4272-9138-f99709370657
 2006-11-02 20:50:50 +00:00
Jens Arnold
72f98786a0 Fixup of the MCF5249 memory mapped register definitions. 
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@7755 a1c6a512-1295-4272-9138-f99709370657
 2005-11-05 03:28:20 +00:00
Linus Nielsen Feltzing
fb5d2629a1 Corrected UART register names 
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@7325 a1c6a512-1295-4272-9138-f99709370657
 2005-08-13 22:12:40 +00:00
Andy
e5d08722f8 Iriver: First attempt at recording. Use Info->Debug->PCM recording to test recording of wav-files. Seams to work fine except occasional 100 ms noise at pos 100 ms (not later) so initialization or synch problem.. 
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@6763 a1c6a512-1295-4272-9138-f99709370657
 2005-06-19 03:05:53 +00:00
Linus Nielsen Feltzing
cff83c78c7 ColdFire: DCR is a 16-bit register 
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@6604 a1c6a512-1295-4272-9138-f99709370657
 2005-06-08 07:37:32 +00:00
Linus Nielsen Feltzing
752d0bb8be Added DMA register definitions 
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@6202 a1c6a512-1295-4272-9138-f99709370657
 2005-03-18 11:33:07 +00:00
Linus Nielsen Feltzing
e52e3f713f Correct size for the DCRx registers 
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@5993 a1c6a512-1295-4272-9138-f99709370657
 2005-02-16 22:14:36 +00:00
Linus Nielsen Feltzing
b57fd974de Correct size for the BCRx registers 
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@5992 a1c6a512-1295-4272-9138-f99709370657
 2005-02-16 22:10:47 +00:00
Linus Nielsen Feltzing
672092c6dc Made the Coldfire registers volatile, rename PLLCONTROL to PLLCR 
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@5941 a1c6a512-1295-4272-9138-f99709370657
 2005-02-14 21:30:30 +00:00
Linus Nielsen Feltzing
58462ab101 The timer registers are 16-bit 
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@5364 a1c6a512-1295-4272-9138-f99709370657
 2004-10-27 06:50:00 +00:00
Linus Nielsen Feltzing
515d819d3e CPU definitions for MCF5249 
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@5183 a1c6a512-1295-4272-9138-f99709370657
 2004-10-06 13:25:56 +00:00