* pcm_get_bytes_remaining()
* pcm_calculate_peaks()
* pcm_get_peak_buffer()
Nothing in-tree uses these at all (except for the lua plugin wrapper)
Change-Id: I971b7beed6760250c8b1ce58f401a601e1e2d585
Nothing in the core has used it for some time. It's exported to the
plugin API but the last plugins to use it were switched to the mixer API
back in 2011.
This allows us to get rid of pcm_play_dma_pause() from all audio drivers
Change-Id: Ic3fa02592316f84963e41d792d1cabb436d1ff6b
7442742 ("iPod Classic: disable IRAM1") was causing subsequent ipod6g
bootloader builds to result in a completely black screen upon
installation, with recovery only possible with a reflash through DFU
mode.
IRAM1 is re-enabled for bootloader only.
Change-Id: I92d489c91f81cad55d66a8647c1e61a45f468770
On Classic, IRAM1 (second 128Kb of a total of 256KB available IRAM) is
slower than DRAM. Codecs that actually are using regions of IRAM1 runs
faster when DRAM is used, so IRAM1 is disabled and only IRAM0 remains
enabled: 48KB for core and 80KB for codecs/plugins.
The next test_codec results shows how decode time is decreased:
file boosted unboosted
*.ra ~1.5% ~0.5%
*.mpc ~21% ~4.5%
*.ogg ~0.5% ~0%
nero_he*.m4a ~8% ~1%
nero*.m4a ~25% ~7%
wmapro*.wma ~4.5% ~0%
wma*.wma ~25% ~7%
In addition there is a small power save when IRAM1 HW is disabled.
Change-Id: I102adee11458e82037f23076d5d5956e23235de8
* Editing a bunch of drivers' thread routines in order to
implement a new feature is tedious.
* No matter the number of storage drivers, they share one thread.
No extra threads needed for CONFIG_STORAGE_MULTI.
* Each has an event callback called by the storage thread.
* A default callback is provided to fake sleeping in order to
trigger idle callbacks. It could also do other default processing.
Changes to it will be part of driver code without editing each
one.
* Drivers may sleep and wake as they please as long as they give
a low pulse on their storage bit to ask to go into sleep mode.
Idle callback is called on its behalf and driver immediately put
into sleep mode.
* Drivers may indicate they are to continue receiving events in
USB mode, otherwise they receve nothing until disconnect (they
do receive SYS_USB_DISCONNECTED no matter what).
* Rework a few things to keep the callback implementation sane
and maintainable. ata.c was dreadful with all those bools; make
it a state machine and easier to follow. Remove last_user_activity;
it has no purpose that isn't served by keeping the disk active
through last_disk_activity instead.
* Even-out stack sizes partly because of a lack of a decent place
to define them by driver or SoC or whatever; it doesn't seem too
critical to do that anyway. Many are simply too large while at
least one isn't really adequate. They may be individually
overridden if necessary (figure out where). The thread uses the
greatest size demanded. Newer file code is much more frugal with
stack space. I barely see use crack 50% after idle callbacks
(usually mid-40s). Card insert/eject doesn't demand much.
* No forcing of idle callbacks. If it isn't necessary for one or
more non-disk storage types, it really isn't any more necessary for
disk storage. Besides, it makes the whole thing easier to implement.
Change-Id: Id30c284d82a8af66e47f2cfe104c52cbd8aa7215
- Fix broken recording from jack microphone.
- Fix recording hardware detection on models that do not support
the jack microphone.
- Enable monitor mode when recording.
Change-Id: Ib79a2746f2d75f74cf6667d33bc9ed6512bbc8a9
As preparation to add new targets to the s5l8702 directory,
rename files as:
s5l8702/ipod6g/*-ipod6g.c -> s5l8702/ipod6g/*-6g.c
Change-Id: I0cd03d6bcf39b2aa198235f9014cb6948bbafcd5
Some drivers set tm_wday just fine and do not need it coerced to
be correct. Others set tm_yday, so don't overwrite what the driver
sets; just zero it inside if it can't fill the field. Move calls
to set_day_of_week() to the sorts of drivers that presumably
required the hammer (FS#11814) in get_time() where the weekday
isn't locked to the date.
Change-Id: Idd0ded6bfc9d9f48fcc1a6074068164c42fcf24a
On PCM record initialization, an unknown clockgate is enabled instead
of the I2S clockgate. This bug does not produce incorrect functionallity
because the right clockgate is already enabled on PCM playback
initialization.
Change-Id: I97a3a4a6f12131e492c1431359a0a976b68014be
Based on emCORE.
Low level functions that do not depend on Rockbox kernel,
intended to be used by the bootloader, dualboot-installer,
RB drivers or other .dfu tools.
Change-Id: I3c616ded42260c6626bda23b7e580791981df61d
Based on emCORE.
Low level functions that do not depend on Rockbox kernel,
intended to be used by the bootloader, dualboot-installer,
RB drivers or other .dfu tools.
Change-Id: Iad369627b55bf1778eab437424072f1a653e4db6
- Some rewrite with the intent to get ride of these random errors
appearing on some builds/devices (not much noticeable on RB but
can ruin bootloader builds).
- Error handling (ACK).
- IIC clock increased to be the same as in OF.
Change-Id: Idf8cfa3c230a0a61ec9c879bf6f0ea8b061a4607
Add code to read USB D+/D- and accessory ADCs, it is shown in HW
debug menu, might be useful in future for RB and/or the bootloader
to identify external USB chargers.
Change-Id: Ia48ca5e06bb7ddc52bb55abedde6734653ce8dba
- Speed auto detection is launched when an accessory is inserted,
so the user doesn't need to modify settings to use accessories
that operates at different speeds (or when the same accessory is
unplugged and plugged again).
- UART controller is disabled when no accessory is inserted, not
much powersave but everything counts.
Change-Id: If20c3617c2a87b6277fd7e0270031030c44fa953
PMU interrupts are used to detect USB Vbus, wall adaptor, accessories
and holdswitch. A thread is needed to poll the PMU throught I2C, ATM
it does nothing but showing the state of the inputs on the HW debug
menu, funcionallity for each individual input will be added in next
patches.
Change-Id: If93bf2044d1052729237a7fd1431c8493e09f1c7
Do not rely on a bootloader initializing the HW, RB initializes
and configures GPIO, I2C, and PMU at startup.
Change-Id: If7f856b1f345f63de584aa4e4fc22d130cd66c80
Low level functions that do not depend on Rockbox kernel,
intended to be used by the bootloader, dualboot-installer,
RB drivers or other .dfu tools.
Change-Id: If80214d26e505265ace19d9704f1e1300f98b2f4
When the bootloader starts, most of HW never has been initialized.
This patch includes all code needed to perform the preliminary
initialization on SYSCON, GPIO, i2c, and MIU.
The code is based on emCORE and OF reverse engineering, ported to
C for readability.
Change-Id: I9ecf2c3e8b1b636241a211dbba8735137accd05c
This patch optimizes UDMA timings to increase write transfer rate on
ATA bus, these transfers are clocked by HCLK, tDVS+tDVH is modified to
decrease Tcyctyp (typical write cycle period). This is not overclocking,
we meet the ATA standar, the settings used by OF are not well optimized
for each UDMA mode, we will never know but probably this was due some
documentation issue.
ATA_UDMA_TIME register is documented on s3c6400 datasheet, information
included in s5l8700 datasheet is wrong or not valid for s5l8702.
From ATA specs, (Minimum, Maximum) values in nanoseconds:
UDMA 0 UDMA 1 UDMA 2 UDMA 3 UDMA 4
tACKENV (20, 70) (20, 70) (20, 70) (20, 55) (20, 55)
tRP (160, --) (125, --) (100, --) (100, --) (100, --)
tSS (50, --) (50, --) (50, --) (50, --) (50, --)
tDVS (70, --) (48, --) (31, --) (20, --) (6.7, --)
tDVH (6.2, --) (6.2, --) (6.2, --) (6.2, --) (6.2, --)
tDVS+tDVH (120, --) (80, --) (60, --) (45, --) (30, --)
Tcyc = tDVS+tDVH
WR[bytes/s] = 1/Tcyc[s] * 2[bytes]
On Classic (boosted):
HClk = 108 MHz. -> T = ~9.26 ns.
Old values (used by OF):
UDMA ATA_UDMA_TIME tACK tRP tSS tDVS tDVH Tcyc WR(MB/s)
0 0x5071152 27.8 166.7 55.6 74.1 55.6 129.7 15.4
1 0x3050a52 27.8 101.8 55.6 55.6 37 92.6 21.6
2 0x3030a52 27.8 101.8 55.6 37 37 74 27
3 0x2020a52 27.8 101.8 55.6 27.8 27.8 55.6 36
4 0x2010a52 27.8 101.8 55.6 18.5 27.8 46.3 43.2
New values:
UDMA ATA_UDMA_TIME tACK tRP tSS tDVS tDVH Tcyc WR(MB/s)
0 0x4071152 27.8 166.7 55.6 74.1 46.3 120.4 16.6
1 0x2050d52 27.8 129.6 55.6 55.6 27.8 83.4 24
2 0x2030a52 27.8 101.8 55.6 37 27.8 64.8 30.9
3 0x1020a52 27.8 101.8 55.6 27.8 18.5 46.3 43.2
4 0x1010a52 27.8 101.8 55.6 18.5 18.5 37 54
To verify that the settings are correct, a write-to-cache test was
performed using emCORE, the measured transfer rate (WRm) is compared
against the theoric transfer rate (WR) at 108 Mhz for the old and
the new UDMA4 settings (iPod 160, HDD Toshiba MK1634GAL):
UDMA ATA_UDMA_TIME Tcyc(ns) WR(MB/s) WRm(MB/s) RDm(MB/s)
4 0x2010a52 46.3 43.2 42.9 59.8
4 0x1010a52 37 54 53.5 59.8
Notes:
- The new UDMA4 settings increases ~25% the ATA transfer rate for
cached-writes. The real HDD write speed is limited by the internal
transfer rate (depends on cilinder, for the MK1634GAL it is 276 to
573 Mbits/s). Sequential write benchmark using diskdump on USB are
~8% faster.
- Read transfers are clocked by the device, it depends on UDMA mode
selected and are not affected by HClk or ATA_UDMA_TIME settings.
Read-from-cache tests results (RDm) using HClk=108 and HClk=54 for
UDMA4 are 59.8 MB/s on MK1634GAL.
- Minimum HClk is limited by tACKENV specs, using current settings
it is 54 MHz for UDMA4,UDMA3 and 43 MHz for UDMA2,UDMA1,UDMA0.
Change-Id: I61d67060410752518a59e1ff08072b21747ca997
When the bootloader starts only IRAM is available, the first task is to
ask the PMU to verify if the iPod has previously been hibernated by OF.
Due to memory limitations, the kernel cannot be used on this stage.
This patch modifies I2C and PMU low level functions to not to depend
on kernel (removes mutexes, and uses HW timer instead of current_tick),
actual kernel functions are modified to be 'mutexed' wrappers of the new
functions.
Change-Id: I7cef9e95dedaf176dc0659315f3dc33166d5b116
- Small rework on the UC8702 UART controller to make it compatible with
other s5l870x SOCs. Files moved and renamed, many conditional code
added to deal with capabilities and 'features' of the different CPUs.
- A couple of optimizacions that should not affect the functionality.
Change-Id: I705169f7e8b18d5d1da642f81ffc31c4089780a6
This should allow FireWire charging to work on these devices.
It also adds charging state detection on the iPod Classic.
(cherry picked from commit fa86fec4fb)
On Classic (and probably Nano 2G), it seems that the 100/500mA limit
applies only to USB chargers, when FW is connected it supplies all the
power (even if USB is also connected) and USB current limit does not
affect to FW charging, therefore the limit is only set when USB is
connected.
Change-Id: I7c6bab1b6a0f295367999c45faeda6085c3fb091
Signed-off-by: Cástor Muñoz <cmvidal@gmail.com>
Read/write buffers who are aligned to 16 were not re-aligned to 32 as
it should be. Althrough USB storage and buffering are always passing
buffers aligned to 32, a few unaligned buffers are being received from
other tasks, so this patch could solve some rare random issues.
Also fixes DMA configuration for HDDs that support any MDMA mode but
only UDMA0 (probably will never happen).
Change-Id: I00219ae434205681c69293fc563e0526224c9adf
- Add description for attributes supported by Samsung HS081HA (80Gb)
and HS161JQ (CEATA 160Gb).
- Show error code when ata_read_smart() fails.
Change-Id: I618cc4f37d139fc90f596e2cf3a751346b27deb6
Reverts commit ead38dbc9d
It was introduced as a temporal workaround to avoid the endless restart
loop when battery is low, but really it is useless. The bootloader should
ensure that there is enough power to launch Rockbox even in the worst
scenario.
Change-Id: Iabebed40c9241af915c16c3c6c4d3c6deef7680e
Configures uncached memory region and adds some defines for misc HW,
for compability with the bootloader and other future use, current
functionality should not be affected.
Change-Id: I390e79bea1aef5b10dfbc72ad327d7fe438ec6f5
