Michael Sevakis
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e4f64da35f
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i.MX31 avic: Fix super-stale comment.
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@30748 a1c6a512-1295-4272-9138-f99709370657
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2011-10-14 06:19:03 +00:00 |
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Michael Sevakis
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830531b7d4
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i.MX31: Simplify nested interrupt handling. Give SVC mode its own stack by grabbing the FIQ stack that's just been taking up space. Just get rid of all FIQ setup since it isn't used anyway.
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@30747 a1c6a512-1295-4272-9138-f99709370657
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2011-10-14 00:01:41 +00:00 |
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Michael Sevakis
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9d97ee1b54
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Gigabeat S/i.MX31: Take care of an interrupt priority inversion that can happen during PCM callback lockout when DVFS switches frequecies during the lockout, preventing a thread from unlocking the callback until DVFS finishes, causing an SSI FIFO underrun. Hadn't thought of an acceptable way to deal with it before.
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@28996 a1c6a512-1295-4272-9138-f99709370657
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2011-01-07 20:40:36 +00:00 |
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Michael Sevakis
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affea5fe9e
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i.MX31: Make some style changes to some driver code so that hardware vs. variable access is more obvious to the eye. Change a few data types and qualifiers. No functional differences.
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@25865 a1c6a512-1295-4272-9138-f99709370657
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2010-05-07 02:29:18 +00:00 |
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Michael Sevakis
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a36a498c57
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i.MX31/Gigabeat S: This should fix stability problems. One problem was to start using the DVFS controller properly so that interrupts will be masked at the lowest and highest frequency indexes. Millions of useless interrupts were occurring at 132MHz because its index was 2, not 3, which masks it automatically when it can't go slower. Stopping the flood was enough to actually see the difference in general. IRQ must be disabled when fiddling with the CCM registers and only enabled when waiting for voltage ramp as having them enables also causes spurious DVFS ints. Implement interruptible ISR pro/epilogue more safely (always using IRQ stack even in SVC mode handling). Fix an improper inequality in DVFS code (which set regs for down when going up and v.v.). Misc. support changes. Have internal tables take less RAM.
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@25837 a1c6a512-1295-4272-9138-f99709370657
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2010-05-06 03:23:51 +00:00 |
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Michael Sevakis
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630b4fc555
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i.MX31/Gigabeat S: The nested IRQ code was just totally wrong and not actually working anyway (which is why it wasn't crashing). AVIC doesn't seem truthful about priority of current ISR either :\. Sometimes there were channel swaps during really active DVFS due to FIFO underflow from a needed long delay in the ISR (100us, and IIS TX only has 45us reserve) and DMARQ *must* be serviced low-latency. Get it doing as was intended.
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@25822 a1c6a512-1295-4272-9138-f99709370657
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2010-05-05 07:15:20 +00:00 |
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Michael Sevakis
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11cca264ff
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i.MX31/Gigabeat S: Implement frequency and voltage scaling-- 1.6V for 528MHz, and 1.35V for 264MHz and 132MHz. Keep DPTC overdrive ( > 400MHz) voltage scaling off for now because of uncertainties. Simplify the (working) mess later.
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@25699 a1c6a512-1295-4272-9138-f99709370657
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2010-04-23 15:32:50 +00:00 |
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Michael Sevakis
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7abf2b53a4
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Gigabeat S/i.MX31: Sort files in the /target tree into things that are SoC-generic (into /imx31) and player-specific (into /gigabeat-s, based upon current appearances). Move i2s clock init into the appropriate file. Housekeeping only-- no functional changes.
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@25547 a1c6a512-1295-4272-9138-f99709370657
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2010-04-09 01:21:53 +00:00 |
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