pcm_dma_apply_settings(): sets the configured PCM frequency,
all native CS42L55 sample rates are available.
Change-Id: I2fcd5581457a669c3044516804cb64fb972218d0
Actually Rockbox does not use this mode, it is supported by
other iPods, so implemented on Classic as well.
Change-Id: Ia6578506df27a95a7f7522b3034b764631a8bb3a
Scale battery voltage ADC readings by 1023 instead of 1000,
using ADC1 (substractor) instead of ADC0 (multiplicator) to
get better resolution.
Percent charge/discharge tables are also modified to return
a similar value than the old ones.
Change-Id: I2951c75faa02f4302599ec24f9156cfd209c36eb
On heavy storage operations (like database update), the ssp dma
irq can be fired around ~10000/sec.
Change-Id: I0e33df6258e051abd4fe110a0f408a19671cd8ad
Do low level power init in system_init(). This can be needed
since imx233 must be able to frequecy scale atfer system_init()
and kernel_init() and this is only possible if power system was
initialised.
Change-Id: I27c66ec0dccd60bda26a45be24683c0bfe72c6da
The current code uses the msec irq to collect statistics and
detect irq storms (debug). But this irq is triggered 1000 times
per sec and we don't need that accuracy. This commit removes the
msec irq and use the tick timer instead which is triggered only
100 times per second.
Change-Id: If14b9503c89a3af370ef322678f10e35fafb4b8a
The lcd driver does not wait for the refresh to be done to return
from lcd_update(). This means that changing a register is unsafe
if done in the middle of the redraw. This could happen when
disabling the lcd for example. Make sure it doesn't happen by
waiting for the lcdif to be ready.
Change-Id: I43ec62a637dd61c3b2a3a6e131c1a9e8035524b1
When changing the cpu frequency, it is important to make sure that
HBUS stays at a reasonable frequency otherwise the chip will
crash. Special care is needed about auto-slow and clk_p/clk_h
ratio on intermediate steps.
Change-Id: Ief9f68ddf286caabe75c879718dac5027ab1560f
Make sure DCDC is running at boot (it is disabled by default when
5V is present and we don't want to rely on the bootloader to
change this).
When changing the voltage on a regulator, it usually takes 2ms for
the voltage to stabilize. In DCDC mode, there is an irq to notify
about the event so use it ! This is especially important when
changing cpu frequency because increasing the cpu freq while the
voltage is rising is unreliable.
Change-Id: Icfe9ef3ee90156d1e17da0820d9041859f7f3bca
HBUS uses the same field for integer and fractional dividers, the
choice is made by a bit. Make sure both are changed together,
otherwise this could result in the wrong divider to be used and in
HBUS freq to be too low or too high (very bad).
Change-Id: I253d8eeee26c5038868b729c4f791511295a39f0
Ideally someone will go through and make a graphic for the 6G, but as it looks nearly identical to the Video its not a huge deal.
Change-Id: If507c6d4f01eb0b1e5fc2f15f6a0e5a3195006c6
Uninitialized struct scroll which is used to pass state between
scrollstrip ISR and button_read_device() can bomb out whole
button subsytem.
Change-Id: I3b415c22cfee4181b2132cddaeff68797c7cc0ea
If interrupts trigger during cache invalidation this could cause memory
corruption. This should be right fix for commit_discard_idcache in
contrast to 72ebcbf and c1ec1ec.
Change-Id: I141fb585004d4a1967b0a03bc37db3964d886564
Reviewed-on: http://gerrit.rockbox.org/345
Tested-by: Andrew Ryabinin <ryabinin.a.a@gmail.com>
Reviewed-by: Marcin Bukat <marcin.bukat@gmail.com>
It seems something wrong with cache handling in rk27xx. OF always disable cache
before invalidating cache ways, therefore, now we do the same.
Hopefully this will fix cache handling, but I couldn't contend that it's really so.
Change-Id: I967c18211f0ddff689b6a17579fbe8685277f132
This is work from FS#12431 synced to current HEAD and slightly
tweaked (gcc 4.6.2 -> 4.6.3, binutils 2.21.1 -> 2.22)
Change-Id: I76af91e80ac2a9c16a776c7f0a33cc51603bbf9b
The running count is only 16-bit wide, since the always tick
setting derives from the crystal clock at 24MHz the user timer
cannot be set lower than ~300Hz which is already too high.
Switch to the 32KHz crystal source to fix this.
Change-Id: Ie7775460b17ea7ab331738734e3d688ad5563857
Several HM-801 DAPs have another buttons circuit.
This patch adds support for such devices so they could work properly.
Change-Id: Ic49e8e46b3e785b91c7c4706003fac3dbc20ae59
Uses register polling method to decide when it's time to decode
RDS packets.
Change-Id: I1d3cc995ea3350ec7b101438b8f2027130d4a4c9
Reviewed-on: http://gerrit.rockbox.org/320
Reviewed-by: Lorenzo Miori <memorys60@gmail.com>
Tested-by: Lorenzo Miori <memorys60@gmail.com>
Reviewed-by: Thomas Martitz <kugel@rockbox.org>
Tested-by: Thomas Martitz <kugel@rockbox.org>
We should cast to (volatile uint32_t*) here, because attempt to refer to volatile
object through use of an lvalue with non-volatile-qualified type will result in
undefined behavior.
Change-Id: I1b2e9688af11d3dcba518a5e31865d703b54b635
Use DMA engine for fullscreen updates and bypass mode for partial
updates. This gives major boost on rk27generic:
default ARM:AHB:APB 200💯50
HEAD 1/1: 26.3fps 1/4: 105.0fps
patched 1/1: 116.5fps 1/4: 249.5fps
with freq scalling NORMAL mode ARM:AHB:APB 50:50:50
HEAD 1/1: 13.1fps 1/4: 52.5fps
patched 1/1: 54.5fps 1/4: 119.0fps
Tested on rk27generic noname DAP and on Hifimans.
Change-Id: Id9dd4d2d61542c7ea6b5c6336b170d6357cefde9
This version resembles how OF handle cache invalidates.
This seems to fix mysterious data aborts on plugin/codec loading
after introducing frequency scaling.
Credit goes to mortalis for pinpointing the reason of aborts.
Change-Id: I3477b3f65d593d7b43c36a0b06d863f71f000812
The functions document my reverse engineer findings about nand
controller. This code is commented out and is purely for reference
as FTL scheme is still unknown.
Change-Id: I70edeb4bfb0cbd51b6adc15afa7193dd8f71e8da
Frequency scaling seems to be unstable and causes the device to
freeze. It is unclear why at the moment, perhaps we need to ramp
up the vddd voltage to avoid a false brownout ?
Change-Id: I7aaea9d7c213922a65250fe50775fb785d430226
This does not scale the EMI frequency and keep the processor
betweel 261MHz and 454MHz. It can still be improve. The auto-slow
divisor could still be change, 8 seems reasonable for now
Change-Id: I639bb3f6b7f8efedc7dc58d08127849156eeb1b6
Implemented scheme:
ARM AHB APB
Normal 50 50 50 MHz
Max 200 100 50 MHz
Frequency scaling is disabled on rk27generic due to too
slow lcd updates when running with 50MHz AHB.
battery_bench shows ~1h runtime improvement on hifiman.
Change-Id: I2c6f8acf6d4570c4e14f5bcc72280b51ce13c408
Remove the old debug stuff about VDDx and add a clean api to
get/set the regulator (VDDD, VDDA, VDDIO, VDDMEM). This is useful
for proper frequency scaling.
Change-Id: Ia5a1a712fd66652a8ad9601ed00db31aba5a7561
Implement cache aligned transfer of more than one sectors. The
current code now transfers almost all data at once by moving
it within the buffer to make it cache aligned. This greatly
improves the performance of the transfers, especially in mass
storage mode.
Change-Id: Ic6e78773302f368426209f6fd6099089ea34cb16
Further merge drivers by using the same command and data functions.
No use one mutex per drive instead of a global sd lock. Fix the
RCA handling which was different between SD and MMC (shifted 16)
and thus confusing. Add MMC commands definition to the mmc.h
header similarly to the SD one. Change MMC handling a bit by
selecting/deselecting on each transfer like SD, which allows
for several MMC devices in theory and is more uniform.
Change-Id: I7024cb19c079553806138ead75b00640f1d2d95c
Merge sd and mmc drivers into a single sdmmc driver. This allows
some factoring of the code and simplify bug fixing. Also fix the
dma/cache related issue by doing all transfers via a correctly
aligned buffer. The current code is not smart enough to take
advantage of large user buffers currently but at least it is safe!
Change-Id: Ib0fd16dc7d52ef7bfe99fd586e03ecf08691edcd
There are tricky DMA/cache related issue on the imx233 which could
pop up with the old driver. The new one ensures that all dma
tranfers are cache safe by using an intermediate buffer.
Change-Id: I72060682d1c285c83ae16455cfdb62f372b5d687
Reduce DMA maximum transfer size since transfering 64Kb requires
to set a size of 0 and it's not worth adding checks everywhere
to handle this special case. Also add statistics about unaligned
transfer (wrt to cache). Update debug screen accordingly and
simplify it so it can fit smaller screens too.
Change-Id: I18391702f5e100a21f6f8d1ebab28d9f2bd8c66f
operation.
The interal ROM clock seems to be needed to reboot the player, so disabling
it is too dangerous. Hopefully this will prevent problems where crashes during
the abort handler resulted in a stock player that needed the battery to drain
in order to reboot.
Change-Id: I7d1e64743dde15b64d718ad3255dada3d570736f
The main reason for this is to be able to downscale the sdl app, which
when used for designing themes for android tends not to fit on laptop
screens these days.
Change-Id: Ib52731dbebcdd03a572be7754c157471165eb2df
Basically it uses the default SI4700 radio chip driver, the only thing that's different is the I2C access,
written specifically to interact with my kernel module.
Next things to add are:
- RDS support!
Change-Id: I0ed125641e00f93124d7a34f90dd508e7f1db5a4
Signed-off-by: Lorenzo Miori <memorys60@gmail.com>
Refactor native/hosted implementation seperation while at it
(no wrappers starting with _ anymore).
Change-Id: If68ae89700443bb3be483c1cace3d6739409560a
Apparently I got the "just-in-case" RXFIFO purge in there before the
RXFIFO was enabled, causing severe hardware spasms.
Change-Id: I2ea4b6d28e06372b61cb3f21ab2fce71dd408213
Implement PLL enabling/disable and unconditionally power the PLL
on startup. This is needed at least on the Zen X-Fi2.
Change-Id: Ib9ddfdeaf973cedded4b3586dd16aa95a61e78ba
1) Change the image with a clean one
2) add keymaps indication
Change-Id: I0d3fff317406809523fb34282df058fe2e074a2c
Reviewed-on: http://gerrit.rockbox.org/173
Reviewed-by: Peter D'Hoye <peter.dhoye@gmail.com>
Tested-by: Peter D'Hoye <peter.dhoye@gmail.com>
Because DMA descriptors needs to be committed and discarded from
the cache, if they are not cache aligned and/or if their size
is not a multiple of cache ligne, nasty side effects could occur
with adjacents data. The same applies to DMA buffers which are
still potentially broken. Add a macro to ensure that these
constraints will not break by error in the future.
Change-Id: I1dd69a5a9c29796c156d953eaa57c0d281e79846
