This speeds up partial updates quite a bit but what is more
important it opens up a way to efficiently implement
lcd_blit_yuv() using hw colorspace conversion.
Tested on rk27generic, hm60x v1 and v2 and on ma9.
Benchmark for hm60x v1 (by mortalis):
HEAD patched
1/1 141fps 138fps
1/4 315fps 395fps
Change-Id: I4cc115786c3139000fc14c49a7290e289cfd6c42
HAVE_SW_VOLUME_CONTROL is required and at this time only affects the
SDL targets using pcm-sdl.c.
Enables balance control in SDL targets, unless mono volume is in use.
Compiles software volume control as unbuffered when
PCM_SW_VOLUME_UNBUFFERED is defined. This avoids the overhead and
extra latency introduced by the double buffer when it is not needed.
Use this config when the target's PCM driver is buffered and sufficient
latency exists to perform safely the volume scaling.
Simulated targets that are double-buffered when made as native targets
remain so in the sim in order to run the same code.
Change-Id: Ifa77d2d3ae7376c65afecdfc785a084478cb5ffb
Reviewed-on: http://gerrit.rockbox.org/457
Reviewed-by: Michael Sevakis <jethead71@rockbox.org>
Tested-by: Michael Sevakis <jethead71@rockbox.org>
Based on FS#9920 by Ryan Press with changes to selection logic so
that it works on my iPod Photo. Should also work on iPod Color/4G
and Mini2G. Moved all target specific code from
firmware/drivers/serial.c into new file
firmware/target/arm/pp/uart-pp.c in the same manner as other
target specific uart code.
Update to fix build error on ipodmini2g by adding defines in config file.
Removed unwanted whitespace
Tested on iPod Photo.
Change-Id: Ia5539563966198e06372d70b5adf2ef78882f863
Reviewed-on: http://gerrit.rockbox.org/455
Reviewed-by: andypotter <liveboxandy@gmail.com>
Tested-by: andypotter <liveboxandy@gmail.com>
Reviewed-by: Marcin Bukat <marcin.bukat@gmail.com>
* SOUND_x enum can be generated by audiohw_settings.h along with settings
entries and sound_val2phys.
* VOLUME_MIN and VOLUME_MAX are no longer necessary within sound.c. If
you need them, they are for target-defined purposes.
* Fix up SDL volume implementation in sdl.c. Move sim volume calculation
code to pcm-sdl.c.
* Min trigger tresholds were based upon VOLUME_MIN for some reason.
These setting have nothing to do with playback volume. Since it is no
longer present, set these at -89dB which is the minimum peak meter
sensitivity setting.
* Fix an oversight in wm8758.c. I forgot to add the dB->register
conversion to audiohw_set_volume.
Change-Id: Ie1df33f1793eee75e6793f16bc7bddd16edb7f75
This is going right in since it's long overdue. If anything is goofed,
drop me a line or just tweak it yourself if you know what's wrong. :-)
Make HW/SW codec interface more uniform when emulating HW functionality
on SWCODEC for functions such as "audiohw_set_pitch". The firmware-to-
DSP plumbing is in firmware/drivers/audiohw-swcodec.c. "sound_XXX"
APIs are all in sound.c with none in DSP code any longer.
Reduce number of settings definitions needed by each codec by providing
defaults for common ones like balance, channels and SW tone controls.
Remove need for separate SIM code and tables and add virtual codec header
for hosted targets.
Change-Id: I3f23702bca054fc9bda40f49824ce681bb7f777b
Onda VX747 sim was missing a limits #define; #include limits.h in
pcm_sw_volume.h.
Simply use the software volume control for the SIM volume control
rather than the SDL volume control when the target would have it
natively.
Change-Id: I8e924a2ff1b410f602452d2ea9b691efb82c931e
Implements double-buffered volume, balance and prescaling control in
the main PCM driver when HAVE_SW_VOLUME_CONTROL is defined ensuring
that all PCM is volume controlled and level changes are low in latency.
Supports -73 to +6 dB using a 15-bit factor so that no large-integer
math is needed.
Low-level hardware drivers do not have to implement it themselves but
parameters can be changed (currently defined in pcm-internal.h) to work
best with a particular SoC or to provide different volume ranges.
Volume and prescale calls should be made in the codec driver. It should
appear as a normal hardware interface. PCM volume calls expect .1 dB
units.
Change-Id: Idf6316a64ef4fb8abcede10707e1e6c6d01d57db
Reviewed-on: http://gerrit.rockbox.org/423
Reviewed-by: Michael Sevakis <jethead71@rockbox.org>
Tested-by: Michael Sevakis <jethead71@rockbox.org>
The old way actually mis-used the API (I misunderstood the docs) because
it specified the marker position as a "low buffer watermark" but instead of a
future playback head position.
The replacement is a simple thread that writes the data regardless of the
filling level of the buffer (write() will just block) and polls the playback
state periodically.
Change-Id: If29237cee4ce78dc42f5a8320878bab0cafe78f7
Reviewed-on: http://gerrit.rockbox.org/422
Tested-by: Dominik Riebeling <Dominik.Riebeling@gmail.com>
Reviewed-by: Thomas Martitz <kugel@rockbox.org>
This was spotted while playing with qemu-jz:
1) rockbox reads TECR and TESR which are described as write-only
registers. Datasheet doesn't mention what happens if they are
readed. Apparently this doesn't have fatal side effects.
It comes down to two defines from jz4740.h
__tcu_stop_counter(n) and __tcu_start_counter(n) which use
read-modify-write sequence.
2) rockbox accesses out of bound offset 0xd4 in DMA memspace.
It comes from dis_irq() in system-jz4740.c. NUM_DMA is 6 but
DMA channels are 0-5 so (irq <= IRQ_DMA_0 + NUM_DMA)) bound
check is wrong.
This are *NOT* tested on device.
Change-Id: I29dff6a4f828030877b7d50fbcc98866478b9e3d
Reviewed-on: http://gerrit.rockbox.org/338
Reviewed-by: Bertrik Sikken <bertrik@sikken.nl>
Tested-by: Purling Nayuki <cyq.yzfl@gmail.com>
Reviewed-by: Marcin Bukat <marcin.bukat@gmail.com>
This patch adds to YP-R0 (and other future targets using Linux
framebuffer) the ability to use LCD_ENABLE to save some CPU cycles
while display is powered off.
This patch also changes the way to toggle LCD power: now using
a proper ioctl call, slightly more efficient.
Change-Id: I544de77f5abd4ac1c13d3fe3a6e40a30f7c0bece
Reviewed-on: http://gerrit.rockbox.org/410
Reviewed-by: Thomas Martitz <kugel@rockbox.org>
The GPIO device file wasn't closed due to this. This wasn't a big deal
because the device powers off shorty afterwards anyway.
Change-Id: I9a6b4d57d32627157323b4883e47b8812f5dcb4d
As per title this patch aims at splitting common target
code and specific target code in a better way to
support future ports within the same environment
(e.g. Samsung YP-R1 where the Linux and the SoC
are the same, with differences in hardware devices
handling)
Change-Id: I67b4918c46403b184d3d8f42ab5aae7d01037fd0
Reviewed-on: http://gerrit.rockbox.org/409
Reviewed-by: Thomas Martitz <kugel@rockbox.org>
Tested-by: Thomas Martitz <kugel@rockbox.org>
commit_discard_dcache_range() is used in sd, lcd and pcm drivers
to handle transfers form/to data buffers so this should not introduce
any problems. It is reported to fix pop noise observed on some hifimans.
We apparently don't fully understand cache handling on this platform.
Change-Id: I436d291509f91d16a13d10965a28171fb27574ab
In commit_discard_idcache(), cache lines were marked as invalid. When
some cache lines are marked as invalid, memory corruption can occur.
This caused instability when using PP502x ATA DMA because of the many
more calls to that function. Here, commit_discard_idcache() is changed
to avoid the problem. Also, the cache is filled after being enabled to
to ensure there are never any cache lines that aren't marked as valid.
Change-Id: Ia26300acef6b0573c1f40299c496ee5cbda3dac8
Reviewed-on: http://gerrit.rockbox.org/339
Reviewed-by: Szymon Dziok <b0hoon@o2.pl>
Tested-by: Szymon Dziok <b0hoon@o2.pl>
Reviewed-by: Marcin Bukat <marcin.bukat@gmail.com>
The SD driver doesn't initialised drives at the beginning but
upon request to handle removable drives. Since means that the
init should call init_drive() and not init_sd_card() otherwise
the check for WINDOW flag is bypasses. This breaks the zenxfi3
bootloader and has been overlooked for some time.
Change-Id: I7325f7164d16d7e7e54eeb4645e98517a08e0836
Move to a table based approach (scales better) and distinguish
between upward changes (increase frequency) and downward changes
(decrease frequency). This provides a better ordering of
operations and in particular it allows to avoid changing the
regulator while running at low speed since it takes a long time !
This should result in a much smoother scaling.
Change-Id: Iad7e5b61277e215f31c07877fbbad07ddde1171f
For some reason it is the responsability of the driver to send
this event so do it. This might fix some non-updating screens.
Change-Id: Ib5fdc94bf266c3497a8ac4e89d0418c0e876ff9f
The lcd kind is always set to st7783 in case we can't read the ID
so don't bother handling impossible cases
Change-Id: I352fd43b26068b460e69190d37c4cd4627e1db9a
The flip and invert settings can potentially be reset to their
value accross a disable/enable cycle, so save the value of the
impacted registers and apply it after each enable. Also avoid
poking registers when the lcd is not on.
Change-Id: Ica98f166c060aade7eb205f5628b58aae692024f
When chaging the cpu and memory frequency we need to disable the
external memory interface (EMI) for a small time. This can
underflow the dma and cause some breakage. Hopefully the SSP
controller handles this gracefully by stopping the clock and the
I2C probably handles this naturally because the clock can be
streched anyway. However the LCDIF has a special setting for this
which needs to be enable, otherwise it will send garbage to the
LCD. No other block is known to suffer from this currently but
this issue might have more unexpected consequences.
Change-Id: Ide154cad87929f2bf6cc419ac1d2ff33e30eec66
The manual recommands to tweak the arm cache settings on frequency
changes. The meaning of these values is undocumented but 0 seems
to be a safe value for all frequencies whereas 3 seems to be valid
only for low frequencies (<=64MHz ?)
Change-Id: Iaa8db4af8191010789cf986b1139ff259d73e2ed
CPU frequency scaling is basically useless without scaling the
memory frequency. On the i.MX233, the EMI (external memory
interface) and DRAM blocks are responsable for the DDR settings.
This commits implements emi frequency scaling. Only some settings
are implemented and the timings values only apply to mDDR
(extracted from Sigmatel linux port) and have been checked to
work on the Fuze+ and Zen X-Fi2/3. This feature is still disabled
by default but I expected some battery life savings by boosting
higher to 454MHz and unboosting lower to 64MHz.
Note that changing the emi frequency is particularly tricky and
to avoid writing it entirely in assembly we rely on the compiler
to not use the stack except in the prolog and epilog (because
it's in dram which is disabled when doing the change) and to put
constant pools in iram which should always be true if the
compiler isn't completely dumb and since the code itself is put
in iram. If this proves to be insufficient, one can always switch
the stack to the irq stack since interrupts are disabled during
the change.
Change-Id: If6ef5357f7ff091130ca1063e48536c6028f23ba
