- Speed auto detection is launched when an accessory is inserted,
so the user doesn't need to modify settings to use accessories
that operates at different speeds (or when the same accessory is
unplugged and plugged again).
- UART controller is disabled when no accessory is inserted, not
much powersave but everything counts.
Change-Id: If20c3617c2a87b6277fd7e0270031030c44fa953
This change ensures that Sansa Connect bootloader.bin will fit in its flash
partition.
Fix _flash_sizem calculation, division was not working properly because
FLASHSIZE included subtraction and defined value was not in parenthesis.
Prior to this change _flash_sizem was 0x00800000, now it is correctly set
to 4 in case of Sansa Connect and 8 in case of other TMS320DM320 players.
This significantly improves boot time as cache is now enabled only for
real flash memory region.
Change-Id: If3e50a3075c840dcb69dfafe5bba608a0acd2bf8
PMU interrupts are used to detect USB Vbus, wall adaptor, accessories
and holdswitch. A thread is needed to poll the PMU throught I2C, ATM
it does nothing but showing the state of the inputs on the HW debug
menu, funcionallity for each individual input will be added in next
patches.
Change-Id: If93bf2044d1052729237a7fd1431c8493e09f1c7
Do not rely on a bootloader initializing the HW, RB initializes
and configures GPIO, I2C, and PMU at startup.
Change-Id: If7f856b1f345f63de584aa4e4fc22d130cd66c80
Low level functions that do not depend on Rockbox kernel,
intended to be used by the bootloader, dualboot-installer,
RB drivers or other .dfu tools.
Change-Id: If80214d26e505265ace19d9704f1e1300f98b2f4
When the bootloader starts, most of HW never has been initialized.
This patch includes all code needed to perform the preliminary
initialization on SYSCON, GPIO, i2c, and MIU.
The code is based on emCORE and OF reverse engineering, ported to
C for readability.
Change-Id: I9ecf2c3e8b1b636241a211dbba8735137accd05c
The write buffer size is undefined to use the default 24Kb. size
defined (and recomended) in usb_storage.c, the read buffer size is
also decremented to 24 Kb. USB sequential read and write benchmarks
using diskdump are now 8-9% faster.
Change-Id: Ia7c9f77b57c8ca5b566b508efffbd713d1587acf
This patch optimizes UDMA timings to increase write transfer rate on
ATA bus, these transfers are clocked by HCLK, tDVS+tDVH is modified to
decrease Tcyctyp (typical write cycle period). This is not overclocking,
we meet the ATA standar, the settings used by OF are not well optimized
for each UDMA mode, we will never know but probably this was due some
documentation issue.
ATA_UDMA_TIME register is documented on s3c6400 datasheet, information
included in s5l8700 datasheet is wrong or not valid for s5l8702.
From ATA specs, (Minimum, Maximum) values in nanoseconds:
UDMA 0 UDMA 1 UDMA 2 UDMA 3 UDMA 4
tACKENV (20, 70) (20, 70) (20, 70) (20, 55) (20, 55)
tRP (160, --) (125, --) (100, --) (100, --) (100, --)
tSS (50, --) (50, --) (50, --) (50, --) (50, --)
tDVS (70, --) (48, --) (31, --) (20, --) (6.7, --)
tDVH (6.2, --) (6.2, --) (6.2, --) (6.2, --) (6.2, --)
tDVS+tDVH (120, --) (80, --) (60, --) (45, --) (30, --)
Tcyc = tDVS+tDVH
WR[bytes/s] = 1/Tcyc[s] * 2[bytes]
On Classic (boosted):
HClk = 108 MHz. -> T = ~9.26 ns.
Old values (used by OF):
UDMA ATA_UDMA_TIME tACK tRP tSS tDVS tDVH Tcyc WR(MB/s)
0 0x5071152 27.8 166.7 55.6 74.1 55.6 129.7 15.4
1 0x3050a52 27.8 101.8 55.6 55.6 37 92.6 21.6
2 0x3030a52 27.8 101.8 55.6 37 37 74 27
3 0x2020a52 27.8 101.8 55.6 27.8 27.8 55.6 36
4 0x2010a52 27.8 101.8 55.6 18.5 27.8 46.3 43.2
New values:
UDMA ATA_UDMA_TIME tACK tRP tSS tDVS tDVH Tcyc WR(MB/s)
0 0x4071152 27.8 166.7 55.6 74.1 46.3 120.4 16.6
1 0x2050d52 27.8 129.6 55.6 55.6 27.8 83.4 24
2 0x2030a52 27.8 101.8 55.6 37 27.8 64.8 30.9
3 0x1020a52 27.8 101.8 55.6 27.8 18.5 46.3 43.2
4 0x1010a52 27.8 101.8 55.6 18.5 18.5 37 54
To verify that the settings are correct, a write-to-cache test was
performed using emCORE, the measured transfer rate (WRm) is compared
against the theoric transfer rate (WR) at 108 Mhz for the old and
the new UDMA4 settings (iPod 160, HDD Toshiba MK1634GAL):
UDMA ATA_UDMA_TIME Tcyc(ns) WR(MB/s) WRm(MB/s) RDm(MB/s)
4 0x2010a52 46.3 43.2 42.9 59.8
4 0x1010a52 37 54 53.5 59.8
Notes:
- The new UDMA4 settings increases ~25% the ATA transfer rate for
cached-writes. The real HDD write speed is limited by the internal
transfer rate (depends on cilinder, for the MK1634GAL it is 276 to
573 Mbits/s). Sequential write benchmark using diskdump on USB are
~8% faster.
- Read transfers are clocked by the device, it depends on UDMA mode
selected and are not affected by HClk or ATA_UDMA_TIME settings.
Read-from-cache tests results (RDm) using HClk=108 and HClk=54 for
UDMA4 are 59.8 MB/s on MK1634GAL.
- Minimum HClk is limited by tACKENV specs, using current settings
it is 54 MHz for UDMA4,UDMA3 and 43 MHz for UDMA2,UDMA1,UDMA0.
Change-Id: I61d67060410752518a59e1ff08072b21747ca997
When the bootloader starts only IRAM is available, the first task is to
ask the PMU to verify if the iPod has previously been hibernated by OF.
Due to memory limitations, the kernel cannot be used on this stage.
This patch modifies I2C and PMU low level functions to not to depend
on kernel (removes mutexes, and uses HW timer instead of current_tick),
actual kernel functions are modified to be 'mutexed' wrappers of the new
functions.
Change-Id: I7cef9e95dedaf176dc0659315f3dc33166d5b116
The kernel on this device reports nonexistent key presses, in particular it
reports right presses when pressing the left button... Since when it happens,
the right press comes after the left one, the new code simply ignores any
right press when the left button in pressed.
Change-Id: Ib6ced02682d9cecf4c7f6c58834907a667419cd7
Add UART support for s5l8700/1 using the UC870X UART controller,
actually the functionallity is disabled and must be enabled for
each individual target. Tested on iPod Nano 2G (s5l8701), not
tested on s5l8700.
Change-Id: Ic0f216bb871502d355a70e4b658e536a2c0976a9
- Small rework on the UC8702 UART controller to make it compatible with
other s5l870x SOCs. Files moved and renamed, many conditional code
added to deal with capabilities and 'features' of the different CPUs.
- A couple of optimizacions that should not affect the functionality.
Change-Id: I705169f7e8b18d5d1da642f81ffc31c4089780a6
With this changes rockbox can be loaded from SD card when internal storage
can't be mount (due to hardware or software problem).
Change-Id: I32b20d3f341566364def747a708a54ba6b4a7f8b
Interrupts version is cause of freeze on USB extraction.
Also non-interrupts version much simpler and faster.
Change-Id: I30a2993cdcaa85abfba77ca06bfacd5b6b4353e2
Fix log file corruption if we have new messages at dumping log to file. Comment
removed as it incorrect. We store all messages in direct order (last message at
end of file).
Change-Id: I4acfa8a0935cc41a889e08f6bc42974fefd1ade2
Voltage is reduced when the CPU is unboosted, resulting in a large
reduction in power consumption. In analogy with the AMSv1 voltage
scaling code (currently disabled due to problems with SD cards),
I have defined a config file option to enable/disable it.
Change-Id: Ia89c31ec06dd012354b4d53435e7b5b36243b206
We need additional delay since ascodec_write_pmu() working faster in
non-interrupts version of I2C2.
Change-Id: If4af3e42b3c8e8214baa36e54353b8adb527552d
After setting new PCLK (96 Mhz) we have too high DBOP (96 / 16 = 6 MHz).
According to datasheet DBOP should be maximum 4 MHz.
Change-Id: I1cbec054f41a76a6f18eadccb902c5b174ad6e3a
We should check sd_wait_for_tran_state() after transfering to prevent data
timeout error. Also we should disable DMA channel manually.
Should be used with g#1270, without it freezes still can occur on data
transfering.
Change-Id: If8c6e5547ab14d66237bccf65f83affc7a346e5e
With current setting we spend few minutes for reading one sector if we have
data timeout error. With new setting system (linux) show error after ~10 seconds.
Change-Id: Id3922acb2ea146c6ea2f89f26206df9488e6ee4e
This should allow FireWire charging to work on these devices.
It also adds charging state detection on the iPod Classic.
(cherry picked from commit fa86fec4fb)
On Classic (and probably Nano 2G), it seems that the 100/500mA limit
applies only to USB chargers, when FW is connected it supplies all the
power (even if USB is also connected) and USB current limit does not
affect to FW charging, therefore the limit is only set when USB is
connected.
Change-Id: I7c6bab1b6a0f295367999c45faeda6085c3fb091
Signed-off-by: Cástor Muñoz <cmvidal@gmail.com>
Read/write buffers who are aligned to 16 were not re-aligned to 32 as
it should be. Althrough USB storage and buffering are always passing
buffers aligned to 32, a few unaligned buffers are being received from
other tasks, so this patch could solve some rare random issues.
Also fixes DMA configuration for HDDs that support any MDMA mode but
only UDMA0 (probably will never happen).
Change-Id: I00219ae434205681c69293fc563e0526224c9adf
- Add description for attributes supported by Samsung HS081HA (80Gb)
and HS161JQ (CEATA 160Gb).
- Show error code when ata_read_smart() fails.
Change-Id: I618cc4f37d139fc90f596e2cf3a751346b27deb6
After previous commit 0b6647f2e9
this alignment should not be needed, but not sure at all, so it
is aligned to cache line length for safety.
Change-Id: I5b2b9a30c913d2a609acc1bdf30bdec6811a2551
Align USB_DEVBSS buffers to 32 (as other USB drivers are doing), this
could solve rare random memory corruption issues on iPod Classic.
Change-Id: I86a28e10415eabedab7bf4a534530900284f81e5
Some old code made the assumption that CONFIG_CPU == AS3525v2 if and only if
HAVE_AS3543, which is not true on targets like the Samsung YP-R0. This fixes
several issues on such targets like a huge volume gap between -39dB and -40dB
and a volume artificially capped at -72dB instead of -82dB.
Change-Id: Ib1c883ac593c0c3ce5e2bf4eb408924ce5f5ad93
Reverts commit ead38dbc9d
It was introduced as a temporal workaround to avoid the endless restart
loop when battery is low, but really it is useless. The bootloader should
ensure that there is enough power to launch Rockbox even in the worst
scenario.
Change-Id: Iabebed40c9241af915c16c3c6c4d3c6deef7680e
seems more logical to me, and is more consistent, since
"SAMSUNG_YH92X_PAD" is already used in the tex files.
Change-Id: Ie9a9d850ea86155a7dcf86c88a22a420a10a3837
Voltage scaling is not yet enabled, but will follow once we are sure
these changes are stable. Preliminary testing suggests a large
increase in battery life, which will be further improved by voltage
scaling. Patch by Mihail Zenkov with help from myself and others on
the forums.
Change-Id: I171d20bbee19a48c13cd14efb0d023883cc8c687
Configures uncached memory region and adds some defines for misc HW,
for compability with the bootloader and other future use, current
functionality should not be affected.
Change-Id: I390e79bea1aef5b10dfbc72ad327d7fe438ec6f5
Uses GPIO.E2 (Request To Send) to detect the holdswitch status,
it is a temporal workaround that seems to work on all models.
Holdswitch status must be detected to drive low GPIO.E2 (RTS)
and GPIO.E4 (Data Out) when the holdswitch is locked, otherwise
battery life decreases about 25%.
Holdswitch unlock action is detected by reading the HELLO message
that the external wheel controller sends when it is powered on,
this allows to quickly capture clickwheel activity after unlock.
GPIO.E2 is also used in case the HELLO message is missed because
the holdswitch was unlocked before Rockbox/bootloader starts.
These 2 lines (RTS and DOUT) can not be used to transmit messages
to the external clickwheel controller, not a problem, actually no
messages are sent while normal operation, only at initialization
stage.
Change-Id: I415fe54bfcbc2086d0f56d7affe6f789ce81a6db
This is a rewrite of the clocking section, the resulting system
frequencies are the same as the current git version.
This pàtch uses fixed FClk and just one register is written to switch
all system frequencies, it needs less steps than the current git
version to reach the desired frequency, so it is faster and safer.
Includes functions to step-up/down over a table of predefined set of
frequencies.
The major difference is that Vcore is decreased from 1050 to 1000 mV.
See clocking-s5l8702.h for more information.
Change-Id: I58ac6634e1996adbe1c0c0918a7ce94ad1917d8e
The main "innovation" in this patch are two "virtual buttons"
for the record switch on YH92x targets. When the switch state
changes, a single BUTTON_REC_SW_ON or .._OFF button event will
be generated. Thus keymap code can react on switching, but
not on the actual state of the switch.
Wherever sensible, the following user scheme is applied:
- use PLAY as confirm button
- use REW button or Long REW to exit
- use REC (YH820) or FFWD (YH92X) as modifier key for button combos
Change-Id: Ic8d1db9cc6869daed8dda98990dfdf7f6fd5d5a1
Adds ata_read_smart() function to storage ATA driver, current
SMART data can be displayed and optionally written to hard
disk using System->Debug menu.
Change-Id: Ie8817bb311d5d956df2f0fbfaf554e2d53e89a93
This patch limits the drawn USB current to 100/500mA, instead of
the actual 200/1000mA settings. It also initializes other USB power
related GPIOs.
Solves some USB disconnect issues: FS#12990, FS#12956. I am using a
powered USB HUB with no problems (Vusb=5.05V unloaded), but there
are lots of USB disconnects when using the motherboard USB ports
(Vusb=4.91V), this patch solves all my issues.
Actually, it seems that the USB current drain is limited to 1000mA,
when a load peak occurs most USB2 ports deliver more than 500mA, as
current consumption increases the USB voltage decreases, an excesive
voltage drop produces USB disconnections. Limiting USB current drain
to 500mA also limits the voltage drop, preventing subsequent USB
failures.
Anyway, to minimize voltage drop, it is recommended to use quality
cables and preferably connect to USB ports with higher Vusb.
Change-Id: I1b931aa18ec93bfd1214e475a72e42893eff52f6
- polling/IRQ modes for Tx/Rx (TODO?: DMA)
- fine adjust for Tx/Rx bitrates
- auto bauding using HW circuitry
- status and stats in debug screen
Change-Id: I8650957063bc6d274d92eba2779d93ae73453fb6
This patch has been tested on iPod 80 and 160slim, actually
it works but some updates must be done to the final version:
- unlimitted input buffer
- decrease CHUNK_SIZE
- use non-cached addresses instead of discard d-cache ???
Capture hardware versions:
Ver iPod models capture support
--- ----------- ---------------
0 80/160fat dock line-in
1 120/160slim dock line-in + jack mic
HW version 1 includes an amplifier for the jack plug mic.
Capture HW detection only tested on iPod 80 and 160slim.
CODEC power:
AFAIK, OF powers CS42L55 at VA=2.4V for capture (1.8V for
playback) and turns on the ADC charge pump. CODEC datasheet
recommmends to disable the charge pump for VA>2.1V.
CS42L55 DS, s4.13 (Required Initialization Settings): for
VA>2.1V, some adjustments "must" be done using undocummented
"control port compensation" registers. OF does not modifies
these registers when VA=2.4V.
This patch configures capture HW in the same way as OF does.
TODO:
- ADC full scale voltage depends on VA, perform tests to find
clipping levels for VA=1.8V and VA=2.4V
Change-Id: I7e20fd3ecaa83b1c58d5c746f5153fe5c3891d75
There are a couple of power saving options that can be selected using
defines, they configure the CODEC in a different way than OF does:
MONO_MIC: jack microphone is connected to left channel, disabling
right channel saves ~1 mW, there is no reason to not to do it.
BYPASS_PGA: this option only applies to the line-in, OF does not
bypass the PGA and configures it to 0 dB gain. At the beginning,
this patch was written based on CODEC datasheet, bypassing PGA
because it saves power and incrementes dinamic range ~1dB, i have
used this setup for a while without problems. Finally this option
was disabled at the last minute, i decided to do it after reviewing
the OF and realizing that CS42L55 datasheet recommends to bypass the
PGA only if the HW includes a couple of capacitors (see Typical
Connection Diagram, Note 4), at this moment i don't know if Classic
includes these capacitors (probably not). Anyway, i am not able to
tell the difference listening to voice recodings.
TODO:
- Use variable PGA gain for jack microphone (it is fixed to +12 dB.
as OF does).
- I am not a fan of having lots of unused #define options, these could
be useful for a generic driver but actually this driver is Classic
oriented, i am not sure if it could be considered disirable to
eliminate them in the final version.
Change-Id: I3dadf2341f44d5e13f3847e6c9de4a76cd6f0918
This patch uses the new pl080 DMA driver for I2S playback and LCD
update. I have tried to be as fiel as possible to the current
behaviour, algorithms and configurations are the same, but using
the new driver. Other modifications:
Playback:
- CHUNK_SIZE is decreased from 42988 to 8188 bytes, it does not
affect normal playback (block size 1024), was tested using
metronome (block size 46080). This change is needed because the
new code commits d-cache range instead of commiting the whole
d-cache, maximum time spent commiting the range should be
limited, CHUNK_SIZE can be decreased even more if necessary.
- pcm_play_dma_start() calls pcm_play_dma_stop() to stop the
channel when it is running (metronome replays the tick sound
without stopping the channel).
- pcm_play_dma_get_peak_buffer(): same as actual SVN function but
returns samples count instead of bytes count.
TODO: AFAIK, actually this function is not used in RB. Not tested,
but probably this function will fail because it returns pointers
to the internal double buffer.
LCD update:
- suppresses lcd_wakeup semaphore and uses yield()
Change-Id: I79b8aa47a941e0dd91847150618f3f7f676c26ef
Motivation:
This driver began as a set of functions to help to test and
experiment with different DMA configurations. It is cumbersome,
time consuming, and leads to mistakes to handle LLIs and DMA
registers dispersed along the code.
Later, i decided to adapt an old DMA queue driver written in the
past for a similar (scatter-gather) controller, all task/queue
code is based on the old driver.
Finally, some cleaning and dmac_ch_get_info() function was added
to complete RB needs.
Description:
- Generic, can be used by other targets including the same
controller. Not difficult to adapt for other similar
controllers if necesary.
- Easy to experiment and compare results using different
setups and/or queue algorithms:
Multi-controller and fully configurable from an unique place.
All task and LLI management is done by the driver, user only
has to (statically) allocate them.
- Two queue modes:
QUEUE_NORMAL: each task in the queue is launched using a new
DMA transfer once previous task is finished.
QUEUE_LINK: when a task is queued, it is linked with the last
queued task, creating a single continuous DMA transfer. New
tasks must be queued while the channel is running, otherwise
the continuous DMA transfer will be broken.
On Classic, QUEUE_LINK mode is needed for I2S continuous
transfers, QUEUE_NORMAL is used for LCD and could be useful
in the future for I2C or UART (non-blocking serial debug) if
necessary.
- Robust DMA transfer progress info (peak meter), needs final
testing, see below.
Technical details about DMA progress:
There are comments in the code related to the method actually
used (sequence method), it reads progress without halting the
DMA transfer. Althought the datasheet does not recommend to do
that, the sequence method seems to be robust, I ran tests calling
dmac_ch_get_info() millions of times and the results were always
as expected (tests done at 2:1 CPU/AHB clock ratio, no other
ratios were tried but probably sequence method will work for any
typical ratio).
This controller allows to halt the transfer and drain the DMAC
FIFO, DMA requests are ignored when the DMA channel is halted.
This method is not suitable for playback because FIFO is never
drained to I2S peripheral (who raises the DMA requests). This
method probably works for capture, the FIFO is drained to memory
before halting.
Another way is to disable (stop) the playback channel. When the
channel is disabled, all FIFO data is lost. It is unknown how much
the FIFO was filled when it was cleared, SRCADDR counter includes
the lost data, therefore the only useful information is LINK and
COUNT, that is the same information disponible when using the
sequence method. At this point we must procced in the same way as
in sequence method, in addition the playback channel should be
relaunched (configure + start) after calculating real SRCADDR.
The stop+relaunch method should work, it is a bit complicated,
and not valid for all peripheral FIFO configurations (depending
on stream rate). Moreover, due to the way the COUNT register is
implemented in HW, I suspect that this method will fail when
source and destination bus widths doesn't match. And more
important, it is not easy to garantize that no sample is lost
here or there, using the sequence method we can always be sure
that playback is ok.
Change-Id: Ib12a1e2992e2b6da4fc68431128c793a21b4b540
This patch implements a simple API to use the external interrupt
hardware present on s5l8702 (GPIO interrupt controller). This
GPIOIC has been fully tested using emcore apps.
Code is based on openiBoot project, there are a few modifications
to optimize space considering we will only use two or three external
interrupts. The API compiles and works, but has been never used,
therefore probably will need some changes to the final version.
External interrupts are necessary for jack remote+mic controller
(see iAP Interface Specifiction: Headphone Remote and Mic System),
this controller is located at I2C bus address 0x72, there is a IRQ
line for remote button press/release events routed to GPIO E6. At
this moment, the functionallity of this controller has been
extensively tested using emcore, getting a lot of information about
how it works. Microphone is already working on RB, jack accessory
detection and button events are work in progress.
PMU IRQ line is also routed to GPIO F3, it signals many events:
holdswitch, usb plug, wall adapter, low battery... The use of PMU
interrupts is the orthodox way of doing things, at this moment
there is no work done in this direction, there are a lot of PMU
events and i think it is a matter of discursion what to do and how.
Change-Id: Icc2e48965e664ca56c9518d84a81c9d9fdd31736
It was possible for interrupts of higher priority than the current IRQ
level to attempt to restart the interface while it was still active on
a transfer. The list modification also wasn't protected within the I2C
ISR itself.
Change-Id: I70635c307a1443bba6801c588cf1efde299db9a4
