Commit graph

17 commits

Author SHA1 Message Date
Aidan MacDonald
3ec66893e3 New port: FiiO M3K on bare metal
Change-Id: I7517e7d5459e129dcfc9465c6fbd708619888fbe
2021-03-28 00:01:37 +00:00
Aidan MacDonald
fb99d890a8 Fix typo in MIPS cache discard
Change-Id: I6a06e5f3098324d985bd59322755cd68122ec0bf
2021-03-04 19:39:28 +00:00
Solomon Peachy
cbace906c6 mips: Revert to commiting the cache when we're told to discard an unaligned block.
The filesystem API often passes in unaligned receive buffers, and some
code (eg BMP reader) processes data in-place, leading to data loss when
we dropped the cache.

(And document exactly what we're doing, so we don't go through this again
 at $future_date)

Change-Id: If47a7f2148a5a1a43777f0bd3be1bdfe8239e91e
2021-03-04 12:00:15 -05:00
Aidan MacDonald
de53965e3f Third try fixing MIPS cache code
Changing this to be a pure discard operation after discussion on IRC

Change-Id: I62955ae7975fdbbfd9eef376476042a36fe3d95a
2021-03-04 02:47:13 +00:00
Aidan MacDonald
8cb4c18310 Really fix the MIPS cache bug this time
In fixing the original bug I tried to optimize discard_dcache_range()
to minimize writeback and inadvertently introduced a second bug, which
typically ends in a TLB refill panic.

It occurs only if the range fits within one cache line, and when both
the start and end of the range are not aligned to a cache line. This
causes ptr to be incremented and end to be decremented, so ptr > end,
and the loop can't terminate.

Change-Id: Ibaac072f1369268d3327d534ad08ef9dcee3db65
2021-03-03 23:57:08 +00:00
Aidan MacDonald
74a3d1f5be Fix MIPS cache operations and enable HAVE_CPU_CACHE_ALIGN on MIPS
- The range-based cache operations on MIPS were broken and only worked
  properly when BOTH the address and size were multiples of the cache
  line size. If this was not the case, the last cache line of the range
  would not be touched!

  Fix is to align start/end pointers to cache lines before iterating.

- To my knowledge all MIPS processors have a cache, so I enabled
  HAVE_CPU_CACHE_ALIGN by default. This also allows mmu-mips.c to use
  the CACHEALIGN_UP/DOWN macros.

- Make jz4760/system-target.h define its cache line size properly.

Change-Id: I1fcd04a59791daa233b9699f04d5ac1cc6bacee7
2021-03-03 20:50:28 +00:00
Solomon Peachy
d015165bc5 mips: Convert 'nop' to 'ssnop' -- for future-proofing
Change-Id: I17625f4d56a1f5205887cb47668a2dcb628053f4
2020-09-05 22:18:26 +00:00
Solomon Peachy
0cb162a76b mips: Heavily rework DMA & caching code
Based on code originally written by Amaury Pouly (g#1789, g#1791, g#1527)
but rebased and heavily updated.

Change-Id: Ic794abb5e8d89feb4b88fc3abe854270fb28db70
2020-09-03 15:34:28 -04:00
William Wilgus
3867f0b959 XduooX3 Sources WS changes
Change-Id: I17ae59e7ef0440756527ce50ab30f8bf34f79007
2020-08-29 10:14:03 -04:00
Solomon Peachy
0662793ca0 Add cleaned-up xDuoo X3 support
Cleaned up, rebased, and forward-ported from the xvortex fork.

(original credit to vsoftster@gmail.com)

Change-Id: Ibcc023a0271ea81e901450a88317708c2683236d
Signed-off-by: Solomon Peachy <pizza@shaftnet.org>
2018-07-28 10:56:31 -04:00
Michael Sevakis
6a67707b5e Commit to certain names for cache coherency APIs and discard the aliases.
Wouldn't surprise me a bit to get some non-green.


git-svn-id: svn://svn.rockbox.org/rockbox/trunk@31339 a1c6a512-1295-4272-9138-f99709370657
2011-12-17 07:27:24 +00:00
Andree Buschmann
5d849a963e Clean up multiple definitions of RAM size. Remove -DMEM (make) and MEM (code), use the already defined MEMORYSIZE instead.
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@29189 a1c6a512-1295-4272-9138-f99709370657
2011-02-02 17:43:32 +00:00
Thomas Martitz
637bb2e608 Also rename cpucache_invalidate() function for mips. There's more in the target tree of mips which I have overlooked yesterday.
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@28057 a1c6a512-1295-4272-9138-f99709370657
2010-09-09 16:41:03 +00:00
Maurus Cuelenaere
48203093ce Fix RoLo on MIPS targets
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@21185 a1c6a512-1295-4272-9138-f99709370657
2009-06-04 11:57:43 +00:00
Maurus Cuelenaere
4532d145f1 Onda VX747:
* Add preliminary keymap
 * Split up generic MIPS stuff from Ingenic specific
 * Make apps/ compilable
 * Add SD driver
 * Fix RTC driver
 * Add debug screen
 * Other cleanups/rewrites/fixes


git-svn-id: svn://svn.rockbox.org/rockbox/trunk@19993 a1c6a512-1295-4272-9138-f99709370657
2009-02-13 00:45:49 +00:00
Maurus Cuelenaere
9b13a5d151 MIPS:
* Add assembly optimised variants for memcpy, memset and find_first_set_bit
 * Add option to map_address in MMU to set caching algorithm


git-svn-id: svn://svn.rockbox.org/rockbox/trunk@19920 a1c6a512-1295-4272-9138-f99709370657
2009-02-04 17:33:19 +00:00
Maurus Cuelenaere
29b136b82d Onda VX747:
* Get USB working (it isn't good at writing support though)
  * Clean up NAND & SD a bit
  * Other comments/fixes
Ingenic Jz4740/MIPS:
  * Split MMU from system


git-svn-id: svn://svn.rockbox.org/rockbox/trunk@19815 a1c6a512-1295-4272-9138-f99709370657
2009-01-21 20:58:33 +00:00