Move PortalPlayer system.c code into the target tree.
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@13239 a1c6a512-1295-4272-9138-f99709370657
This commit is contained in:
Barry Wardell
parent
0a643b8d90
commit
f43e50dc53
4 changed files with 448 additions and 386 deletions
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@ -282,6 +282,11 @@ target/arm/pnx0101/i2c-pnx0101.c
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target/arm/pnx0101/system-pnx0101.c
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#endif
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#if defined(CPU_PP)
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#if CONFIG_CPU == PP5002
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target/arm/system-pp5002.c
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#elif (CONFIG_CPU == PP5020) || (CONFIG_CPU == PP5024)
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target/arm/system-pp502x.c
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#endif
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#ifdef BOOTLOADER
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target/arm/crt0-pp-bl.S
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#else
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@ -201,391 +201,5 @@ void UIE(unsigned int pc, unsigned int num)
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}
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}
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#if CONFIG_CPU==PP5020 || CONFIG_CPU==PP5024
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unsigned int ipod_hw_rev;
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#ifndef BOOTLOADER
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extern void TIMER1(void);
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extern void TIMER2(void);
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#if defined(IPOD_MINI) /* mini 1 only, mini 2G uses iPod 4G code */
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extern void ipod_mini_button_int(void);
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void irq(void)
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{
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if(CURRENT_CORE == CPU)
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{
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if (CPU_INT_STAT & TIMER1_MASK)
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TIMER1();
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else if (CPU_INT_STAT & TIMER2_MASK)
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TIMER2();
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else if (CPU_HI_INT_STAT & GPIO_MASK)
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ipod_mini_button_int();
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} else {
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if (COP_INT_STAT & TIMER1_MASK)
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TIMER1();
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else if (COP_INT_STAT & TIMER2_MASK)
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TIMER2();
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else if (COP_HI_INT_STAT & GPIO_MASK)
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ipod_mini_button_int();
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}
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}
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#elif (defined IRIVER_H10) || (defined IRIVER_H10_5GB) || defined(ELIO_TPJ1022) \
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|| (defined SANSA_E200)
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/* TODO: this should really be in the target tree, but moving it there caused
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crt0.S not to find it while linking */
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/* TODO: Even if it isn't in the target tree, this should be the default case */
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void irq(void)
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{
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if(CURRENT_CORE == CPU)
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{
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if (CPU_INT_STAT & TIMER1_MASK)
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TIMER1();
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else if (CPU_INT_STAT & TIMER2_MASK)
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TIMER2();
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} else {
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if (COP_INT_STAT & TIMER1_MASK)
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TIMER1();
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else if (COP_INT_STAT & TIMER2_MASK)
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TIMER2();
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}
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}
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#else
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extern void ipod_4g_button_int(void);
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void irq(void)
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{
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if(CURRENT_CORE == CPU)
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{
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if (CPU_INT_STAT & TIMER1_MASK)
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TIMER1();
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else if (CPU_INT_STAT & TIMER2_MASK)
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TIMER2();
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else if (CPU_HI_INT_STAT & I2C_MASK)
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ipod_4g_button_int();
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} else {
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if (COP_INT_STAT & TIMER1_MASK)
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TIMER1();
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else if (COP_INT_STAT & TIMER2_MASK)
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TIMER2();
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else if (COP_HI_INT_STAT & I2C_MASK)
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ipod_4g_button_int();
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}
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}
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#endif
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#endif /* BOOTLOADER */
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/* TODO: The following two function have been lifted straight from IPL, and
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hence have a lot of numeric addresses used straight. I'd like to use
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#defines for these, but don't know what most of them are for or even what
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they should be named. Because of this I also have no way of knowing how
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to extend the funtions to do alternate cache configurations and/or
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some other CPU frequency scaling. */
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#ifndef BOOTLOADER
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static void ipod_init_cache(void)
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{
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/* Initialising the cache in the iPod bootloader prevents Rockbox from starting */
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unsigned i;
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/* cache init mode? */
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CACHE_CTL = CACHE_INIT;
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/* PP5002 has 8KB cache */
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for (i = 0xf0004000; i < 0xf0006000; i += 16) {
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outl(0x0, i);
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}
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outl(0x0, 0xf000f040);
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outl(0x3fc0, 0xf000f044);
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/* enable cache */
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CACHE_CTL = CACHE_ENABLE;
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for (i = 0x10000000; i < 0x10002000; i += 16)
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inb(i);
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}
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#endif
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/* Not all iPod targets support CPU freq. boosting yet */
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#ifdef HAVE_ADJUSTABLE_CPU_FREQ
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void set_cpu_frequency(long frequency)
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{
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unsigned long postmult;
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# if NUM_CORES > 1
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/* Using mutex or spinlock isn't safe here. */
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while (test_and_set(&boostctrl_mtx.locked, 1)) ;
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# endif
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if (frequency == CPUFREQ_NORMAL)
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postmult = CPUFREQ_NORMAL_MULT;
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else if (frequency == CPUFREQ_MAX)
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postmult = CPUFREQ_MAX_MULT;
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else
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postmult = CPUFREQ_DEFAULT_MULT;
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cpu_frequency = frequency;
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/* Enable PLL? */
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outl(inl(0x70000020) | (1<<30), 0x70000020);
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/* Select 24MHz crystal as clock source? */
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outl((inl(0x60006020) & 0x0fffff0f) | 0x20000020, 0x60006020);
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/* Clock frequency = (24/8)*postmult */
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outl(0xaa020000 | 8 | (postmult << 8), 0x60006034);
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/* Wait for PLL relock? */
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udelay(2000);
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/* Select PLL as clock source? */
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outl((inl(0x60006020) & 0x0fffff0f) | 0x20000070, 0x60006020);
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# if defined(IPOD_COLOR) || defined(IPOD_4G) || defined(IPOD_MINI) || defined(IRIVER_H10) || defined(IRIVER_H10_5GB)
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/* We don't know why the timer interrupt gets disabled on the PP5020
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based ipods, but without the following line, the 4Gs will freeze
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when CPU frequency changing is enabled.
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Note also that a simple "CPU_INT_EN = TIMER1_MASK;" (as used
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elsewhere to enable interrupts) doesn't work, we need "|=".
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It's not needed on the PP5021 and PP5022 ipods.
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*/
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/* unmask interrupt source */
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CPU_INT_EN |= TIMER1_MASK;
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COP_INT_EN |= TIMER1_MASK;
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# endif
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# if NUM_CORES > 1
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boostctrl_mtx.locked = 0;
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# endif
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}
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#elif !defined(BOOTLOADER)
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void ipod_set_cpu_frequency(void)
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{
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/* Enable PLL? */
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outl(inl(0x70000020) | (1<<30), 0x70000020);
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/* Select 24MHz crystal as clock source? */
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outl((inl(0x60006020) & 0x0fffff0f) | 0x20000020, 0x60006020);
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/* Clock frequency = (24/8)*25 = 75MHz */
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outl(0xaa020000 | 8 | (25 << 8), 0x60006034);
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/* Wait for PLL relock? */
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udelay(2000);
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/* Select PLL as clock source? */
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outl((inl(0x60006020) & 0x0fffff0f) | 0x20000070, 0x60006020);
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}
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#endif
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void system_init(void)
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{
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#ifndef BOOTLOADER
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if (CURRENT_CORE == CPU)
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{
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/* Remap the flash ROM from 0x00000000 to 0x20000000. */
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MMAP3_LOGICAL = 0x20000000 | 0x3a00;
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MMAP3_PHYSICAL = 0x00000000 | 0x3f84;
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/* The hw revision is written to the last 4 bytes of SDRAM by the
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bootloader - we save it before Rockbox overwrites it. */
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ipod_hw_rev = (*((volatile unsigned long*)(0x01fffffc)));
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/* disable all irqs */
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COP_HI_INT_CLR = -1;
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CPU_HI_INT_CLR = -1;
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HI_INT_FORCED_CLR = -1;
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COP_INT_CLR = -1;
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CPU_INT_CLR = -1;
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INT_FORCED_CLR = -1;
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# if NUM_CORES > 1 && defined(HAVE_ADJUSTABLE_CPU_FREQ)
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spinlock_init(&boostctrl_mtx);
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# endif
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#if (!defined HAVE_ADJUSTABLE_CPU_FREQ) && (NUM_CORES == 1)
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ipod_set_cpu_frequency();
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#endif
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}
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#if (!defined HAVE_ADJUSTABLE_CPU_FREQ) && (NUM_CORES > 1)
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else
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{
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ipod_set_cpu_frequency();
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}
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#endif
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ipod_init_cache();
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#endif
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}
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void system_reboot(void)
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{
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/* Reboot */
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DEV_RS |= DEV_SYSTEM;
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}
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int system_memory_guard(int newmode)
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{
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(void)newmode;
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return 0;
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}
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#elif CONFIG_CPU==PP5002
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unsigned int ipod_hw_rev;
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#ifndef BOOTLOADER
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extern void TIMER1(void);
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extern void TIMER2(void);
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void irq(void)
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{
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if(CURRENT_CORE == CPU)
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{
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if (CPU_INT_STAT & TIMER1_MASK)
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TIMER1();
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else if (CPU_INT_STAT & TIMER2_MASK)
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TIMER2();
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} else {
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if (COP_INT_STAT & TIMER1_MASK)
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TIMER1();
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else if (COP_INT_STAT & TIMER2_MASK)
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TIMER2();
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}
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}
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#endif
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unsigned int current_core(void)
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{
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if(((*(volatile unsigned long *)(0xc4000000)) & 0xff) == 0x55)
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{
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return CPU;
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}
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return COP;
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}
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/* TODO: The following two function have been lifted straight from IPL, and
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hence have a lot of numeric addresses used straight. I'd like to use
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#defines for these, but don't know what most of them are for or even what
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they should be named. Because of this I also have no way of knowing how
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to extend the funtions to do alternate cache configurations and/or
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some other CPU frequency scaling. */
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#ifndef BOOTLOADER
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static void ipod_init_cache(void)
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{
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int i =0;
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/* Initialising the cache in the iPod bootloader prevents Rockbox from starting */
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outl(inl(0xcf004050) & ~0x700, 0xcf004050);
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outl(0x4000, 0xcf004020);
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outl(0x2, 0xcf004024);
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/* PP5002 has 8KB cache */
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for (i = 0xf0004000; i < (int)(0xf0006000); i += 16) {
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outl(0x0, i);
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}
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outl(0x0, 0xf000f020);
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outl(0x3fc0, 0xf000f024);
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outl(0x3, 0xcf004024);
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}
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#endif
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#ifdef HAVE_ADJUSTABLE_CPU_FREQ
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void set_cpu_frequency(long frequency)
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{
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unsigned long postmult;
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if (CURRENT_CORE == CPU)
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{
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if (frequency == CPUFREQ_NORMAL)
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postmult = CPUFREQ_NORMAL_MULT;
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else if (frequency == CPUFREQ_MAX)
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postmult = CPUFREQ_MAX_MULT;
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else
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postmult = CPUFREQ_DEFAULT_MULT;
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cpu_frequency = frequency;
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outl(0x02, 0xcf005008);
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outl(0x55, 0xcf00500c);
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outl(0x6000, 0xcf005010);
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/* Clock frequency = (24/8)*postmult */
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outl(8, 0xcf005018);
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outl(postmult, 0xcf00501c);
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outl(0xe000, 0xcf005010);
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/* Wait for PLL relock? */
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udelay(2000);
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/* Select PLL as clock source? */
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outl(0xa8, 0xcf00500c);
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}
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}
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#elif !defined(BOOTLOADER)
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static void ipod_set_cpu_speed(void)
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{
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outl(0x02, 0xcf005008);
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outl(0x55, 0xcf00500c);
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outl(0x6000, 0xcf005010);
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#if 1
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// 75 MHz (24/24 * 75) (default)
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outl(24, 0xcf005018);
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outl(75, 0xcf00501c);
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#endif
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#if 0
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// 66 MHz (24/3 * 8)
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outl(3, 0xcf005018);
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outl(8, 0xcf00501c);
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#endif
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outl(0xe000, 0xcf005010);
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udelay(2000);
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outl(0xa8, 0xcf00500c);
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}
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#endif
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void system_init(void)
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{
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#ifndef BOOTLOADER
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if (CURRENT_CORE == CPU)
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{
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/* Remap the flash ROM from 0x00000000 to 0x20000000. */
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MMAP3_LOGICAL = 0x20000000 | 0x3a00;
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MMAP3_PHYSICAL = 0x00000000 | 0x3f84;
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ipod_hw_rev = (*((volatile unsigned long*)(0x01fffffc)));
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outl(-1, 0xcf00101c);
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outl(-1, 0xcf001028);
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outl(-1, 0xcf001038);
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#ifndef HAVE_ADJUSTABLE_CPU_FREQ
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ipod_set_cpu_speed();
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#endif
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}
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ipod_init_cache();
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#endif
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}
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void system_reboot(void)
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{
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outl(inl(0xcf005030) | 0x4, 0xcf005030);
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}
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int system_memory_guard(int newmode)
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{
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(void)newmode;
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return 0;
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}
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#endif /* CPU_ARM */
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#endif /* CONFIG_CPU */
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184
firmware/target/arm/system-pp5002.c
Normal file
184
firmware/target/arm/system-pp5002.c
Normal file
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@ -0,0 +1,184 @@
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/***************************************************************************
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* __________ __ ___.
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* Open \______ \ ____ ____ | | _\_ |__ _______ ___
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* Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
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* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
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* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
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* \/ \/ \/ \/ \/
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* $Id$
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*
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* Copyright (C) 2002 by Alan Korr
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*
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* All files in this archive are subject to the GNU General Public License.
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* See the file COPYING in the source tree root for full license agreement.
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*
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* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
|
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* KIND, either express or implied.
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*
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****************************************************************************/
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#include <stdio.h>
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#include "config.h"
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#include <stdbool.h>
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#include "lcd.h"
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#include "font.h"
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#include "system.h"
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#include "kernel.h"
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#include "thread.h"
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#include "timer.h"
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#include "inttypes.h"
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#include "string.h"
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unsigned int ipod_hw_rev;
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#ifndef BOOTLOADER
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extern void TIMER1(void);
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extern void TIMER2(void);
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|
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void irq(void)
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{
|
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if(CURRENT_CORE == CPU)
|
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{
|
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if (CPU_INT_STAT & TIMER1_MASK)
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TIMER1();
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else if (CPU_INT_STAT & TIMER2_MASK)
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TIMER2();
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} else {
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if (COP_INT_STAT & TIMER1_MASK)
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TIMER1();
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else if (COP_INT_STAT & TIMER2_MASK)
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TIMER2();
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}
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}
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#endif
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unsigned int current_core(void)
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{
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if(((*(volatile unsigned long *)(0xc4000000)) & 0xff) == 0x55)
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{
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return CPU;
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||||
}
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return COP;
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||||
}
|
||||
|
||||
|
||||
/* TODO: The following two function have been lifted straight from IPL, and
|
||||
hence have a lot of numeric addresses used straight. I'd like to use
|
||||
#defines for these, but don't know what most of them are for or even what
|
||||
they should be named. Because of this I also have no way of knowing how
|
||||
to extend the funtions to do alternate cache configurations and/or
|
||||
some other CPU frequency scaling. */
|
||||
|
||||
#ifndef BOOTLOADER
|
||||
static void ipod_init_cache(void)
|
||||
{
|
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int i =0;
|
||||
/* Initialising the cache in the iPod bootloader prevents Rockbox from starting */
|
||||
outl(inl(0xcf004050) & ~0x700, 0xcf004050);
|
||||
outl(0x4000, 0xcf004020);
|
||||
|
||||
outl(0x2, 0xcf004024);
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||||
|
||||
/* PP5002 has 8KB cache */
|
||||
for (i = 0xf0004000; i < (int)(0xf0006000); i += 16) {
|
||||
outl(0x0, i);
|
||||
}
|
||||
|
||||
outl(0x0, 0xf000f020);
|
||||
outl(0x3fc0, 0xf000f024);
|
||||
|
||||
outl(0x3, 0xcf004024);
|
||||
}
|
||||
|
||||
#endif
|
||||
|
||||
#ifdef HAVE_ADJUSTABLE_CPU_FREQ
|
||||
void set_cpu_frequency(long frequency)
|
||||
{
|
||||
unsigned long postmult;
|
||||
|
||||
if (CURRENT_CORE == CPU)
|
||||
{
|
||||
if (frequency == CPUFREQ_NORMAL)
|
||||
postmult = CPUFREQ_NORMAL_MULT;
|
||||
else if (frequency == CPUFREQ_MAX)
|
||||
postmult = CPUFREQ_MAX_MULT;
|
||||
else
|
||||
postmult = CPUFREQ_DEFAULT_MULT;
|
||||
cpu_frequency = frequency;
|
||||
|
||||
outl(0x02, 0xcf005008);
|
||||
outl(0x55, 0xcf00500c);
|
||||
outl(0x6000, 0xcf005010);
|
||||
|
||||
/* Clock frequency = (24/8)*postmult */
|
||||
outl(8, 0xcf005018);
|
||||
outl(postmult, 0xcf00501c);
|
||||
|
||||
outl(0xe000, 0xcf005010);
|
||||
|
||||
/* Wait for PLL relock? */
|
||||
udelay(2000);
|
||||
|
||||
/* Select PLL as clock source? */
|
||||
outl(0xa8, 0xcf00500c);
|
||||
}
|
||||
}
|
||||
#elif !defined(BOOTLOADER)
|
||||
static void ipod_set_cpu_speed(void)
|
||||
{
|
||||
outl(0x02, 0xcf005008);
|
||||
outl(0x55, 0xcf00500c);
|
||||
outl(0x6000, 0xcf005010);
|
||||
#if 1
|
||||
// 75 MHz (24/24 * 75) (default)
|
||||
outl(24, 0xcf005018);
|
||||
outl(75, 0xcf00501c);
|
||||
#endif
|
||||
|
||||
#if 0
|
||||
// 66 MHz (24/3 * 8)
|
||||
outl(3, 0xcf005018);
|
||||
outl(8, 0xcf00501c);
|
||||
#endif
|
||||
|
||||
outl(0xe000, 0xcf005010);
|
||||
|
||||
udelay(2000);
|
||||
|
||||
outl(0xa8, 0xcf00500c);
|
||||
}
|
||||
#endif
|
||||
|
||||
void system_init(void)
|
||||
{
|
||||
#ifndef BOOTLOADER
|
||||
if (CURRENT_CORE == CPU)
|
||||
{
|
||||
/* Remap the flash ROM from 0x00000000 to 0x20000000. */
|
||||
MMAP3_LOGICAL = 0x20000000 | 0x3a00;
|
||||
MMAP3_PHYSICAL = 0x00000000 | 0x3f84;
|
||||
|
||||
ipod_hw_rev = (*((volatile unsigned long*)(0x01fffffc)));
|
||||
outl(-1, 0xcf00101c);
|
||||
outl(-1, 0xcf001028);
|
||||
outl(-1, 0xcf001038);
|
||||
#ifndef HAVE_ADJUSTABLE_CPU_FREQ
|
||||
ipod_set_cpu_speed();
|
||||
#endif
|
||||
}
|
||||
ipod_init_cache();
|
||||
#endif
|
||||
}
|
||||
|
||||
void system_reboot(void)
|
||||
{
|
||||
outl(inl(0xcf005030) | 0x4, 0xcf005030);
|
||||
}
|
||||
|
||||
int system_memory_guard(int newmode)
|
||||
{
|
||||
(void)newmode;
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
||||
259
firmware/target/arm/system-pp502x.c
Normal file
259
firmware/target/arm/system-pp502x.c
Normal file
|
|
@ -0,0 +1,259 @@
|
|||
/***************************************************************************
|
||||
* __________ __ ___.
|
||||
* Open \______ \ ____ ____ | | _\_ |__ _______ ___
|
||||
* Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
|
||||
* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
|
||||
* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
|
||||
* \/ \/ \/ \/ \/
|
||||
* $Id$
|
||||
*
|
||||
* Copyright (C) 2002 by Alan Korr
|
||||
*
|
||||
* All files in this archive are subject to the GNU General Public License.
|
||||
* See the file COPYING in the source tree root for full license agreement.
|
||||
*
|
||||
* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
|
||||
* KIND, either express or implied.
|
||||
*
|
||||
****************************************************************************/
|
||||
#include <stdio.h>
|
||||
#include "config.h"
|
||||
#include <stdbool.h>
|
||||
#include "lcd.h"
|
||||
#include "font.h"
|
||||
#include "system.h"
|
||||
#include "kernel.h"
|
||||
#include "thread.h"
|
||||
#include "timer.h"
|
||||
#include "inttypes.h"
|
||||
#include "string.h"
|
||||
|
||||
unsigned int ipod_hw_rev;
|
||||
|
||||
#ifndef BOOTLOADER
|
||||
extern void TIMER1(void);
|
||||
extern void TIMER2(void);
|
||||
|
||||
#if defined(IPOD_MINI) /* mini 1 only, mini 2G uses iPod 4G code */
|
||||
extern void ipod_mini_button_int(void);
|
||||
|
||||
void irq(void)
|
||||
{
|
||||
if(CURRENT_CORE == CPU)
|
||||
{
|
||||
if (CPU_INT_STAT & TIMER1_MASK)
|
||||
TIMER1();
|
||||
else if (CPU_INT_STAT & TIMER2_MASK)
|
||||
TIMER2();
|
||||
else if (CPU_HI_INT_STAT & GPIO_MASK)
|
||||
ipod_mini_button_int();
|
||||
} else {
|
||||
if (COP_INT_STAT & TIMER1_MASK)
|
||||
TIMER1();
|
||||
else if (COP_INT_STAT & TIMER2_MASK)
|
||||
TIMER2();
|
||||
else if (COP_HI_INT_STAT & GPIO_MASK)
|
||||
ipod_mini_button_int();
|
||||
}
|
||||
}
|
||||
#elif (defined IRIVER_H10) || (defined IRIVER_H10_5GB) || defined(ELIO_TPJ1022) \
|
||||
|| (defined SANSA_E200)
|
||||
/* TODO: this should really be in the target tree, but moving it there caused
|
||||
crt0.S not to find it while linking */
|
||||
/* TODO: Even if it isn't in the target tree, this should be the default case */
|
||||
void irq(void)
|
||||
{
|
||||
if(CURRENT_CORE == CPU)
|
||||
{
|
||||
if (CPU_INT_STAT & TIMER1_MASK)
|
||||
TIMER1();
|
||||
else if (CPU_INT_STAT & TIMER2_MASK)
|
||||
TIMER2();
|
||||
} else {
|
||||
if (COP_INT_STAT & TIMER1_MASK)
|
||||
TIMER1();
|
||||
else if (COP_INT_STAT & TIMER2_MASK)
|
||||
TIMER2();
|
||||
}
|
||||
}
|
||||
#else
|
||||
extern void ipod_4g_button_int(void);
|
||||
|
||||
void irq(void)
|
||||
{
|
||||
if(CURRENT_CORE == CPU)
|
||||
{
|
||||
if (CPU_INT_STAT & TIMER1_MASK)
|
||||
TIMER1();
|
||||
else if (CPU_INT_STAT & TIMER2_MASK)
|
||||
TIMER2();
|
||||
else if (CPU_HI_INT_STAT & I2C_MASK)
|
||||
ipod_4g_button_int();
|
||||
} else {
|
||||
if (COP_INT_STAT & TIMER1_MASK)
|
||||
TIMER1();
|
||||
else if (COP_INT_STAT & TIMER2_MASK)
|
||||
TIMER2();
|
||||
else if (COP_HI_INT_STAT & I2C_MASK)
|
||||
ipod_4g_button_int();
|
||||
}
|
||||
}
|
||||
#endif
|
||||
#endif /* BOOTLOADER */
|
||||
|
||||
/* TODO: The following two function have been lifted straight from IPL, and
|
||||
hence have a lot of numeric addresses used straight. I'd like to use
|
||||
#defines for these, but don't know what most of them are for or even what
|
||||
they should be named. Because of this I also have no way of knowing how
|
||||
to extend the funtions to do alternate cache configurations and/or
|
||||
some other CPU frequency scaling. */
|
||||
|
||||
#ifndef BOOTLOADER
|
||||
static void ipod_init_cache(void)
|
||||
{
|
||||
/* Initialising the cache in the iPod bootloader prevents Rockbox from starting */
|
||||
unsigned i;
|
||||
|
||||
/* cache init mode? */
|
||||
CACHE_CTL = CACHE_INIT;
|
||||
|
||||
/* PP5002 has 8KB cache */
|
||||
for (i = 0xf0004000; i < 0xf0006000; i += 16) {
|
||||
outl(0x0, i);
|
||||
}
|
||||
|
||||
outl(0x0, 0xf000f040);
|
||||
outl(0x3fc0, 0xf000f044);
|
||||
|
||||
/* enable cache */
|
||||
CACHE_CTL = CACHE_ENABLE;
|
||||
|
||||
for (i = 0x10000000; i < 0x10002000; i += 16)
|
||||
inb(i);
|
||||
}
|
||||
#endif
|
||||
|
||||
/* Not all iPod targets support CPU freq. boosting yet */
|
||||
#ifdef HAVE_ADJUSTABLE_CPU_FREQ
|
||||
void set_cpu_frequency(long frequency)
|
||||
{
|
||||
unsigned long postmult;
|
||||
|
||||
# if NUM_CORES > 1
|
||||
/* Using mutex or spinlock isn't safe here. */
|
||||
while (test_and_set(&boostctrl_mtx.locked, 1)) ;
|
||||
# endif
|
||||
|
||||
if (frequency == CPUFREQ_NORMAL)
|
||||
postmult = CPUFREQ_NORMAL_MULT;
|
||||
else if (frequency == CPUFREQ_MAX)
|
||||
postmult = CPUFREQ_MAX_MULT;
|
||||
else
|
||||
postmult = CPUFREQ_DEFAULT_MULT;
|
||||
cpu_frequency = frequency;
|
||||
|
||||
/* Enable PLL? */
|
||||
outl(inl(0x70000020) | (1<<30), 0x70000020);
|
||||
|
||||
/* Select 24MHz crystal as clock source? */
|
||||
outl((inl(0x60006020) & 0x0fffff0f) | 0x20000020, 0x60006020);
|
||||
|
||||
/* Clock frequency = (24/8)*postmult */
|
||||
outl(0xaa020000 | 8 | (postmult << 8), 0x60006034);
|
||||
|
||||
/* Wait for PLL relock? */
|
||||
udelay(2000);
|
||||
|
||||
/* Select PLL as clock source? */
|
||||
outl((inl(0x60006020) & 0x0fffff0f) | 0x20000070, 0x60006020);
|
||||
|
||||
# if defined(IPOD_COLOR) || defined(IPOD_4G) || defined(IPOD_MINI) || defined(IRIVER_H10) || defined(IRIVER_H10_5GB)
|
||||
/* We don't know why the timer interrupt gets disabled on the PP5020
|
||||
based ipods, but without the following line, the 4Gs will freeze
|
||||
when CPU frequency changing is enabled.
|
||||
|
||||
Note also that a simple "CPU_INT_EN = TIMER1_MASK;" (as used
|
||||
elsewhere to enable interrupts) doesn't work, we need "|=".
|
||||
|
||||
It's not needed on the PP5021 and PP5022 ipods.
|
||||
*/
|
||||
|
||||
/* unmask interrupt source */
|
||||
CPU_INT_EN |= TIMER1_MASK;
|
||||
COP_INT_EN |= TIMER1_MASK;
|
||||
# endif
|
||||
|
||||
# if NUM_CORES > 1
|
||||
boostctrl_mtx.locked = 0;
|
||||
# endif
|
||||
}
|
||||
#elif !defined(BOOTLOADER)
|
||||
void ipod_set_cpu_frequency(void)
|
||||
{
|
||||
/* Enable PLL? */
|
||||
outl(inl(0x70000020) | (1<<30), 0x70000020);
|
||||
|
||||
/* Select 24MHz crystal as clock source? */
|
||||
outl((inl(0x60006020) & 0x0fffff0f) | 0x20000020, 0x60006020);
|
||||
|
||||
/* Clock frequency = (24/8)*25 = 75MHz */
|
||||
outl(0xaa020000 | 8 | (25 << 8), 0x60006034);
|
||||
/* Wait for PLL relock? */
|
||||
udelay(2000);
|
||||
|
||||
/* Select PLL as clock source? */
|
||||
outl((inl(0x60006020) & 0x0fffff0f) | 0x20000070, 0x60006020);
|
||||
}
|
||||
#endif
|
||||
|
||||
void system_init(void)
|
||||
{
|
||||
#ifndef BOOTLOADER
|
||||
if (CURRENT_CORE == CPU)
|
||||
{
|
||||
/* Remap the flash ROM from 0x00000000 to 0x20000000. */
|
||||
MMAP3_LOGICAL = 0x20000000 | 0x3a00;
|
||||
MMAP3_PHYSICAL = 0x00000000 | 0x3f84;
|
||||
|
||||
/* The hw revision is written to the last 4 bytes of SDRAM by the
|
||||
bootloader - we save it before Rockbox overwrites it. */
|
||||
ipod_hw_rev = (*((volatile unsigned long*)(0x01fffffc)));
|
||||
|
||||
/* disable all irqs */
|
||||
COP_HI_INT_CLR = -1;
|
||||
CPU_HI_INT_CLR = -1;
|
||||
HI_INT_FORCED_CLR = -1;
|
||||
|
||||
COP_INT_CLR = -1;
|
||||
CPU_INT_CLR = -1;
|
||||
INT_FORCED_CLR = -1;
|
||||
|
||||
# if NUM_CORES > 1 && defined(HAVE_ADJUSTABLE_CPU_FREQ)
|
||||
spinlock_init(&boostctrl_mtx);
|
||||
# endif
|
||||
|
||||
#if (!defined HAVE_ADJUSTABLE_CPU_FREQ) && (NUM_CORES == 1)
|
||||
ipod_set_cpu_frequency();
|
||||
#endif
|
||||
}
|
||||
#if (!defined HAVE_ADJUSTABLE_CPU_FREQ) && (NUM_CORES > 1)
|
||||
else
|
||||
{
|
||||
ipod_set_cpu_frequency();
|
||||
}
|
||||
#endif
|
||||
ipod_init_cache();
|
||||
#endif
|
||||
}
|
||||
|
||||
void system_reboot(void)
|
||||
{
|
||||
/* Reboot */
|
||||
DEV_RS |= DEV_SYSTEM;
|
||||
}
|
||||
|
||||
int system_memory_guard(int newmode)
|
||||
{
|
||||
(void)newmode;
|
||||
return 0;
|
||||
}
|
||||
Loading…
Reference in a new issue