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rk27load: stage1 dram config fix #2

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Change-Id: I5c4cf3dedab26e4cae05496bcae3a2d235d12e2f
This commit is contained in:
Marcin Bukat 2014-07-23 22:08:24 +02:00
parent dcd8172f4f
commit 345841aa56
1 changed files with 5 additions and 7 deletions
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12
utils/rk27utils/rk27load/stage1/main.S
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@ -70,18 +70,16 @@ row_loop:
str r7, [r0, #0x108] /* MCSDR_ADDCFG */
add r7, r5, #11 /* row_num_bits */
mov r7, r3, lsl r7 /* 1<<row_num_bits */
mla lr, r7, r6, r6 /* (1<<row_num_bits)*(1<<col_num_bits) +
* (1<<col_num_bits) (row1, col1 mem cell)
*/
mov lr, r3, lsl r7 /* 1<<row_num_bits */
mul lr, lr, r6 /* (1<<row_num_bits)*(1<<col_num_bits) */
mov r7, #0
str r7, [r2] /* *(0x60000000) = 0 */
str r2, [r2, lr] /* store test pattern */
str r1, [r2, lr] /* store test pattern */
ldr r7, [r2]
cmp r7, #0 /* check if beginning of dram is not touched */
ldreq lr, [r2, lr] /* readback row1,col1 addr */
cmpeq lr, r1 /* check if test pattern is valid */
ldreq r7, [r2, lr] /* readback row1 addr */
cmpeq r7, r1 /* check if test pattern is valid */
beq end
subs r5, #1
bpl row_loop