rk27load: fix stage1 dram config bug
Change-Id: I03d44dbd05fcd5dfc0e508020fae7006d8a97505
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1 changed files with 9 additions and 9 deletions
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@ -52,11 +52,11 @@ col_loop:
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add r5, r4, #8 /* col_num_bits */
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mov r6, r3, lsl r5 /* offset to the col1 (1<<col_num_bits) */
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mov r7, #0
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str r7, [r1] /* *(0x60000000) = 0 */
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str r1, [r1, r6] /* store test pattern in col1 addr */
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ldr r7, [r1]
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str r7, [r2] /* *(0x60000000) = 0 */
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str r1, [r2, r6] /* store test pattern in col1 addr */
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ldr r7, [r2]
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cmp r7, #0 /* check if beginning of dram is not touched */
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ldreq r7, [r1, r6] /* readback col1 addr */
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ldreq r7, [r2, r6] /* readback col1 addr */
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cmpeq r7, r1 /* check if test pattern is valid */
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beq row_loop_setup /* quit column loop */
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subs r4, #1
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@ -76,12 +76,12 @@ row_loop:
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*/
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mov r7, #0
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str r7, [r1] /* *(0x60000000) = 0 */
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str r2, [r1, lr] /* store test pattern */
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ldr r7, [r1]
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str r7, [r2] /* *(0x60000000) = 0 */
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str r2, [r2, lr] /* store test pattern */
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ldr r7, [r2]
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cmp r7, #0 /* check if beginning of dram is not touched */
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ldreq lr, [r1, lr] /* readback row1,col1 addr */
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cmpeq lr, r2 /* check if test pattern is valid */
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ldreq lr, [r2, lr] /* readback row1,col1 addr */
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cmpeq lr, r1 /* check if test pattern is valid */
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beq end
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subs r5, #1
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bpl row_loop
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