rk27load: fix stage1 dram config bug

Change-Id: I03d44dbd05fcd5dfc0e508020fae7006d8a97505
This commit is contained in:
Marcin Bukat 2014-07-23 12:32:16 +02:00
parent 9fb65294fb
commit dcd8172f4f

View file

@ -52,11 +52,11 @@ col_loop:
add r5, r4, #8 /* col_num_bits */
mov r6, r3, lsl r5 /* offset to the col1 (1<<col_num_bits) */
mov r7, #0
str r7, [r1] /* *(0x60000000) = 0 */
str r1, [r1, r6] /* store test pattern in col1 addr */
ldr r7, [r1]
str r7, [r2] /* *(0x60000000) = 0 */
str r1, [r2, r6] /* store test pattern in col1 addr */
ldr r7, [r2]
cmp r7, #0 /* check if beginning of dram is not touched */
ldreq r7, [r1, r6] /* readback col1 addr */
ldreq r7, [r2, r6] /* readback col1 addr */
cmpeq r7, r1 /* check if test pattern is valid */
beq row_loop_setup /* quit column loop */
subs r4, #1
@ -76,12 +76,12 @@ row_loop:
*/
mov r7, #0
str r7, [r1] /* *(0x60000000) = 0 */
str r2, [r1, lr] /* store test pattern */
ldr r7, [r1]
str r7, [r2] /* *(0x60000000) = 0 */
str r2, [r2, lr] /* store test pattern */
ldr r7, [r2]
cmp r7, #0 /* check if beginning of dram is not touched */
ldreq lr, [r1, lr] /* readback row1,col1 addr */
cmpeq lr, r2 /* check if test pattern is valid */
ldreq lr, [r2, lr] /* readback row1,col1 addr */
cmpeq lr, r1 /* check if test pattern is valid */
beq end
subs r5, #1
bpl row_loop