Reverting parts of r19760 that was mistakenly committed.
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@19761 a1c6a512-1295-4272-9138-f99709370657
This commit is contained in:
Björn Stenberg
parent
7bc29086ec
commit
30414d56c9
3 changed files with 88 additions and 91 deletions
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@ -151,4 +151,3 @@ superdom.c
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#endif /* m:robe 500 */
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#endif /* m:robe 500 */
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md5sum.c
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md5sum.c
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test_boost.c
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@ -50,15 +50,22 @@
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*/
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*/
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#if MEM < 32
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#if MEM < 32
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#define MAX_REFRESH_TIMER 54
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#define MAX_REFRESH_TIMER 59
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#define NORMAL_REFRESH_TIMER 10
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#define NORMAL_REFRESH_TIMER 21
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#define DEFAULT_REFRESH_TIMER 4
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#define DEFAULT_REFRESH_TIMER 4
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#else
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#else
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#define MAX_REFRESH_TIMER 26
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#define MAX_REFRESH_TIMER 29
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#define NORMAL_REFRESH_TIMER 4
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#define NORMAL_REFRESH_TIMER 10
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#define DEFAULT_REFRESH_TIMER 1
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#define DEFAULT_REFRESH_TIMER 1
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#endif
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#endif
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#ifdef IRIVER_H300_SERIES
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#define RECALC_DELAYS(f) \
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pcf50606_i2c_recalc_delay(f)
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#else
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#define RECALC_DELAYS(f)
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#endif
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#ifdef HAVE_SERIAL
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#ifdef HAVE_SERIAL
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#define BAUD_RATE 57600
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#define BAUD_RATE 57600
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#define BAUDRATE_DIV_DEFAULT (CPUFREQ_DEFAULT/(BAUD_RATE*32*2))
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#define BAUDRATE_DIV_DEFAULT (CPUFREQ_DEFAULT/(BAUD_RATE*32*2))
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@ -66,21 +73,6 @@
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#define BAUDRATE_DIV_MAX (CPUFREQ_MAX/(BAUD_RATE*32*2))
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#define BAUDRATE_DIV_MAX (CPUFREQ_MAX/(BAUD_RATE*32*2))
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#endif
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#endif
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static bool pll_initialized = false;
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static void init_pll(void)
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{
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/* Refresh timer for bypass frequency */
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PLLCR &= ~1; /* Bypass mode */
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PLLCR = 0x0189e025 | (PLLCR & 0x70400000); /* set 112 MHz */
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/* Wait until the PLL has locked. This may take up to 10ms! */
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while(!(PLLCR & 0x80000000)) {};
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pll_initialized = true;
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}
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#ifdef HAVE_ADJUSTABLE_CPU_FREQ
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#ifdef HAVE_ADJUSTABLE_CPU_FREQ
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void set_cpu_frequency (long) __attribute__ ((section (".icode")));
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void set_cpu_frequency (long) __attribute__ ((section (".icode")));
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void set_cpu_frequency(long frequency)
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void set_cpu_frequency(long frequency)
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@ -89,78 +81,84 @@ void cf_set_cpu_frequency (long) __attribute__ ((section (".icode")));
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void cf_set_cpu_frequency(long frequency)
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void cf_set_cpu_frequency(long frequency)
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#endif
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#endif
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{
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{
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if (!pll_initialized)
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init_pll();
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switch(frequency)
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switch(frequency)
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{
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{
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case CPUFREQ_MAX:
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case CPUFREQ_MAX:
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CSCR0 = 0x00001180; /* Flash: 4 wait states */
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DCR = (0x8200 | DEFAULT_REFRESH_TIMER);
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CSCR1 = 0x00001580; /* LCD: 5 wait states */
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/* Refresh timer for bypass frequency */
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PLLCR &= ~1; /* Bypass mode */
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timers_adjust_prescale(CPUFREQ_DEFAULT_MULT, false);
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RECALC_DELAYS(CPUFREQ_MAX);
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PLLCR = 0x018ae025 | (PLLCR & 0x70400000);
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CSCR0 = 0x00001180; /* Flash: 4 wait states */
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CSCR1 = 0x00001580; /* LCD: 5 wait states */
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#if CONFIG_USBOTG == USBOTG_ISP1362
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#if CONFIG_USBOTG == USBOTG_ISP1362
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CSCR3 = 0x00002180; /* USBOTG: 8 wait states */
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CSCR3 = 0x00002180; /* USBOTG: 8 wait states */
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#endif
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#endif
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#if CONFIG_RTC == RTC_PCF50606
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while(!(PLLCR & 0x80000000)) {}; /* Wait until the PLL has locked.
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pcf50606_i2c_recalc_delay(CPUFREQ_MAX);
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This may take up to 10ms! */
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#endif
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timers_adjust_prescale(CPUFREQ_MAX_MULT, true);
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timers_adjust_prescale(CPUFREQ_MAX_MULT, true);
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DCR = (0x8200 | MAX_REFRESH_TIMER); /* Refresh timer */
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DCR = (0x8200 | MAX_REFRESH_TIMER); /* Refresh timer */
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cpu_frequency = CPUFREQ_MAX;
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IDECONFIG1 = 0x10100000 | (1 << 13) | (3 << 10);
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IDECONFIG1 = 0x10100000 | (1 << 13) | (3 << 10);
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/* SRE active on write (H300 USBOTG) | BUFEN2 enable | CS2Post | CS2Pre */
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/* SRE active on write (H300 USBOTG) | BUFEN2 enable | CS2Post | CS2Pre */
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IDECONFIG2 = 0x40000 | (1 << 8); /* TA enable 2 + CS2wait */
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IDECONFIG2 = 0x40000 | (1 << 8); /* TA enable + CS2wait */
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PLLCR = (PLLCR & ~0x07000000) | (1 << 24); /* set CPUDIV */
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DCR = (0x8200 | MAX_REFRESH_TIMER); /* DRAM refresh timer */
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cpu_frequency = CPUFREQ_MAX;
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break;
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case CPUFREQ_NORMAL:
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PLLCR = (PLLCR & ~0x07000000) | (5 << 24); /* set CPUDIV */
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DCR = (0x8000 | NORMAL_REFRESH_TIMER); /* DRAM refresh timer */
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cpu_frequency = CPUFREQ_MAX;
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CSCR0 = 0x00000580; /* Flash: 1 wait state */
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CSCR1 = 0x00000180; /* LCD: 0 wait states */
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#if CONFIG_USBOTG == USBOTG_ISP1362
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CSCR3 = 0x00000580; /* USBOTG: 1 wait state */
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#endif
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#if CONFIG_RTC == RTC_PCF50606
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pcf50606_i2c_recalc_delay(CPUFREQ_NORMAL);
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#endif
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timers_adjust_prescale(CPUFREQ_NORMAL_MULT, true);
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IDECONFIG1 = 0x10100000 | (1 << 13) | (1 << 10);
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/* SRE active on write (H300 USBOTG) | BUFEN2 enable | CS2Post | CS2Pre */
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IDECONFIG2 = 0x40000; /* TA enable 2 */
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break;
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default:
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DCR = (DCR & ~0x01ff) | DEFAULT_REFRESH_TIMER;
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/* Refresh timer for bypass frequency */
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PLLCR &= ~1; /* Bypass mode */
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timers_adjust_prescale(CPUFREQ_DEFAULT_MULT, true);
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#if CONFIG_RTC == RTC_PCF50606
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pcf50606_i2c_recalc_delay(CPUFREQ_DEFAULT_MULT);
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#endif
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/* Power down PLL, but keep CRSEL and CLSEL */
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PLLCR = 0x00800200 | (PLLCR & 0x70400000);
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CSCR0 = 0x00000180; /* Flash: 0 wait states */
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CSCR1 = 0x00000180; /* LCD: 0 wait states */
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#if CONFIG_USBOTG == USBOTG_ISP1362
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CSCR3 = 0x00000180; /* USBOTG: 0 wait states */
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#endif
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DCR = (0x8000 | DEFAULT_REFRESH_TIMER); /* Refresh timer */
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cpu_frequency = CPUFREQ_DEFAULT;
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IDECONFIG1 = 0x10100000 | (1 << 13) | (1 << 10);
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/* SRE active on write (H300 USBOTG) | BUFEN2 enable | CS2Post | CS2Pre */
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IDECONFIG2 = 0x40000; /* TA enable 2 */
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pll_initialized = false;
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break;
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}
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#ifdef HAVE_SERIAL
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#ifdef HAVE_SERIAL
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UBG10 = BAUDRATE_DIV_NORMAL >> 8;
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UBG10 = BAUDRATE_DIV_MAX >> 8;
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UBG20 = BAUDRATE_DIV_NORMAL & 0xff;
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UBG20 = BAUDRATE_DIV_MAX & 0xff;
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#endif
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#endif
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break;
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case CPUFREQ_NORMAL:
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DCR = (DCR & ~0x01ff) | DEFAULT_REFRESH_TIMER;
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/* Refresh timer for bypass frequency */
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PLLCR &= ~1; /* Bypass mode */
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timers_adjust_prescale(CPUFREQ_DEFAULT_MULT, false);
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RECALC_DELAYS(CPUFREQ_NORMAL);
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PLLCR = 0x0589e021 | (PLLCR & 0x70400000);
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CSCR0 = 0x00000580; /* Flash: 1 wait state */
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CSCR1 = 0x00000180; /* LCD: 0 wait states */
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#if CONFIG_USBOTG == USBOTG_ISP1362
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CSCR3 = 0x00000580; /* USBOTG: 1 wait state */
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#endif
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while(!(PLLCR & 0x80000000)) {}; /* Wait until the PLL has locked.
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This may take up to 10ms! */
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timers_adjust_prescale(CPUFREQ_NORMAL_MULT, true);
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DCR = (0x8000 | NORMAL_REFRESH_TIMER); /* Refresh timer */
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cpu_frequency = CPUFREQ_NORMAL;
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IDECONFIG1 = 0x10100000 | (1 << 13) | (1 << 10);
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/* SRE active on write (H300 USBOTG) | BUFEN2 enable | CS2Post | CS2Pre */
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IDECONFIG2 = 0x40000 | (0 << 8); /* TA enable + CS2wait */
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#ifdef HAVE_SERIAL
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UBG10 = BAUDRATE_DIV_NORMAL >> 8;
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UBG20 = BAUDRATE_DIV_NORMAL & 0xff;
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#endif
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break;
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default:
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DCR = (DCR & ~0x01ff) | DEFAULT_REFRESH_TIMER;
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/* Refresh timer for bypass frequency */
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PLLCR &= ~1; /* Bypass mode */
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timers_adjust_prescale(CPUFREQ_DEFAULT_MULT, true);
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RECALC_DELAYS(CPUFREQ_DEFAULT);
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/* Power down PLL, but keep CRSEL and CLSEL */
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PLLCR = 0x00800200 | (PLLCR & 0x70400000);
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CSCR0 = 0x00000180; /* Flash: 0 wait states */
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CSCR1 = 0x00000180; /* LCD: 0 wait states */
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#if CONFIG_USBOTG == USBOTG_ISP1362
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CSCR3 = 0x00000180; /* USBOTG: 0 wait states */
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#endif
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DCR = (0x8000 | DEFAULT_REFRESH_TIMER); /* Refresh timer */
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cpu_frequency = CPUFREQ_DEFAULT;
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IDECONFIG1 = 0x10100000 | (1 << 13) | (1 << 10);
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/* SRE active on write (H300 USBOTG) | BUFEN2 enable | CS2Post | CS2Pre */
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IDECONFIG2 = 0x40000 | (0 << 8); /* TA enable + CS2wait */
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#ifdef HAVE_SERIAL
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UBG10 = BAUDRATE_DIV_DEFAULT >> 8;
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UBG20 = BAUDRATE_DIV_DEFAULT & 0xff;
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#endif
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break;
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}
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}
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}
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@ -215,11 +215,11 @@ extern void cf_set_cpu_frequency(long frequency);
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/* 11.2896 MHz */
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/* 11.2896 MHz */
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#define CPUFREQ_DEFAULT_MULT 1
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#define CPUFREQ_DEFAULT_MULT 1
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#define CPUFREQ_DEFAULT (CPUFREQ_DEFAULT_MULT * CPU_FREQ)
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#define CPUFREQ_DEFAULT (CPUFREQ_DEFAULT_MULT * CPU_FREQ)
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/* 22.5792 MHz */
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/* 45.1584 MHz */
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#define CPUFREQ_NORMAL_MULT 2
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#define CPUFREQ_NORMAL_MULT 4
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#define CPUFREQ_NORMAL (CPUFREQ_NORMAL_MULT * CPU_FREQ)
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#define CPUFREQ_NORMAL (CPUFREQ_NORMAL_MULT * CPU_FREQ)
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/* 112.896 MHz */
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/* 124.1856 MHz */
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#define CPUFREQ_MAX_MULT 10
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#define CPUFREQ_MAX_MULT 11
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#define CPUFREQ_MAX (CPUFREQ_MAX_MULT * CPU_FREQ)
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#define CPUFREQ_MAX (CPUFREQ_MAX_MULT * CPU_FREQ)
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#endif /* SYSTEM_TARGET_H */
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#endif /* SYSTEM_TARGET_H */
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