From 30414d56c9f8b4fc35ac2918c4d22e5e2ded0eb6 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Bj=C3=B6rn=20Stenberg?= Date: Tue, 13 Jan 2009 14:56:20 +0000 Subject: [PATCH] Reverting parts of r19760 that was mistakenly committed. git-svn-id: svn://svn.rockbox.org/rockbox/trunk@19761 a1c6a512-1295-4272-9138-f99709370657 --- apps/plugins/SOURCES | 1 - .../target/coldfire/iriver/system-iriver.c | 170 +++++++++--------- firmware/target/coldfire/system-target.h | 8 +- 3 files changed, 88 insertions(+), 91 deletions(-) diff --git a/apps/plugins/SOURCES b/apps/plugins/SOURCES index 8f461f37e2..7d48be60c1 100644 --- a/apps/plugins/SOURCES +++ b/apps/plugins/SOURCES @@ -151,4 +151,3 @@ superdom.c #endif /* m:robe 500 */ md5sum.c -test_boost.c diff --git a/firmware/target/coldfire/iriver/system-iriver.c b/firmware/target/coldfire/iriver/system-iriver.c index aa24f6ecc9..1916eec0cd 100644 --- a/firmware/target/coldfire/iriver/system-iriver.c +++ b/firmware/target/coldfire/iriver/system-iriver.c @@ -50,15 +50,22 @@ */ #if MEM < 32 -#define MAX_REFRESH_TIMER 54 -#define NORMAL_REFRESH_TIMER 10 +#define MAX_REFRESH_TIMER 59 +#define NORMAL_REFRESH_TIMER 21 #define DEFAULT_REFRESH_TIMER 4 #else -#define MAX_REFRESH_TIMER 26 -#define NORMAL_REFRESH_TIMER 4 +#define MAX_REFRESH_TIMER 29 +#define NORMAL_REFRESH_TIMER 10 #define DEFAULT_REFRESH_TIMER 1 #endif +#ifdef IRIVER_H300_SERIES +#define RECALC_DELAYS(f) \ + pcf50606_i2c_recalc_delay(f) +#else +#define RECALC_DELAYS(f) +#endif + #ifdef HAVE_SERIAL #define BAUD_RATE 57600 #define BAUDRATE_DIV_DEFAULT (CPUFREQ_DEFAULT/(BAUD_RATE*32*2)) @@ -66,21 +73,6 @@ #define BAUDRATE_DIV_MAX (CPUFREQ_MAX/(BAUD_RATE*32*2)) #endif -static bool pll_initialized = false; - -static void init_pll(void) -{ - /* Refresh timer for bypass frequency */ - PLLCR &= ~1; /* Bypass mode */ - PLLCR = 0x0189e025 | (PLLCR & 0x70400000); /* set 112 MHz */ - - /* Wait until the PLL has locked. This may take up to 10ms! */ - while(!(PLLCR & 0x80000000)) {}; - - pll_initialized = true; -} - - #ifdef HAVE_ADJUSTABLE_CPU_FREQ void set_cpu_frequency (long) __attribute__ ((section (".icode"))); void set_cpu_frequency(long frequency) @@ -89,78 +81,84 @@ void cf_set_cpu_frequency (long) __attribute__ ((section (".icode"))); void cf_set_cpu_frequency(long frequency) #endif { - if (!pll_initialized) - init_pll(); - switch(frequency) { - case CPUFREQ_MAX: - CSCR0 = 0x00001180; /* Flash: 4 wait states */ - CSCR1 = 0x00001580; /* LCD: 5 wait states */ + case CPUFREQ_MAX: + DCR = (0x8200 | DEFAULT_REFRESH_TIMER); + /* Refresh timer for bypass frequency */ + PLLCR &= ~1; /* Bypass mode */ + timers_adjust_prescale(CPUFREQ_DEFAULT_MULT, false); + RECALC_DELAYS(CPUFREQ_MAX); + PLLCR = 0x018ae025 | (PLLCR & 0x70400000); + CSCR0 = 0x00001180; /* Flash: 4 wait states */ + CSCR1 = 0x00001580; /* LCD: 5 wait states */ #if CONFIG_USBOTG == USBOTG_ISP1362 - CSCR3 = 0x00002180; /* USBOTG: 8 wait states */ + CSCR3 = 0x00002180; /* USBOTG: 8 wait states */ #endif -#if CONFIG_RTC == RTC_PCF50606 - pcf50606_i2c_recalc_delay(CPUFREQ_MAX); -#endif - timers_adjust_prescale(CPUFREQ_MAX_MULT, true); - DCR = (0x8200 | MAX_REFRESH_TIMER); /* Refresh timer */ - IDECONFIG1 = 0x10100000 | (1 << 13) | (3 << 10); - /* SRE active on write (H300 USBOTG) | BUFEN2 enable | CS2Post | CS2Pre */ - IDECONFIG2 = 0x40000 | (1 << 8); /* TA enable 2 + CS2wait */ - - PLLCR = (PLLCR & ~0x07000000) | (1 << 24); /* set CPUDIV */ - DCR = (0x8200 | MAX_REFRESH_TIMER); /* DRAM refresh timer */ - cpu_frequency = CPUFREQ_MAX; - break; - - case CPUFREQ_NORMAL: - PLLCR = (PLLCR & ~0x07000000) | (5 << 24); /* set CPUDIV */ - DCR = (0x8000 | NORMAL_REFRESH_TIMER); /* DRAM refresh timer */ - cpu_frequency = CPUFREQ_MAX; - - CSCR0 = 0x00000580; /* Flash: 1 wait state */ - CSCR1 = 0x00000180; /* LCD: 0 wait states */ -#if CONFIG_USBOTG == USBOTG_ISP1362 - CSCR3 = 0x00000580; /* USBOTG: 1 wait state */ -#endif -#if CONFIG_RTC == RTC_PCF50606 - pcf50606_i2c_recalc_delay(CPUFREQ_NORMAL); -#endif - timers_adjust_prescale(CPUFREQ_NORMAL_MULT, true); - - IDECONFIG1 = 0x10100000 | (1 << 13) | (1 << 10); - /* SRE active on write (H300 USBOTG) | BUFEN2 enable | CS2Post | CS2Pre */ - IDECONFIG2 = 0x40000; /* TA enable 2 */ - break; - - default: - DCR = (DCR & ~0x01ff) | DEFAULT_REFRESH_TIMER; - /* Refresh timer for bypass frequency */ - PLLCR &= ~1; /* Bypass mode */ - timers_adjust_prescale(CPUFREQ_DEFAULT_MULT, true); -#if CONFIG_RTC == RTC_PCF50606 - pcf50606_i2c_recalc_delay(CPUFREQ_DEFAULT_MULT); -#endif - /* Power down PLL, but keep CRSEL and CLSEL */ - PLLCR = 0x00800200 | (PLLCR & 0x70400000); - CSCR0 = 0x00000180; /* Flash: 0 wait states */ - CSCR1 = 0x00000180; /* LCD: 0 wait states */ -#if CONFIG_USBOTG == USBOTG_ISP1362 - CSCR3 = 0x00000180; /* USBOTG: 0 wait states */ -#endif - DCR = (0x8000 | DEFAULT_REFRESH_TIMER); /* Refresh timer */ - cpu_frequency = CPUFREQ_DEFAULT; - IDECONFIG1 = 0x10100000 | (1 << 13) | (1 << 10); - /* SRE active on write (H300 USBOTG) | BUFEN2 enable | CS2Post | CS2Pre */ - IDECONFIG2 = 0x40000; /* TA enable 2 */ - - pll_initialized = false; - break; - } + while(!(PLLCR & 0x80000000)) {}; /* Wait until the PLL has locked. + This may take up to 10ms! */ + timers_adjust_prescale(CPUFREQ_MAX_MULT, true); + DCR = (0x8200 | MAX_REFRESH_TIMER); /* Refresh timer */ + cpu_frequency = CPUFREQ_MAX; + IDECONFIG1 = 0x10100000 | (1 << 13) | (3 << 10); + /* SRE active on write (H300 USBOTG) | BUFEN2 enable | CS2Post | CS2Pre */ + IDECONFIG2 = 0x40000 | (1 << 8); /* TA enable + CS2wait */ #ifdef HAVE_SERIAL - UBG10 = BAUDRATE_DIV_NORMAL >> 8; - UBG20 = BAUDRATE_DIV_NORMAL & 0xff; + UBG10 = BAUDRATE_DIV_MAX >> 8; + UBG20 = BAUDRATE_DIV_MAX & 0xff; #endif + break; + + case CPUFREQ_NORMAL: + DCR = (DCR & ~0x01ff) | DEFAULT_REFRESH_TIMER; + /* Refresh timer for bypass frequency */ + PLLCR &= ~1; /* Bypass mode */ + timers_adjust_prescale(CPUFREQ_DEFAULT_MULT, false); + RECALC_DELAYS(CPUFREQ_NORMAL); + PLLCR = 0x0589e021 | (PLLCR & 0x70400000); + CSCR0 = 0x00000580; /* Flash: 1 wait state */ + CSCR1 = 0x00000180; /* LCD: 0 wait states */ +#if CONFIG_USBOTG == USBOTG_ISP1362 + CSCR3 = 0x00000580; /* USBOTG: 1 wait state */ +#endif + while(!(PLLCR & 0x80000000)) {}; /* Wait until the PLL has locked. + This may take up to 10ms! */ + timers_adjust_prescale(CPUFREQ_NORMAL_MULT, true); + DCR = (0x8000 | NORMAL_REFRESH_TIMER); /* Refresh timer */ + cpu_frequency = CPUFREQ_NORMAL; + IDECONFIG1 = 0x10100000 | (1 << 13) | (1 << 10); + /* SRE active on write (H300 USBOTG) | BUFEN2 enable | CS2Post | CS2Pre */ + IDECONFIG2 = 0x40000 | (0 << 8); /* TA enable + CS2wait */ + +#ifdef HAVE_SERIAL + UBG10 = BAUDRATE_DIV_NORMAL >> 8; + UBG20 = BAUDRATE_DIV_NORMAL & 0xff; +#endif + break; + default: + DCR = (DCR & ~0x01ff) | DEFAULT_REFRESH_TIMER; + /* Refresh timer for bypass frequency */ + PLLCR &= ~1; /* Bypass mode */ + timers_adjust_prescale(CPUFREQ_DEFAULT_MULT, true); + RECALC_DELAYS(CPUFREQ_DEFAULT); + /* Power down PLL, but keep CRSEL and CLSEL */ + PLLCR = 0x00800200 | (PLLCR & 0x70400000); + CSCR0 = 0x00000180; /* Flash: 0 wait states */ + CSCR1 = 0x00000180; /* LCD: 0 wait states */ +#if CONFIG_USBOTG == USBOTG_ISP1362 + CSCR3 = 0x00000180; /* USBOTG: 0 wait states */ +#endif + DCR = (0x8000 | DEFAULT_REFRESH_TIMER); /* Refresh timer */ + cpu_frequency = CPUFREQ_DEFAULT; + IDECONFIG1 = 0x10100000 | (1 << 13) | (1 << 10); + /* SRE active on write (H300 USBOTG) | BUFEN2 enable | CS2Post | CS2Pre */ + IDECONFIG2 = 0x40000 | (0 << 8); /* TA enable + CS2wait */ + +#ifdef HAVE_SERIAL + UBG10 = BAUDRATE_DIV_DEFAULT >> 8; + UBG20 = BAUDRATE_DIV_DEFAULT & 0xff; +#endif + break; + } } diff --git a/firmware/target/coldfire/system-target.h b/firmware/target/coldfire/system-target.h index 892cbe89cf..84ec6ed4b0 100644 --- a/firmware/target/coldfire/system-target.h +++ b/firmware/target/coldfire/system-target.h @@ -215,11 +215,11 @@ extern void cf_set_cpu_frequency(long frequency); /* 11.2896 MHz */ #define CPUFREQ_DEFAULT_MULT 1 #define CPUFREQ_DEFAULT (CPUFREQ_DEFAULT_MULT * CPU_FREQ) -/* 22.5792 MHz */ -#define CPUFREQ_NORMAL_MULT 2 +/* 45.1584 MHz */ +#define CPUFREQ_NORMAL_MULT 4 #define CPUFREQ_NORMAL (CPUFREQ_NORMAL_MULT * CPU_FREQ) -/* 112.896 MHz */ -#define CPUFREQ_MAX_MULT 10 +/* 124.1856 MHz */ +#define CPUFREQ_MAX_MULT 11 #define CPUFREQ_MAX (CPUFREQ_MAX_MULT * CPU_FREQ) #endif /* SYSTEM_TARGET_H */