as3525v2-usb: end of massive renaming
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@26972 a1c6a512-1295-4272-9138-f99709370657
This commit is contained in:
Amaury Pouly
parent
19b3348656
commit
04ae1db331
2 changed files with 190 additions and 174 deletions
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@ -144,8 +144,8 @@ static void flush_tx_fifos(int nums)
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{
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unsigned int i = 0;
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GRSTCTL = (GRSTCTL & (~GRSTCTL_txfnum_bits))
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| (nums << GRSTCTL_txfnum_bit_pos)
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GRSTCTL = (GRSTCTL & ~bitm(GRSTCTL, txfnum))
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| (nums << GRSTCTL_txfnum_bitp)
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| GRSTCTL_txfflsh_flush;
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while(GRSTCTL & GRSTCTL_txfflsh_flush && i < 0x300)
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i++;
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@ -209,8 +209,8 @@ static void reset_endpoints(void)
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* Setup EP0 IN/OUT with 64 byte maximum packet size and activate both. Enable transfer on EP0 OUT
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*/
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DOEPTSIZ(0) = (1 << DEPTSIZ0_supcnt_bit_pos)
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| (1 << DEPTSIZ0_pkcnt_bit_pos)
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DOEPTSIZ(0) = (1 << DEPTSIZ0_supcnt_bitp)
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| (1 << DEPTSIZ0_pkcnt_bitp)
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| 8;
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/* setup DMA */
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@ -219,10 +219,10 @@ static void reset_endpoints(void)
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/* Enable endpoint, clear nak */
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DOEPCTL(0) = DEPCTL_epena | DEPCTL_cnak | DEPCTL_usbactep
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| (DEPCTL_MPS_8 << DEPCTL_mps_bit_pos);
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| (DEPCTL_MPS_8 << DEPCTL_mps_bitp);
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/* 64 bytes packet size, active endpoint */
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DIEPCTL(0) = (DEPCTL_MPS_8 << DEPCTL_mps_bit_pos)
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DIEPCTL(0) = (DEPCTL_MPS_8 << DEPCTL_mps_bitp)
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| DEPCTL_usbactep;
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DCTL = DCTL_cgnpinnak | DCTL_cgoutnak;
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@ -236,22 +236,22 @@ static void core_dev_init(void)
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/* Restart the phy clock */
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PCGCCTL = 0;
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/* Set phy speed : high speed */
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DCFG = (DCFG & ~DCFG_devspd_bits) | DCFG_devspd_hs_phy_hs;
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DCFG = (DCFG & ~bitm(DCFG, devspd)) | DCFG_devspd_hs_phy_hs;
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/* Check hardware capabilities */
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if(extract(GHWCFG2, ARCH) != INT_DMA_ARCH)
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panicf("usb: wrong architecture (%ld)", extract(GHWCFG2, ARCH));
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if(extract(GHWCFG2, HS_PHY_TYPE) != PHY_TYPE_UTMI)
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panicf("usb: wrong HS phy type (%ld)", extract(GHWCFG2, HS_PHY_TYPE));
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if(extract(GHWCFG2, FS_PHY_TYPE) != PHY_TYPE_UNSUPPORTED)
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panicf("usb: wrong FS phy type (%ld)", extract(GHWCFG2, FS_PHY_TYPE));
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if(GHWCFG4_UTMI_PHY_DATA_WIDTH != 0x2)
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panicf("usb: wrong utmi data width (%ld)", GHWCFG4_UTMI_PHY_DATA_WIDTH);
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if(GHWCFG4_DED_FIFO_EN != 1) /* it seems to be multiple tx fifo support */
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if(extract(GHWCFG2, arch) != GHWCFG2_ARCH_INTERNAL_DMA)
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panicf("usb: wrong architecture (%ld)", extract(GHWCFG2, arch));
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if(extract(GHWCFG2, hs_phy_type) != GHWCFG2_PHY_TYPE_UTMI)
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panicf("usb: wrong HS phy type (%ld)", extract(GHWCFG2, hs_phy_type));
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if(extract(GHWCFG2, fs_phy_type) != GHWCFG2_PHY_TYPE_UNSUPPORTED)
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panicf("usb: wrong FS phy type (%ld)", extract(GHWCFG2, fs_phy_type));
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if(extract(GHWCFG4, utmi_phy_data_width) != 0x2)
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panicf("usb: wrong utmi data width (%ld)", extract(GHWCFG4, utmi_phy_data_width));
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if(!(GHWCFG4 & GHWCFG4_ded_fifo_en)) /* it seems to be multiple tx fifo support */
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panicf("usb: no multiple tx fifo");
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#ifdef USE_CUSTOM_FIFO_LAYOUT
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if(!(GHWCFG2 & GHWCFG2_DYN_FIFO))
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if(!(GHWCFG2 & GHWCFG2_dyn_fifo))
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panicf("usb: no dynamic fifo");
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if(GRXFSIZ != DATA_FIFO_DEPTH)
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panicf("usb: wrong data fifo size");
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@ -263,10 +263,10 @@ static void core_dev_init(void)
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logf("hwcfg3: %08lx", GHWCFG3);
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logf("hwcfg4: %08lx", GHWCFG4);
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logf("%ld endpoints", extract(GHWCFG2, NUM_EP));
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logf("%ld endpoints", extract(GHWCFG2, num_ep));
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num_in_ep = 0;
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num_out_ep = 0;
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for(i = 0; i < extract(GHWCFG2, NUM_EP); i++)
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for(i = 0; i < extract(GHWCFG2, num_ep); i++)
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{
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if(GHWCFG1 & GHWCFG1_IN_EP(i))
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num_in_ep++;
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@ -277,8 +277,8 @@ static void core_dev_init(void)
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GHWCFG1 & GHWCFG1_OUT_EP(i) ? "yes" : "no");
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}
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if(num_in_ep != GHWCFG4_NUM_IN_EP)
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panicf("usb: num in ep mismatch(%d,%lu)", num_in_ep, GHWCFG4_NUM_IN_EP);
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if(num_in_ep != extract(GHWCFG4, num_in_ep))
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panicf("usb: num in ep mismatch(%d,%lu)", num_in_ep, extract(GHWCFG4, num_in_ep));
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if(num_in_ep != NUM_IN_EP)
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panicf("usb: num in ep static mismatch(%u,%u)", num_in_ep, NUM_IN_EP);
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if(num_out_ep != NUM_OUT_EP)
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@ -287,7 +287,7 @@ static void core_dev_init(void)
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logf("%d in ep, %d out ep", num_in_ep, num_out_ep);
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logf("initial:");
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logf(" tot fifo sz: %lx", GHWCFG3_DFIFO_LEN);
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logf(" tot fifo sz: %lx", extract(GHWCFG3, dfifo_len));
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logf(" rx fifo: [%04x,+%4lx]", 0, GRXFSIZ);
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logf(" nptx fifo: [%04lx,+%4lx]", GET_FIFOSIZE_START_ADR(GNPTXFSIZ),
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GET_FIFOSIZE_DEPTH(GNPTXFSIZ));
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@ -344,9 +344,9 @@ static void core_dev_init(void)
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logf("threshold control:");
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logf(" non_iso_thr_en: %d", (DTHRCTL & DTHRCTL_non_iso_thr_en) ? 1 : 0);
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logf(" iso_thr_en: %d", (DTHRCTL & DTHRCTL_iso_thr_en) ? 1 : 0);
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logf(" tx_thr_len: %lu", (DTHRCTL & DTHRCTL_tx_thr_len_bits) >> DTHRCTL_tx_thr_len_bit_pos);
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logf(" tx_thr_len: %lu", extract(DTHRCTL, tx_thr_len));
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logf(" rx_thr_en: %d", (DTHRCTL & DTHRCTL_rx_thr_en) ? 1 : 0);
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logf(" rx_thr_len: %lu", (DTHRCTL & DTHRCTL_rx_thr_len_bits) >> DTHRCTL_rx_thr_len_bit_pos);
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logf(" rx_thr_len: %lu", extract(DTHRCTL, rx_thr_len));
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*/
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DTHRCTL = 0;
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@ -365,7 +365,7 @@ static void core_init(void)
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/* fixme: the current code is for internal DMA only, the clip+ architecture
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* define the internal DMA model */
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/* Set burstlen and enable DMA*/
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GAHBCFG = (GAHBCFG_INT_DMA_BURST_INCR4 << GAHBCFG_hburstlen_bit_pos)
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GAHBCFG = (GAHBCFG_INT_DMA_BURST_INCR4 << GAHBCFG_hburstlen_bitp)
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| GAHBCFG_dma_enable;
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/* Disable HNP and SRP, not sure it's useful because we already forced dev mode */
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GUSBCFG &= ~(GUSBCFG_srpcap | GUSBCFG_hnpcapp);
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@ -422,7 +422,7 @@ static bool handle_reset(void)
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reset_endpoints();
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/* Reset Device Address */
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DCFG &= ~DCFG_devadr_bits;
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DCFG &= bitm(DCFG, devadr);
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usb_core_bus_reset();
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@ -450,7 +450,7 @@ static bool handle_enum_done(void)
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logf("DCFG=%lx", DCFG);
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logf("DTHRCTL=%lx", DTHRCTL);
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switch((DSTS & DSTS_enumspd_bits) >> DSTS_enumspd_bit_pos)
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switch(extract(DSTS, enumspd))
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{
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case DSTS_ENUMSPD_HS_PHY_30MHZ_OR_60MHZ:
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logf("usb: HS");
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@ -463,23 +463,7 @@ static bool handle_enum_done(void)
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panicf("usb: LS is not supported");
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}
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DOEPCTL(0) = (DOEPCTL(0) & ~DEPCTL_mps_bits)
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| (DEPCTL_MPS_64 << DEPCTL_mps_bit_pos);
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DIEPCTL(0) = (DIEPCTL(0) & ~DEPCTL_mps_bits)
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| (DEPCTL_MPS_64 << DEPCTL_mps_bit_pos);
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unsigned i, ep;
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FOR_EACH_IN_EP(i, ep)
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DIEPCTL(ep) = (DIEPCTL(ep) & ~DEPCTL_mps_bits)
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| (512 << DEPCTL_mps_bit_pos);
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FOR_EACH_OUT_EP(i, ep)
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DOEPCTL(ep) = (DOEPCTL(ep) & ~DEPCTL_mps_bits)
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| (512 << DEPCTL_mps_bit_pos);
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DOEPTSIZ(0) = (1 << DEPTSIZ0_supcnt_bit_pos)
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| (1 << DEPTSIZ0_pkcnt_bit_pos)
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| 64;
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/* fixme: change EP0 mps here */
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return true;
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}
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@ -24,15 +24,26 @@
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#include "as3525v2.h"
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/* All multi-bit fields in the driver use the following convention.
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* If the register name is NAME, then there is one define NAME_bit_pos
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* If the register name is NAME, then there is one define NAME_bitp
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* which holds the bit position and one define NAME_bits which holds
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* a mask of the bits within the register.
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* a mask of the bits within the register (after shift).
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* These macros allow easy access and construction of such fields */
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/* Usage:
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* - extract(reg_name,field_name)
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note: the field_name must not be prefix with the reg name */
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* extract a field of the register
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* - bitm(reg_name,field_name)
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* build a bitmask for the field
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* - make(reg_name,field_name,value)
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* build the value of the field (doesn't mask)
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*/
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#define extract(reg_name, field_name) \
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((reg_name & reg_name##_##field_name##_bits) >> reg_name##_##field_name##_bit_pos)
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((reg_name >> reg_name##_##field_name##_bitp) & reg_name##_##field_name##_bits)
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#define bitm(reg_name, field_name) \
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(reg_name##_##field_name##_bits << reg_name##_##field_name##_bitp)
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#define make(reg_name, field_name, value) \
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((value) << reg_name##_##field_name##_bitp)
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#define USB_DEVICE (USB_BASE + 0x0800) /** USB Device base address */
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@ -50,7 +61,7 @@
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/** Core AHB Configuration Register */
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#define GAHBCFG BASE_REG(0x008)
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#define GAHBCFG_glblintrmsk (1 << 0) /** Global interrupt mask */
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#define GAHBCFG_hburstlen_bit_pos 1
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#define GAHBCFG_hburstlen_bitp 1
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#define GAHBCFG_INT_DMA_BURST_SINGLE 0
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#define GAHBCFG_INT_DMA_BURST_INCR 1 /** note: the linux patch has several other value, this is one picked for internal dma */
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#define GAHBCFG_INT_DMA_BURST_INCR4 3
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@ -60,8 +71,8 @@
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/** Core USB Configuration Register */
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#define GUSBCFG BASE_REG(0x00C)
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#define GUSBCFG_toutcal_bit_pos 0
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#define GUSBCFG_toutcal_bits (0x7 << GUSBCFG_toutcal_bit_pos)
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#define GUSBCFG_toutcal_bitp 0
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#define GUSBCFG_toutcal_bits 0x7
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#define GUSBCFG_phy_if (1 << 3) /** select utmi bus width ? */
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#define GUSBCFG_ulpi_utmi_sel (1 << 4) /** select ulpi:1 or utmi:0 */
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#define GUSBCFG_fsintf (1 << 5)
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@ -69,8 +80,8 @@
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#define GUSBCFG_ddrsel (1 << 7)
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#define GUSBCFG_srpcap (1 << 8)
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#define GUSBCFG_hnpcapp (1 << 9)
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#define GUSBCFG_usbtrdtim_bit_pos 10
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#define GUSBCFG_usbtrdtim_bits (0xf << GUSBCFG_usbtrdtim_bit_pos)
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#define GUSBCFG_usbtrdtim_bitp 10
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#define GUSBCFG_usbtrdtim_bits 0xf
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#define GUSBCFG_nptxfrwnden (1 << 14)
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#define GUSBCFG_phylpwrclksel (1 << 15)
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#define GUSBCFG_otgutmifssel (1 << 16)
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@ -91,8 +102,8 @@
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#define GRSTCTL_intknqflsh (1 << 3) /** In Token Sequence Learning Queue Flush */
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#define GRSTCTL_rxfflsh_flush (1 << 4) /** RxFIFO Flush */
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#define GRSTCTL_txfflsh_flush (1 << 5) /** TxFIFO Flush */
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#define GRSTCTL_txfnum_bit_pos 6 /** TxFIFO Number */
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#define GRSTCTL_txfnum_bits (0x1f << 6)
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#define GRSTCTL_txfnum_bitp 6 /** TxFIFO Number */
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#define GRSTCTL_txfnum_bits 0x1f
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#define GRSTCTL_ahbidle (1 << 31) /** AHB idle state*/
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/** Core Interrupt Register */
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@ -166,25 +177,32 @@
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/** User HW Config2 Register */
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#define GHWCFG2 BASE_REG(0x048)
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#define GHWCFG2_ARCH_bit_pos 3 /** Architecture */
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#define GHWCFG2_ARCH_bits (0x3 << GHWCFG2_ARCH_bit_pos)
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#define GHWCFG2_HS_PHY_TYPE_bit_pos 6 /** High speed PHY type */
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#define GHWCFG2_HS_PHY_TYPE_bits (0x3 << GHWCFG2_HS_PHY_TYPE_bit_pos)
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#define GHWCFG2_FS_PHY_TYPE_bit_pos 8 /** Full speed PHY type */
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#define GHWCFG2_FS_PHY_TYPE_bits (0x3 << GHWCFG2_FS_PHY_TYPE_bit_pos)
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#define GHWCFG2_NUM_EP_bit_pos 10 /** Number of endpoints */
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#define GHWCFG2_NUM_EP_bits (0xf << GHWCFG2_NUM_EP_bit_pos)
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#define GHWCFG2_DYN_FIFO (1 << 19) /** Dynamic FIFO */
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/* For GHWCFG2_HS_PHY_TYPE and GHWCFG2_SS_PHY_TYPE */
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#define PHY_TYPE_UNSUPPORTED 0
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#define PHY_TYPE_UTMI 1
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#define INT_DMA_ARCH 2
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#define GHWCFG2_arch_bitp 3 /** Architecture */
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#define GHWCFG2_arch_bits 0x3
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#define GHWCFG2_hs_phy_type_bitp 6 /** High speed PHY type */
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#define GHWCFG2_hs_phy_type_bits 0x3
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#define GHWCFG2_fs_phy_type_bitp 8 /** Full speed PHY type */
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#define GHWCFG2_fs_phy_type_bits 0x3
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#define GHWCFG2_num_ep_bitp 10 /** Number of endpoints */
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#define GHWCFG2_num_ep_bits 0xf
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#define GHWCFG2_dyn_fifo (1 << 19) /** Dynamic FIFO */
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/* For GHWCFG2_HS_PHY_TYPE and GHWCFG2_FS_PHY_TYPE */
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#define GHWCFG2_PHY_TYPE_UNSUPPORTED 0
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#define GHWCFG2_PHY_TYPE_UTMI 1
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#define GHWCFG2_ARCH_INTERNAL_DMA 2
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/** User HW Config3 Register */
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#define GHWCFG3 BASE_REG(0x04C)
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#define GHWCFG3 BASE_REG(0x04C)
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#define GHWCFG3_dfifo_len_bitp 16 /** Total fifo size */
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#define GHWCFG3_dfifo_len_bits 0xffff
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/** User HW Config4 Register */
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#define GHWCFG4 BASE_REG(0x050)
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#define GHWCFG4 BASE_REG(0x050)
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#define GHWCFG4_utmi_phy_data_width_bitp 14 /** UTMI+ data bus width */
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#define GHWCFG4_utmi_phy_data_width_bits 0x3
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#define GHWCFG4_ded_fifo_en (1 << 25) /** Dedicated Tx FIFOs */
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#define GHWCFG4_num_in_ep_bitp 26 /** Number of IN endpoints */
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#define GHWCFG4_num_in_ep_bits 0xf
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/* 1<=ep<=15, don't use ep=0 !!! */
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/** Device IN Endpoint Transmit FIFO (ep) Size Register */
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@ -200,86 +218,121 @@
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#define GET_FIFOSIZE_START_ADR(data) \
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((data) & 0xffff)
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#define GHWCFG3_DFIFO_LEN (GHWCFG3 >> 16) /** Total fifo size */
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#define GHWCFG4_UTMI_PHY_DATA_WIDTH ((GHWCFG4 >> 14) & 0x3) /** UTMI+ data bus width (format is unsure) */
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#define GHWCFG4_DED_FIFO_EN ((GHWCFG4 >> 25) & 0x1) /** Dedicated Tx FIFOs */
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#define GHWCFG4_NUM_IN_EP ((GHWCFG4 >> 26) & 0xf) /** Number of IN endpoints */
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/**
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* Device Registers Base Addresses
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*/
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#define DEV_REG(offset) (*(volatile unsigned long *)(USB_DEVICE + offset))
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#define DCFG DEV_REG(0x00) /** Device Configuration Register */
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#define DCTL DEV_REG(0x04) /** Device Control Register */
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#define DSTS DEV_REG(0x08) /** Device Status Register */
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#define DIEPMSK DEV_REG(0x10) /** Device IN Endpoint Common Interrupt Mask Register */
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#define DOEPMSK DEV_REG(0x14) /** Device OUT Endpoint Common Interrupt Mask Register */
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#define DAINT DEV_REG(0x18) /** Device All Endpoints Interrupt Register */
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#define DAINTMSK DEV_REG(0x1C) /** Device Endpoints Interrupt Mask Register */
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#define DTKNQR1 DEV_REG(0x20) /** Device IN Token Sequence Learning Queue Read Register 1 */
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#define DTKNQR2 DEV_REG(0x24) /** Device IN Token Sequence Learning Queue Register 2 */
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#define DTKNQP DEV_REG(0x28) /** Device IN Token Queue Pop register */
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/* fixme: those registers are not present in registers.h but are in dwc_otgh_regs.h.
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* the previous registers exists but has a different name :( */
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#define DVBUSDIS DEV_REG(0x28) /** Device VBUS discharge register*/
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#define DVBUSPULSE DEV_REG(0x2C) /** Device VBUS pulse register */
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#define DTKNQR3 DEV_REG(0x30) /** Device IN Token Queue Read Register 3 (RO) */
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#define DTHRCTL DEV_REG(0x30) /** Device Thresholding control register */
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#define DTKNQR4 DEV_REG(0x34) /** Device IN Token Queue Read Register 4 (RO) */
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#define FFEMPTYMSK DEV_REG(0x34) /** Device IN EPs empty Inr. Mask Register */
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/** Device Configuration Register */
|
||||
#define DCFG DEV_REG(0x00)
|
||||
#define DCFG_devspd_bitp 0 /** Device Speed */
|
||||
#define DCFG_devspd_bits 0x3
|
||||
#define DCFG_devspd_hs_phy_hs 0 /** High speed PHY running at high speed */
|
||||
#define DCFG_devspd_hs_phy_fs 1 /** High speed PHY running at full speed */
|
||||
#define DCFG_nzstsouthshk (1 << 2) /** Non Zero Length Status OUT Handshake */
|
||||
#define DCFG_devadr_bitp 4 /** Device Address */
|
||||
#define DCFG_devadr_bits 0x7f
|
||||
#define DCFG_perfrint_bitp 11 /** Periodic Frame Interval */
|
||||
#define DCFG_perfrint_bits 0x3
|
||||
#define DCFG_FRAME_INTERVAL_80 0
|
||||
#define DCFG_FRAME_INTERVAL_85 1
|
||||
#define DCFG_FRAME_INTERVAL_90 2
|
||||
#define DCFG_FRAME_INTERVAL_95 3
|
||||
|
||||
#define DCTL_rmtwkupsig (1 << 0) /** Remote Wakeup */
|
||||
#define DCTL_sftdiscon (1 << 1) /** Soft Disconnect */
|
||||
#define DCTL_gnpinnaksts (1 << 2) /** Global Non-Periodic IN NAK Status */
|
||||
#define DCTL_goutnaksts (1 << 3) /** Global OUT NAK Status */
|
||||
#define DCTL_tstctl_bit_pos 4 /** Test Control */
|
||||
#define DCTL_tstctl_bits (0x7 << DCTL_tstctl_bit_pos)
|
||||
#define DCTL_sgnpinnak (1 << 7) /** Set Global Non-Periodic IN NAK */
|
||||
#define DCTL_cgnpinnak (1 << 8) /** Clear Global Non-Periodic IN NAK */
|
||||
#define DCTL_sgoutnak (1 << 9) /** Set Global OUT NAK */
|
||||
#define DCTL_cgoutnak (1 << 10) /** Clear Global OUT NAK */
|
||||
/** Device Control Register */
|
||||
#define DCTL DEV_REG(0x04)
|
||||
#define DCTL_rmtwkupsig (1 << 0) /** Remote Wakeup */
|
||||
#define DCTL_sftdiscon (1 << 1) /** Soft Disconnect */
|
||||
#define DCTL_gnpinnaksts (1 << 2) /** Global Non-Periodic IN NAK Status */
|
||||
#define DCTL_goutnaksts (1 << 3) /** Global OUT NAK Status */
|
||||
#define DCTL_tstctl_bitp 4 /** Test Control */
|
||||
#define DCTL_tstctl_bits 0x7
|
||||
#define DCTL_sgnpinnak (1 << 7) /** Set Global Non-Periodic IN NAK */
|
||||
#define DCTL_cgnpinnak (1 << 8) /** Clear Global Non-Periodic IN NAK */
|
||||
#define DCTL_sgoutnak (1 << 9) /** Set Global OUT NAK */
|
||||
#define DCTL_cgoutnak (1 << 10) /** Clear Global OUT NAK */
|
||||
/* "documented" in constants.h only */
|
||||
#define DCTL_pwronprgdone (1 << 11) /** Power on Program Done ? */
|
||||
#define DCTL_pwronprgdone (1 << 11) /** Power on Program Done ? */
|
||||
|
||||
#define DCFG_devspd_bits 0x3 /** Device Speed */
|
||||
#define DCFG_devspd_hs_phy_hs 0 /** High speed PHY running at high speed */
|
||||
#define DCFG_devspd_hs_phy_fs 1 /** High speed PHY running at full speed */
|
||||
#define DCFG_nzstsouthshk (1 << 2) /** Non Zero Length Status OUT Handshake */
|
||||
#define DCFG_devadr_bit_pos 4 /** Device Address */
|
||||
#define DCFG_devadr_bits (0x7f << DCFG_devadr_bit_pos)
|
||||
#define DCFG_perfrint_bit_pos 11 /** Periodic Frame Interval */
|
||||
#define DCFG_perfrint_bits (0x3 << DCFG_perfrint_bit_pos)
|
||||
#define DCFG_FRAME_INTERVAL_80 0
|
||||
#define DCFG_FRAME_INTERVAL_85 1
|
||||
#define DCFG_FRAME_INTERVAL_90 2
|
||||
#define DCFG_FRAME_INTERVAL_95 3
|
||||
|
||||
#define DSTS_suspsts (1 << 0) /** Suspend status */
|
||||
#define DSTS_enumspd_bit_pos 1 /** Enumerated speed */
|
||||
#define DSTS_enumspd_bits (0x3 << DSTS_enumspd_bit_pos)
|
||||
/** Device Status Register */
|
||||
#define DSTS DEV_REG(0x08)
|
||||
#define DSTS_suspsts (1 << 0) /** Suspend status */
|
||||
#define DSTS_enumspd_bitp 1 /** Enumerated speed */
|
||||
#define DSTS_enumspd_bits 0x3
|
||||
#define DSTS_ENUMSPD_HS_PHY_30MHZ_OR_60MHZ 0
|
||||
#define DSTS_ENUMSPD_FS_PHY_30MHZ_OR_60MHZ 1
|
||||
#define DSTS_ENUMSPD_LS_PHY_6MHZ 2
|
||||
#define DSTS_ENUMSPD_FS_PHY_48MHZ 3
|
||||
#define DSTS_errticerr (1 << 3) /** Erratic errors ? */
|
||||
#define DSTS_soffn_bit_pos 7 /** Frame or Microframe Number of the received SOF */
|
||||
#define DSTS_soffn_bits (0x3fff << DSTS_soffn_bit_pos)
|
||||
#define DSTS_errticerr (1 << 3) /** Erratic errors ? */
|
||||
#define DSTS_soffn_bitp 7 /** Frame or Microframe Number of the received SOF */
|
||||
#define DSTS_soffn_bits 0x3fff
|
||||
|
||||
/** Device IN Endpoint Common Interrupt Mask Register */
|
||||
#define DIEPMSK DEV_REG(0x10)
|
||||
/* the following apply to DIEPMSK and DIEPINT */
|
||||
#define DIEPINT_xfercompl (1 << 0) /** Transfer complete */
|
||||
#define DIEPINT_epdisabled (1 << 1) /** Endpoint disabled */
|
||||
#define DIEPINT_ahberr (1 << 2) /** AHB error */
|
||||
#define DIEPINT_timeout (1 << 3) /** Timeout handshake (non-iso TX) */
|
||||
#define DIEPINT_intktxfemp (1 << 4) /** IN token received with tx fifo empty */
|
||||
#define DIEPINT_intknepmis (1 << 5) /** IN token received with ep mismatch */
|
||||
#define DIEPINT_inepnakeff (1 << 6) /** IN endpoint NAK effective */
|
||||
#define DIEPINT_emptyintr (1 << 7) /** linux doc broken on this, empty fifo ? */
|
||||
#define DIEPINT_txfifoundrn (1 << 8) /** linux doc void on this, tx fifo underrun ? */
|
||||
|
||||
/** Device OUT Endpoint Common Interrupt Mask Register */
|
||||
#define DOEPMSK DEV_REG(0x14)
|
||||
/* the following apply to DOEPMSK and DOEPINT */
|
||||
#define DOEPINT_xfercompl (1 << 0) /** Transfer complete */
|
||||
#define DOEPINT_epdisabled (1 << 1) /** Endpoint disabled */
|
||||
#define DOEPINT_ahberr (1 << 2) /** AHB error */
|
||||
#define DOEPINT_setup (1 << 3) /** Setup Phase Done (control EPs)*/
|
||||
|
||||
/** Device All Endpoints Interrupt Register */
|
||||
#define DAINT DEV_REG(0x18)
|
||||
/* valid for DAINT and DAINTMSK, for 0<=ep<=15 */
|
||||
#define DAINT_IN_EP(i) (1 << (i))
|
||||
#define DAINT_OUT_EP(i) (1 << ((i) + 16))
|
||||
|
||||
/** Device Endpoints Interrupt Mask Register */
|
||||
#define DAINTMSK DEV_REG(0x1C)
|
||||
|
||||
/** Device IN Token Sequence Learning Queue Read Register 1 */
|
||||
#define DTKNQR1 DEV_REG(0x20)
|
||||
|
||||
/** Device IN Token Sequence Learning Queue Register 2 */
|
||||
#define DTKNQR2 DEV_REG(0x24)
|
||||
|
||||
/** Device IN Token Queue Pop register */
|
||||
#define DTKNQP DEV_REG(0x28)
|
||||
|
||||
/* fixme: those registers are not present in registers.h but are in dwc_otgh_regs.h.
|
||||
* the previous registers exists but has a different name :( */
|
||||
/** Device VBUS discharge register*/
|
||||
#define DVBUSDIS DEV_REG(0x28)
|
||||
|
||||
/** Device VBUS pulse register */
|
||||
#define DVBUSPULSE DEV_REG(0x2C)
|
||||
|
||||
/** Device IN Token Queue Read Register 3 (RO) */
|
||||
#define DTKNQR3 DEV_REG(0x30)
|
||||
|
||||
/** Device Thresholding control register */
|
||||
#define DTHRCTL DEV_REG(0x30)
|
||||
#define DTHRCTL_non_iso_thr_en (1 << 0)
|
||||
#define DTHRCTL_iso_thr_en (1 << 1)
|
||||
#define DTHRCTL_tx_thr_len_bitp 2
|
||||
#define DTHRCTL_tx_thr_len_bits 0x1FF
|
||||
#define DTHRCTL_rx_thr_en (1 << 16)
|
||||
#define DTHRCTL_rx_thr_len_bitp 17
|
||||
#define DTHRCTL_rx_thr_len_bits 0x1FF
|
||||
|
||||
/** Device IN Token Queue Read Register 4 (RO) */
|
||||
#define DTKNQR4 DEV_REG(0x34)
|
||||
|
||||
/** Device IN EPs empty Inr. Mask Register */
|
||||
#define FFEMPTYMSK DEV_REG(0x34)
|
||||
|
||||
#define DTHRCTL_non_iso_thr_en (1 << 0)
|
||||
#define DTHRCTL_iso_thr_en (1 << 1)
|
||||
#define DTHRCTL_tx_thr_len_bit_pos 2
|
||||
#define DTHRCTL_tx_thr_len_bits (0x1FF << DTHRCTL_tx_thr_len_bit_pos)
|
||||
#define DTHRCTL_rx_thr_en (1 << 16)
|
||||
#define DTHRCTL_rx_thr_len_bit_pos 17
|
||||
#define DTHRCTL_rx_thr_len_bits (0x1FF << DTHRCTL_rx_thr_len_bit_pos)
|
||||
|
||||
/* 0<=ep<=15, you can use ep=0 */
|
||||
/** Device IN Endpoint (ep) Control Register */
|
||||
|
|
@ -293,23 +346,6 @@
|
|||
/** Device IN Endpoint (ep) Transmit FIFO Status Register */
|
||||
#define DTXFSTS(ep) DEV_REG(0x100 + (ep) * 0x20 + 0x18)
|
||||
|
||||
/* the following also apply to DIEPMSK */
|
||||
#define DIEPINT_xfercompl (1 << 0) /** Transfer complete */
|
||||
#define DIEPINT_epdisabled (1 << 1) /** Endpoint disabled */
|
||||
#define DIEPINT_ahberr (1 << 2) /** AHB error */
|
||||
#define DIEPINT_timeout (1 << 3) /** Timeout handshake (non-iso TX) */
|
||||
#define DIEPINT_intktxfemp (1 << 4) /** IN token received with tx fifo empty */
|
||||
#define DIEPINT_intknepmis (1 << 5) /** IN token received with ep mismatch */
|
||||
#define DIEPINT_inepnakeff (1 << 6) /** IN endpoint NAK effective */
|
||||
#define DIEPINT_emptyintr (1 << 7) /** linux doc broken on this, empty fifo ? */
|
||||
#define DIEPINT_txfifoundrn (1 << 8) /** linux doc void on this, tx fifo underrun ? */
|
||||
|
||||
/* the following also apply to DOEPMSK */
|
||||
#define DOEPINT_xfercompl (1 << 0) /** Transfer complete */
|
||||
#define DOEPINT_epdisabled (1 << 1) /** Endpoint disabled */
|
||||
#define DOEPINT_ahberr (1 << 2) /** AHB error */
|
||||
#define DOEPINT_setup (1 << 3) /** Setup Phase Done (control EPs)*/
|
||||
|
||||
/* 0<=ep<=15, you can use ep=0 */
|
||||
/** Device OUT Endpoint (ep) Control Register */
|
||||
#define DOEPCTL(ep) DEV_REG(0x300 + (ep) * 0x20)
|
||||
|
|
@ -332,8 +368,8 @@
|
|||
* 2'b01: 32
|
||||
* 2'b10: 16
|
||||
* 2'b11: 8 */
|
||||
#define DEPCTL_mps_bitp 0
|
||||
#define DEPCTL_mps_bits 0x7ff
|
||||
#define DEPCTL_mps_bit_pos 0
|
||||
#define DEPCTL_MPS_64 0
|
||||
#define DEPCTL_MPS_32 1
|
||||
#define DEPCTL_MPS_16 2
|
||||
|
|
@ -341,8 +377,8 @@
|
|||
/** Next Endpoint
|
||||
* IN EPn/IN EP0
|
||||
* OUT EPn/OUT EP0 - reserved */
|
||||
#define DEPCTL_nextep_bit_pos 11
|
||||
#define DEPCTL_nextep_bits (0xf << DEPCTL_nextep_bit_pos)
|
||||
#define DEPCTL_nextep_bitp 11
|
||||
#define DEPCTL_nextep_bits 0xf
|
||||
#define DEPCTL_usbactep (1 << 15) /** USB Active Endpoint */
|
||||
/** Endpoint DPID (INTR/Bulk IN and OUT endpoints)
|
||||
* This field contains the PID of the packet going to
|
||||
|
|
@ -365,8 +401,8 @@
|
|||
* 2'b01: Isochronous
|
||||
* 2'b10: Bulk
|
||||
* 2'b11: Interrupt */
|
||||
#define DEPCTL_eptype_bit_pos 18
|
||||
#define DEPCTL_eptype_bits (0x3 << DEPCTL_eptype_bit_pos)
|
||||
#define DEPCTL_eptype_bitp 18
|
||||
#define DEPCTL_eptype_bits 0x3
|
||||
/** Snoop Mode
|
||||
* OUT EPn/OUT EP0
|
||||
* IN EPn/IN EP0 - reserved */
|
||||
|
|
@ -375,8 +411,8 @@
|
|||
/** Tx Fifo Number
|
||||
* IN EPn/IN EP0
|
||||
* OUT EPn/OUT EP0 - reserved */
|
||||
#define DEPCTL_txfnum_bit_pos 22
|
||||
#define DEPCTL_txfnum_bits (0xf << DEPCTL_txfnum_bit_pos)
|
||||
#define DEPCTL_txfnum_bitp 22
|
||||
#define DEPCTL_txfnum_bits 0xf
|
||||
|
||||
#define DEPCTL_cnak (1 << 26) /** Clear NAK */
|
||||
#define DEPCTL_snak (1 << 27) /** Set NAK */
|
||||
|
|
@ -403,21 +439,17 @@
|
|||
|
||||
/* valid for any D{I,O}EPTSIZi with 1<=i<=15, NOT for i=0 ! */
|
||||
#define DEPTSIZ_xfersize_bits 0x7ffff /** Transfer Size */
|
||||
#define DEPTSIZ_pkcnt_bit_pos 19 /** Packet Count */
|
||||
#define DEPTSIZ_pkcnt_bits (0x3ff << DEPTSIZ_pkcnt_bit_pos)
|
||||
#define DEPTSIZ_mc_bit_pos 29 /** Multi Count - Periodic IN endpoints */
|
||||
#define DEPTSIZ_mc_bits (0x3 << DEPTSIZ_mc_bit_pos)
|
||||
#define DEPTSIZ_pkcnt_bitp 19 /** Packet Count */
|
||||
#define DEPTSIZ_pkcnt_bits 0x3ff
|
||||
#define DEPTSIZ_mc_bitp 29 /** Multi Count - Periodic IN endpoints */
|
||||
#define DEPTSIZ_mc_bits 0x3
|
||||
|
||||
/* idem but for i=0 */
|
||||
#define DEPTSIZ0_xfersize_bits 0x7f /** Transfer Size */
|
||||
#define DEPTSIZ0_pkcnt_bit_pos 19 /** Packet Count */
|
||||
#define DEPTSIZ0_pkcnt_bits (0x1 << DEPTSIZ0_pkcnt_bit_pos)
|
||||
#define DEPTSIZ0_supcnt_bit_pos 29 /** Setup Packet Count (DOEPTSIZ0 Only) */
|
||||
#define DEPTSIZ0_supcnt_bits (0x3 << DEPTSIZ0_supcnt_bit_pos)
|
||||
|
||||
/* valid for DAINT and DAINTMSK, for 0<=ep<=15 */
|
||||
#define DAINT_IN_EP(i) (1 << (i))
|
||||
#define DAINT_OUT_EP(i) (1 << ((i) + 16))
|
||||
#define DEPTSIZ0_xfersize_bits 0x7f /** Transfer Size */
|
||||
#define DEPTSIZ0_pkcnt_bitp 19 /** Packet Count */
|
||||
#define DEPTSIZ0_pkcnt_bits 0x1
|
||||
#define DEPTSIZ0_supcnt_bitp 29 /** Setup Packet Count (DOEPTSIZ0 Only) */
|
||||
#define DEPTSIZ0_supcnt_bits 0x3
|
||||
|
||||
/**
|
||||
* Parameters
|
||||
|
|
|
|||
Loading…
Reference in a new issue