365 lines
12 KiB
C
365 lines
12 KiB
C
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/***************************************************************************
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* __________ __ ___.
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* Open \______ \ ____ ____ | | _\_ |__ _______ ___
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* Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
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* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
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* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
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* \/ \/ \/ \/ \/
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* $Id$
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*
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* Copyright (c) 2010 Michael Sevakis
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*
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* i.MX31 IOMUXC helper routines
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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*
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* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
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* KIND, either express or implied.
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*
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****************************************************************************/
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#ifndef _IOMUXC_IMX31_H_
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#define _IOMUXC_IMX31_H_
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enum IMX31_IOMUXC_PINS
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{
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IOMUXC_TTM_PAD = 0,
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IOMUXC_CSPI3_SPI_RDY = 1,
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IOMUXC_CSPI3_SCLK = 2,
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IOMUXC_CSPI3_MISO = 3,
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IOMUXC_CSPI3_MOSI = 4,
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IOMUXC_CLKSS = 5,
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IOMUXC_CE_CONTROL = 6,
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IOMUXC_ATA_RST_B = 7,
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IOMUXC_ATA_DMACK = 8,
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IOMUXC_ATA_DIOW = 9,
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IOMUXC_ATA_DIOR = 10,
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IOMUXC_ATA_CS1 = 11,
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IOMUXC_ATA_CS0 = 12,
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IOMUXC_SD1_DATA3 = 13,
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IOMUXC_SD1_DATA2 = 14,
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IOMUXC_SD1_DATA1 = 15,
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IOMUXC_SD1_DATA0 = 16,
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IOMUXC_SD1_CLK = 17,
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IOMUXC_SD1_CMD = 18,
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IOMUXC_D3_SPL = 19,
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IOMUXC_D3_CLS = 20,
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IOMUXC_D3_REV = 21,
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IOMUXC_CONTRAST = 22,
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IOMUXC_VSYNC3 = 23,
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IOMUXC_READ = 24,
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IOMUXC_WRITE = 25,
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IOMUXC_PAR_RS = 26,
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IOMUXC_SER_RS = 27,
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IOMUXC_LCS1 = 28,
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IOMUXC_LCS0 = 29,
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IOMUXC_SD_D_CLK = 30,
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IOMUXC_SD_D_IO = 31,
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IOMUXC_SD_D_I = 32,
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IOMUXC_DRDY0 = 33,
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IOMUXC_FPSHIFT = 34,
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IOMUXC_HSYNC = 35,
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IOMUXC_VSYNC0 = 36,
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IOMUXC_LD17 = 37,
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IOMUXC_LD16 = 38,
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IOMUXC_LD15 = 39,
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IOMUXC_LD14 = 40,
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IOMUXC_LD13 = 41,
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IOMUXC_LD12 = 42,
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IOMUXC_LD11 = 43,
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IOMUXC_LD10 = 44,
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IOMUXC_LD9 = 45,
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IOMUXC_LD8 = 46,
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IOMUXC_LD7 = 47,
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IOMUXC_LD6 = 48,
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IOMUXC_LD5 = 49,
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IOMUXC_LD4 = 50,
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IOMUXC_LD3 = 51,
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IOMUXC_LD2 = 52,
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IOMUXC_LD1 = 53,
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IOMUXC_LD0 = 54,
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IOMUXC_USBH2_DATA1 = 55,
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IOMUXC_USBH2_DATA0 = 56,
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IOMUXC_USBH2_NXT = 57,
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IOMUXC_USBH2_STP = 58,
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IOMUXC_USBH2_DIR = 59,
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IOMUXC_USBH2_CLK = 60,
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IOMUXC_USBOTG_DATA7 = 61,
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IOMUXC_USBOTG_DATA6 = 62,
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IOMUXC_USBOTG_DATA5 = 63,
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IOMUXC_USBOTG_DATA4 = 64,
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IOMUXC_USBOTG_DATA3 = 65,
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IOMUXC_USBOTG_DATA2 = 66,
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IOMUXC_USBOTG_DATA1 = 67,
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IOMUXC_USBOTG_DATA0 = 68,
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IOMUXC_USBOTG_NXT = 69,
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IOMUXC_USBOTG_STP = 70,
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IOMUXC_USBOTG_DIR = 71,
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IOMUXC_USBOTG_CLK = 72,
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IOMUXC_USB_BYP = 73,
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IOMUXC_USB_OC = 74,
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IOMUXC_USB_PWR = 75,
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IOMUXC_SJC_MOD = 76,
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IOMUXC_DE_B = 77,
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IOMUXC_TRSTB = 78,
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IOMUXC_TDO = 79,
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IOMUXC_TDI = 80,
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IOMUXC_TMS = 81,
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IOMUXC_TCK = 82,
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IOMUXC_RTCK = 83,
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IOMUXC_KEY_COL7 = 84,
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IOMUXC_KEY_COL6 = 85,
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IOMUXC_KEY_COL5 = 86,
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IOMUXC_KEY_COL4 = 87,
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IOMUXC_KEY_COL3 = 88,
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IOMUXC_KEY_COL2 = 89,
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IOMUXC_KEY_COL1 = 90,
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IOMUXC_KEY_COL0 = 91,
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IOMUXC_KEY_ROW7 = 92,
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IOMUXC_KEY_ROW6 = 93,
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IOMUXC_KEY_ROW5 = 94,
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IOMUXC_KEY_ROW4 = 95,
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IOMUXC_KEY_ROW3 = 96,
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IOMUXC_KEY_ROW2 = 97,
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IOMUXC_KEY_ROW1 = 98,
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IOMUXC_KEY_ROW0 = 99,
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IOMUXC_BATT_LINE = 100,
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IOMUXC_CTS2 = 101,
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IOMUXC_RTS2 = 102,
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IOMUXC_TXD2 = 103,
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IOMUXC_RXD2 = 104,
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IOMUXC_DTR_DCE2 = 105,
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IOMUXC_DCD_DTE1 = 106,
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IOMUXC_RI_DTE1 = 107,
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IOMUXC_DSR_DTE1 = 108,
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IOMUXC_DTR_DTE1 = 109,
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IOMUXC_DCD_DCE1 = 110,
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IOMUXC_RI_DCE1 = 111,
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IOMUXC_DSR_DCE1 = 112,
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IOMUXC_DTR_DCE1 = 113,
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IOMUXC_CTS1 = 114,
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IOMUXC_RTS1 = 115,
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IOMUXC_TXD1 = 116,
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IOMUXC_RXD1 = 117,
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IOMUXC_CSPI2_SPI_RDY = 118,
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IOMUXC_CSPI2_SCLK = 119,
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IOMUXC_CSPI2_SS2 = 120,
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IOMUXC_CSPI2_SS1 = 121,
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IOMUXC_CSPI2_SS0 = 122,
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IOMUXC_CSPI2_MISO = 123,
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IOMUXC_CSPI2_MOSI = 124,
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IOMUXC_CSPI1_SPI_RDY = 125,
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IOMUXC_CSPI1_SCLK = 126,
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IOMUXC_CSPI1_SS2 = 127,
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IOMUXC_CSPI1_SS1 = 128,
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IOMUXC_CSPI1_SS0 = 129,
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IOMUXC_CSPI1_MISO = 130,
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IOMUXC_CSPI1_MOSI = 131,
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IOMUXC_SFS6 = 132,
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IOMUXC_SCK6 = 133,
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IOMUXC_SRXD6 = 134,
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IOMUXC_STXD6 = 135,
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IOMUXC_SFS5 = 136,
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IOMUXC_SCK5 = 137,
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IOMUXC_SRXD5 = 138,
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IOMUXC_STXD5 = 139,
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IOMUXC_SFS4 = 140,
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IOMUXC_SCK4 = 141,
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IOMUXC_SRXD4 = 142,
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IOMUXC_STXD4 = 143,
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IOMUXC_SFS3 = 144,
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IOMUXC_SCK3 = 145,
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IOMUXC_SRXD3 = 146,
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IOMUXC_STXD3 = 147,
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IOMUXC_I2C_DAT = 148,
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IOMUXC_I2C_CLK = 149,
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IOMUXC_CSI_PIXCLK = 150,
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IOMUXC_CSI_HSYNC = 151,
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IOMUXC_CSI_VSYNC = 152,
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IOMUXC_CSI_MCLK = 153,
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IOMUXC_CSI_D15 = 154,
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IOMUXC_CSI_D14 = 155,
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IOMUXC_CSI_D13 = 156,
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IOMUXC_CSI_D12 = 157,
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IOMUXC_CSI_D11 = 158,
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IOMUXC_CSI_D10 = 159,
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IOMUXC_CSI_D9 = 160,
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IOMUXC_CSI_D8 = 161,
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IOMUXC_CSI_D7 = 162,
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IOMUXC_CSI_D6 = 163,
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IOMUXC_CSI_D5 = 164,
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IOMUXC_CSI_D4 = 165,
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IOMUXC_M_GRANT = 166,
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IOMUXC_M_REQUEST = 167,
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IOMUXC_PC_POE = 168,
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IOMUXC_PC_RW_B = 169,
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IOMUXC_IOIS16 = 170,
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IOMUXC_PC_RST = 171,
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IOMUXC_PC_BVD2 = 172,
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IOMUXC_PC_BVD1 = 173,
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IOMUXC_PC_VS2 = 174,
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IOMUXC_PC_VS1 = 175,
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IOMUXC_PC_PWRON = 176,
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IOMUXC_PC_READY = 177,
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IOMUXC_PC_WAIT_B = 178,
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IOMUXC_PC_CD2_B = 179,
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IOMUXC_PC_CD1_B = 180,
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IOMUXC_D0 = 181,
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IOMUXC_D1 = 182,
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IOMUXC_D2 = 183,
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IOMUXC_D3 = 184,
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IOMUXC_D4 = 185,
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IOMUXC_D5 = 186,
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IOMUXC_D6 = 187,
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IOMUXC_D7 = 188,
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IOMUXC_D8 = 189,
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IOMUXC_D9 = 190,
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IOMUXC_D10 = 191,
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IOMUXC_D11 = 192,
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IOMUXC_D12 = 193,
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IOMUXC_D13 = 194,
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IOMUXC_D14 = 195,
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IOMUXC_D15 = 196,
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IOMUXC_NFRB = 197,
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IOMUXC_NFCE_B = 198,
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IOMUXC_NFWP_B = 199,
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IOMUXC_NFCLE = 200,
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IOMUXC_NFALE = 201,
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IOMUXC_NFRE_B = 202,
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IOMUXC_NFWE_B = 203,
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IOMUXC_SDQS3 = 204,
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IOMUXC_SDQS2 = 205,
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IOMUXC_SDQS1 = 206,
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IOMUXC_SDQS0 = 207,
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IOMUXC_RESERVED0 = 208,
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IOMUXC_SDCLK = 209,
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IOMUXC_SDCKE1 = 210,
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IOMUXC_SDCKE0 = 211,
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IOMUXC_SDWE = 212,
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IOMUXC_CAS = 213,
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IOMUXC_RAS = 214,
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IOMUXC_RW = 215,
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IOMUXC_BCLK = 216,
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IOMUXC_LBA = 217,
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IOMUXC_ECB = 218,
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IOMUXC_CS5 = 219,
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IOMUXC_CS4 = 220,
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IOMUXC_CS3 = 221,
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IOMUXC_CS2 = 222,
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IOMUXC_CS1 = 223,
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IOMUXC_CS0 = 224,
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IOMUXC_OE = 225,
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IOMUXC_EB1 = 226,
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IOMUXC_EB0 = 227,
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IOMUXC_DQM3 = 228,
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IOMUXC_DQM2 = 229,
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IOMUXC_DQM1 = 230,
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IOMUXC_DQM0 = 231,
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IOMUXC_SD31 = 232,
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IOMUXC_SD30 = 233,
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IOMUXC_SD29 = 234,
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IOMUXC_SD28 = 235,
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IOMUXC_SD27 = 236,
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IOMUXC_SD26 = 237,
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IOMUXC_SD25 = 238,
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IOMUXC_SD24 = 239,
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IOMUXC_SD23 = 240,
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IOMUXC_SD22 = 241,
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IOMUXC_SD21 = 242,
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IOMUXC_SD20 = 243,
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IOMUXC_SD19 = 244,
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IOMUXC_SD18 = 245,
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IOMUXC_SD17 = 246,
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IOMUXC_SD16 = 247,
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IOMUXC_SD15 = 248,
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IOMUXC_SD14 = 249,
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IOMUXC_SD13 = 250,
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IOMUXC_SD12 = 251,
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IOMUXC_SD11 = 252,
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IOMUXC_SD10 = 253,
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IOMUXC_SD9 = 254,
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IOMUXC_SD8 = 255,
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IOMUXC_SD7 = 256,
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IOMUXC_SD6 = 257,
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IOMUXC_SD5 = 258,
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IOMUXC_SD4 = 259,
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IOMUXC_SD3 = 260,
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IOMUXC_SD2 = 261,
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IOMUXC_SD1 = 262,
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IOMUXC_SD0 = 263,
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IOMUXC_SDBA0 = 264,
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IOMUXC_SDBA1 = 265,
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IOMUXC_A25 = 266,
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IOMUXC_A24 = 267,
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IOMUXC_A23 = 268,
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IOMUXC_A22 = 269,
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IOMUXC_A21 = 270,
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IOMUXC_A20 = 271,
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IOMUXC_A19 = 272,
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IOMUXC_A18 = 273,
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IOMUXC_A17 = 274,
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IOMUXC_A16 = 275,
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IOMUXC_A15 = 276,
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IOMUXC_A14 = 277,
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IOMUXC_A13 = 278,
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IOMUXC_A12 = 279,
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IOMUXC_A11 = 280,
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IOMUXC_MA10 = 281,
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IOMUXC_A10 = 282,
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IOMUXC_A9 = 283,
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IOMUXC_A8 = 284,
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IOMUXC_A7 = 285,
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IOMUXC_A6 = 286,
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IOMUXC_A5 = 287,
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IOMUXC_A4 = 288,
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IOMUXC_A3 = 289,
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IOMUXC_A2 = 290,
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IOMUXC_A1 = 291,
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IOMUXC_A0 = 292,
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IOMUXC_VPG1 = 293,
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IOMUXC_VPG0 = 294,
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IOMUXC_DVFS1 = 295,
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IOMUXC_DVFS0 = 296,
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||
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IOMUXC_VSTBY = 297,
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||
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IOMUXC_POWER_FAIL = 298,
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||
|
|
IOMUXC_CKIL = 299,
|
||
|
|
IOMUXC_BOOT_MODE4 = 300,
|
||
|
|
IOMUXC_BOOT_MODE3 = 301,
|
||
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|
IOMUXC_BOOT_MODE2 = 302,
|
||
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|
IOMUXC_BOOT_MODE1 = 303,
|
||
|
|
IOMUXC_BOOT_MODE0 = 304,
|
||
|
|
IOMUXC_CLKO = 305,
|
||
|
|
IOMUXC_POR_B = 306,
|
||
|
|
IOMUXC_RESET_IN_B = 307,
|
||
|
|
IOMUXC_CKIH = 308,
|
||
|
|
IOMUXC_SIMPD0 = 309,
|
||
|
|
IOMUXC_SRX0 = 310,
|
||
|
|
IOMUXC_STX0 = 311,
|
||
|
|
IOMUXC_SVEN0 = 312,
|
||
|
|
IOMUXC_SRST0 = 313,
|
||
|
|
IOMUXC_SCLK0 = 314,
|
||
|
|
IOMUXC_GPIO3_1 = 315,
|
||
|
|
IOMUXC_GPIO3_0 = 316,
|
||
|
|
IOMUXC_GPIO1_6 = 317,
|
||
|
|
IOMUXC_GPIO1_5 = 318,
|
||
|
|
IOMUXC_GPIO1_4 = 319,
|
||
|
|
IOMUXC_GPIO1_3 = 320,
|
||
|
|
IOMUXC_GPIO1_2 = 321,
|
||
|
|
IOMUXC_GPIO1_1 = 322,
|
||
|
|
IOMUXC_GPIO1_0 = 323,
|
||
|
|
IOMUXC_PWMO = 324,
|
||
|
|
IOMUXC_WATCHDOG_RST = 325,
|
||
|
|
IOMUXC_COMPARE = 326,
|
||
|
|
IOMUXC_CAPTURE = 327,
|
||
|
|
};
|
||
|
|
|
||
|
|
/* Set the pin multiplexing configuration (functional, GPIO, etc.) */
|
||
|
|
void iomuxc_set_pin_mux(enum IMX31_IOMUXC_PINS pin, unsigned long mux);
|
||
|
|
|
||
|
|
/* Set the pin pad configuration (keeper, drive strength, etc.) */
|
||
|
|
void iomuxc_set_pad_config(enum IMX31_IOMUXC_PINS pin, unsigned long config);
|
||
|
|
|
||
|
|
#endif /* _IOMUXC_IMX31_H_ */
|