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i.MX31: Add some enums and a couple helper functions to make dealing with pin muxing and pad configuration a bit more sane. Convert any existing code which changes mux/pad settings to use helpers.

Browse source 
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@25698 a1c6a512-1295-4272-9138-f99709370657
This commit is contained in:
Michael Sevakis 2010-04-23 13:46:04 +00:00
parent 57dc493db5
commit 6cee7579db
5 changed files with 477 additions and 276 deletions
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1
firmware/SOURCES
View file

@ -877,6 +877,7 @@ target/arm/imx31/debug-imx31.c
target/arm/imx31/dvfs_dptc-imx31.c
target/arm/imx31/gpio-imx31.c
target/arm/imx31/i2c-imx31.c
target/arm/imx31/iomuxc-imx31.c
target/arm/imx31/mc13783-imx31.c
target/arm/imx31/mmu-imx31.c
target/arm/imx31/rolo_restart.S

295
firmware/export/imx31l.h
View file

@ -135,269 +135,56 @@
#define IIM_SREV_2_0_1L 0x29 /* i.MX31L 2.0/2.0.1, M91E */
/* IOMUXC */
#define IOMUXC_(o) (*(REG32_PTR_T)(IOMUXC_BASE_ADDR+(o)))
#define IOMUXC_GPR (*(REG32_PTR_T)(IOMUXC_BASE_ADDR+0x008))
/* GPR */
#define IOMUXC_GPR IOMUXC_(0x008)
/* SW_MUX_CTL_* */
#define IOMUXC_MUX_OUT (0x7 << 4)
#define IOMUXC_MUX_OUT_POS (4)
#define IOMUXC_MUX_IN (0xf << 0)
#define IOMUXC_MUX_IN_POS (0)
#define IOMUXC_MUX_MASK (0x7f)
/* SW_MUX_CTL */
#define SW_MUX_CTL_CSPI3_MISO_CSPI3_SCLK_CSPI3_SPI_RDY_TTM_PAD IOMUXC_(0x00C)
#define SW_MUX_CTL_ATA_RESET_B_CE_CONTROL_CLKSS_CSPI3_MOSI IOMUXC_(0x010)
#define SW_MUX_CTL_ATA_CS1_ATA_DIOR_ATA_DIOW_ATA_DMACK IOMUXC_(0x014)
#define SW_MUX_CTL_SD1_DATA1_SD1_DATA2_SD1_DATA3_ATA_CS0 IOMUXC_(0x018)
#define SW_MUX_CTL_D3_SPL_SD1_CMD_SD1_CLK_SD1_DATA0 IOMUXC_(0x01C)
#define SW_MUX_CTL_VSYNC3_CONTRAST_D3_REV_D3_CLS IOMUXC_(0x020)
#define SW_MUX_CTL_SER_RS_PAR_RS_WRITE_READ IOMUXC_(0x024)
#define SW_MUX_CTL_SD_D_IO_SD_D_CLK_LCS0_LCS1 IOMUXC_(0x028)
#define SW_MUX_CTL_HSYNC_FPSHIFT_DRDY0_SD_D_I IOMUXC_(0x02C)
#define SW_MUX_CTL_LD15_LD16_LD17_VSYNC0 IOMUXC_(0x030)
#define SW_MUX_CTL_LD11_LD12_LD13_LD14 IOMUXC_(0x034)
#define SW_MUX_CTL_LD7_LD8_LD9_LD10 IOMUXC_(0x038)
#define SW_MUX_CTL_LD3_LD4_LD5_LD6 IOMUXC_(0x03C)
#define SW_MUX_CTL_USBH2_DATA1_LD0_LD1_LD2 IOMUXC_(0x040)
#define SW_MUX_CTL_USBH2_DIR_USBH2_STP_USBH2_NXT_USBH2_DATA0 IOMUXC_(0x044)
#define SW_MUX_CTL_USBOTG_DATA5_USBOTG_DATA6_USBOTG_DATA7_USBH2_CLK IOMUXC_(0x048)
#define SW_MUX_CTL_USBOTG_DATA1_USBOTG_DATA2_USBOTG_DATA3_USBOTG_DATA4 IOMUXC_(0x04C)
#define SW_MUX_CTL_USBOTG_DIR_USBOTG_STP_USBOTG_NXT_USBOTG_DATA0 IOMUXC_(0x050)
#define SW_MUX_CTL_USB_PWR_USB_OC_USB_BYP_USBOTG_CLK IOMUXC_(0x054)
#define SW_MUX_CTL_TDO_TRSTB_DE_B_SJC_MOD IOMUXC_(0x058)
#define SW_MUX_CTL_RTCK_TCK_TMS_TDI IOMUXC_(0x05C)
#define SW_MUX_CTL_KEY_COL4_KEY_COL5_KEY_COL6_KEY_COL7 IOMUXC_(0x060)
#define SW_MUX_CTL_KEY_COL0_KEY_COL1_KEY_COL2_KEY_COL3 IOMUXC_(0x064)
#define SW_MUX_CTL_KEY_ROW4_KEY_ROW5_KEY_ROW6_KEY_ROW7 IOMUXC_(0x068)
#define SW_MUX_CTL_KEY_ROW0_KEY_ROW1_KEY_ROW2_KEY_ROW3 IOMUXC_(0x06C)
#define SW_MUX_CTL_TXD2_RTS2_CTS2_BATT_LINE IOMUXC_(0x070)
#define SW_MUX_CTL_RI_DTE1_DCD_DTE1_DTR_DCE2_RXD2 IOMUXC_(0x074)
#define SW_MUX_CTL_RI_DCE1_DCD_DCE1_DTR_DTE1_DSR_DTE1 IOMUXC_(0x078)
#define SW_MUX_CTL_RTS1_CTS1_DTR_DCE1_DSR_DCE1 IOMUXC_(0x07C)
#define SW_MUX_CTL_CSPI2_SCLK_CSPI2_SPI_RDY_RXD1_TXD1 IOMUXC_(0x080)
#define SW_MUX_CTL_CSPI2_MISO_CSPI2_SS0_CSPI2_SS1_CSPI2_SS2 IOMUXC_(0x084)
#define SW_MUX_CTL_CSPI1_SS2_CSPI1_SCLK_CSPI1_SPI_RDY_CSPI2_MOSI IOMUXC_(0x088)
#define SW_MUX_CTL_CSPI1_MOSI_CSPI1_MISO_CSPI1_SS0_CSPI1_SS1 IOMUXC_(0x08C)
#define SW_MUX_CTL_STXD6_SRXD6_SCK6_SFS6 IOMUXC_(0x090)
#define SW_MUX_CTL_STXD5_SRXD5_SCK5_SFS5 IOMUXC_(0x094)
#define SW_MUX_CTL_STXD4_SRXD4_SCK4_SFS4 IOMUXC_(0x098)
#define SW_MUX_CTL_STXD3_SRXD3_SCK3_SFS3 IOMUXC_(0x09C)
#define SW_MUX_CTL_CSI_HSYNC_CSI_PIXCLK_I2C_CLK_I2C_DAT IOMUXC_(0x0A0)
#define SW_MUX_CTL_CSI_D14_CSI_D15_CSI_MCLK_CSI_VSYNC IOMUXC_(0x0A4)
#define SW_MUX_CTL_CSI_D10_CSI_D11_CSI_D12_CSI_D13 IOMUXC_(0x0A8)
#define SW_MUX_CTL_CSI_D6_CSI_D7_CSI_D8_CSI_D9 IOMUXC_(0x0AC)
#define SW_MUX_CTL_M_REQUEST_M_GRANT_CSI_D4_CSI_D5 IOMUXC_(0x0B0)
#define SW_MUX_CTL_PC_RST_IOIS16_PC_RW_B_PC_POE IOMUXC_(0x0B4)
#define SW_MUX_CTL_PC_VS1_PC_VS2_PC_BVD1_PC_BVD2 IOMUXC_(0x0B8)
#define SW_MUX_CTL_PC_CD2_B_PC_WAIT_B_PC_READY_PC_PWRON IOMUXC_(0x0BC)
#define SW_MUX_CTL_D2_D1_D0_PC_CD1_B IOMUXC_(0x0C0)
#define SW_MUX_CTL_D6_D5_D4_D3 IOMUXC_(0x0C4)
#define SW_MUX_CTL_D10_D9_D8_D7 IOMUXC_(0x0C8)
#define SW_MUX_CTL_D14_D13_D12_D11 IOMUXC_(0x0CC)
#define SW_MUX_CTL_NFWP_B_NFCE_B_NFRB_D15 IOMUXC_(0x0D0)
#define SW_MUX_CTL_NFWE_B_NFRE_B_NFALE_NFCLE IOMUXC_(0x0D4)
#define SW_MUX_CTL_SDQS0_SDQS1_SDQS2_SDQS3 IOMUXC_(0x0D8)
#define SW_MUX_CTL_SDCKE0_SDCKE1_SDCLK_SDCLK_B IOMUXC_(0x0DC)
#define SW_MUX_CTL_RW_RAS_CAS_SDWE IOMUXC_(0x0E0)
#define SW_MUX_CTL_CS5_ECB_LBA_BCLK IOMUXC_(0x0E4)
#define SW_MUX_CTL_CS1_CS2_CS3_CS4 IOMUXC_(0x0E8)
#define SW_MUX_CTL_EB0_EB1_OE_CS0 IOMUXC_(0x0EC)
#define SW_MUX_CTL_DQM0_DQM1_DQM2_DQM3 IOMUXC_(0x0F0)
#define SW_MUX_CTL_SD28_SD29_SD30_SD31 IOMUXC_(0x0F4)
#define SW_MUX_CTL_SD24_SD25_SD26_SD27 IOMUXC_(0x0F8)
#define SW_MUX_CTL_SD20_SD21_SD22_SD23 IOMUXC_(0x0FC)
#define SW_MUX_CTL_SD16_SD17_SD18_SD19 IOMUXC_(0x100)
#define SW_MUX_CTL_SD12_SD13_SD14_SD15 IOMUXC_(0x104)
#define SW_MUX_CTL_SD8_SD9_SD10_SD11 IOMUXC_(0x108)
#define SW_MUX_CTL_SD4_SD5_SD6_SD7 IOMUXC_(0x10C)
#define SW_MUX_CTL_SD0_SD1_SD2_SD3 IOMUXC_(0x110)
#define SW_MUX_CTL_A24_A25_SDBA1_SDBA0 IOMUXC_(0x114)
#define SW_MUX_CTL_A20_A21_A22_A23 IOMUXC_(0x118)
#define SW_MUX_CTL_A16_A17_A18_A19 IOMUXC_(0x11C)
#define SW_MUX_CTL_A12_A13_A14_A15 IOMUXC_(0x120)
#define SW_MUX_CTL_A9_A10_MA10_A11 IOMUXC_(0x124)
#define SW_MUX_CTL_A5_A6_A7_A8 IOMUXC_(0x128)
#define SW_MUX_CTL_A1_A2_A3_A4 IOMUXC_(0x12C)
#define SW_MUX_CTL_DVFS1_VPG0_VPG1_A0 IOMUXC_(0x130)
#define SW_MUX_CTL_CKIL_POWER_FAIL_VSTBY_DVFS0 IOMUXC_(0x134)
#define SW_MUX_CTL_BOOT_MODE1_BOOT_MODE2_BOOT_MODE3_BOOT_MODE4 IOMUXC_(0x138)
#define SW_MUX_CTL_RESET_IN_B_POR_B_CLKO_BOOT_MODE0 IOMUXC_(0x13C)
#define SW_MUX_CTL_STX0_SRX0_SIMPD0_CKIH IOMUXC_(0x140)
#define SW_MUX_CTL_GPIO3_1_SCLK0_SRST0_SVEN0 IOMUXC_(0x144)
#define SW_MUX_CTL_GPIO1_4_GPIO1_5_GPIO1_6_GPIO3_0 IOMUXC_(0x148)
#define SW_MUX_CTL_GPIO1_0_GPIO1_1_GPIO1_2_GPIO1_3 IOMUXC_(0x14C)
#define SW_MUX_CTL_CAPTURE_COMPARE_WATCHDOG_RST_PWMO IOMUXC_(0x150)
#define IOMUXC_MUX_OUT_GPIO (0x0 << IOMUXC_MUX_OUT_POS)
#define IOMUXC_MUX_OUT_FUNCTIONAL (0x1 << IOMUXC_MUX_OUT_POS)
#define IOMUXC_MUX_OUT_ALT1 (0x2 << IOMUXC_MUX_OUT_POS)
#define IOMUXC_MUX_OUT_ALT2 (0x3 << IOMUXC_MUX_OUT_POS)
#define IOMUXC_MUX_OUT_ALT3 (0x4 << IOMUXC_MUX_OUT_POS)
#define IOMUXC_MUX_OUT_ALT4 (0x5 << IOMUXC_MUX_OUT_POS)
#define IOMUXC_MUX_OUT_ALT5 (0x6 << IOMUXC_MUX_OUT_POS)
#define IOMUXC_MUX_OUT_ALT6 (0x7 << IOMUXC_MUX_OUT_POS)
#define SW_MUX_OUT (0x7 << 4)
#define SW_MUX_OUT_GPIO_DR (0x0 << 4)
#define SW_MUX_OUT_FUNCTIONAL (0x1 << 4)
#define SW_MUX_OUT_ALT1 (0x2 << 4)
#define SW_MUX_OUT_ALT2 (0x3 << 4)
#define SW_MUX_OUT_ALT3 (0x4 << 4)
#define SW_MUX_OUT_ALT4 (0x5 << 4)
#define SW_MUX_OUT_ALT5 (0x6 << 4)
#define SW_MUX_OUT_ALT6 (0x7 << 4)
#define IOMUXC_MUX_IN_NONE (0x0 << IOMUXC_MUX_IN_POS)
#define IOMUXC_MUX_IN_GPIO (0x1 << IOMUXC_MUX_IN_POS)
#define IOMUXC_MUX_IN_FUNCTIONAL (0x2 << IOMUXC_MUX_IN_POS)
#define IOMUXC_MUX_IN_ALT1 (0x4 << IOMUXC_MUX_IN_POS)
#define IOMUXC_MUX_IN_ALT2 (0x8 << IOMUXC_MUX_IN_POS)
#define SW_MUX_IN (0xf << 0)
#define SW_MUX_IN_NO_INPUTS (0x0 << 0)
#define SW_MUX_IN_GPIO_PSR_ISR (0x1 << 0)
#define SW_MUX_IN_FUNCTIONAL (0x2 << 0)
#define SW_MUX_IN_ALT1 (0x4 << 0)
#define SW_MUX_IN_ALT2 (0x8 << 0)
/* Masks for each signal field */
#define SW_MUX_CTL_SIG1 (0x7f << 0)
#define SW_MUX_CTL_SIG2 (0x7f << 8)
#define SW_MUX_CTL_SIG3 (0x7f << 16)
#define SW_MUX_CTL_SIG4 (0x7f << 24)
/* Shift above flags into one of the four fields in each register */
#define SW_MUX_CTL_SIG1_POS (0)
#define SW_MUX_CTL_SIG2_POS (8)
#define SW_MUX_CTL_SIG3_POS (16)
#define SW_MUX_CTL_SIG4_POS (24)
/* SW_PAD_CTL */
#define SW_PAD_CTL_TTM_PAD__X__X IOMUXC_(0x154)
#define SW_PAD_CTL_CSPI3_MISO_CSPI3_SCLK_CSPI3_SPI_RDY IOMUXC_(0x158)
#define SW_PAD_CTL_CE_CONTROL_CLKSS_CSPI3_MOSI IOMUXC_(0x15C)
#define SW_PAD_CTL_ATA_DIOW_ATA_DMACK_ATA_RESET_B IOMUXC_(0x160)
#define SW_PAD_CTL_ATA_CS0_ATA_CS1_ATA_DIOR IOMUXC_(0x164)
#define SW_PAD_CTL_SD1_DATA1_SD1_DATA2_SD1_DATA3 IOMUXC_(0x168)
#define SW_PAD_CTL_SD1_CMD_SD1_CLK_SD1_DATA0 IOMUXC_(0x16C)
#define SW_PAD_CTL_D3_REV_D3_CLS_D3_SPL IOMUXC_(0x170)
#define SW_PAD_CTL_READ_VSYNC3_CONTRAST IOMUXC_(0x174)
#define SW_PAD_CTL_SER_RS_PAR_RS_WRITE IOMUXC_(0x178)
#define SW_PAD_CTL_SD_D_CLK_LCS0_LCS1 IOMUXC_(0x17C)
#define SW_PAD_CTL_DRDY0_SD_D_I_SD_D_IO IOMUXC_(0x180)
#define SW_PAD_CTL_VSYNC0_HSYNC_FPSHIFT IOMUXC_(0x184)
#define SW_PAD_CTL_LD15_LD16_LD17 IOMUXC_(0x188)
#define SW_PAD_CTL_LD12_LD13_LD14 IOMUXC_(0x18C)
#define SW_PAD_CTL_LD9_LD10_LD11 IOMUXC_(0x190)
#define SW_PAD_CTL_LD6_LD7_LD8 IOMUXC_(0x194)
#define SW_PAD_CTL_LD3_LD4_LD5 IOMUXC_(0x198)
#define SW_PAD_CTL_LD0_LD1_LD2 IOMUXC_(0x19C)
#define SW_PAD_CTL_USBH2_NXT_USBH2_DATA0_USBH2_DATA1 IOMUXC_(0x1A0)
#define SW_PAD_CTL_USBH2_CLK_USBH2_DIR_USBH2_STP IOMUXC_(0x1A4)
#define SW_PAD_CTL_USBOTG_DATA5_USBOTG_DATA6_USBOTG_DATA7 IOMUXC_(0x1A8)
#define SW_PAD_CTL_USBOTG_DATA2_USBOTG_DATA3_USBOTG_DATA4 IOMUXC_(0x1AC)
#define SW_PAD_CTL_USBOTG_NXT_USBOTG_DATA0_USBOTG_DATA1 IOMUXC_(0x1B0)
#define SW_PAD_CTL_USBOTG_CLK_USBOTG_DIR_USBOTG_STP IOMUXC_(0x1B4)
#define SW_PAD_CTL_USB_PWR_USB_OC_USB_BYP IOMUXC_(0x1B8)
#define SW_PAD_CTL_TRSTB_DE_B_SJC_MOD IOMUXC_(0x1BC)
#define SW_PAD_CTL_TMS_TDI_TDO IOMUXC_(0x1C0)
#define SW_PAD_CTL_KEY_COL7_RTCK_TCK IOMUXC_(0x1C4)
#define SW_PAD_CTL_KEY_COL4_KEY_COL5_KEY_COL6 IOMUXC_(0x1C8)
#define SW_PAD_CTL_KEY_COL1_KEY_COL2_KEY_COL3 IOMUXC_(0x1CC)
#define SW_PAD_CTL_KEY_ROW6_KEY_ROW7_KEY_COL0 IOMUXC_(0x1D0)
#define SW_PAD_CTL_KEY_ROW3_KEY_ROW4_KEY_ROW5 IOMUXC_(0x1D4)
#define SW_PAD_CTL_KEY_ROW0_KEY_ROW1_KEY_ROW2 IOMUXC_(0x1D8)
#define SW_PAD_CTL_RTS2_CTS2_BATT_LINE IOMUXC_(0x1DC)
#define SW_PAD_CTL_DTR_DCE2_RXD2_TXD2 IOMUXC_(0x1E0)
#define SW_PAD_CTL_DSR_DTE1_RI_DTE1_DCD_DTE1 IOMUXC_(0x1E4)
#define SW_PAD_CTL_RI_DCE1_DCD_DCE1_DTR_DTE1 IOMUXC_(0x1E8)
#define SW_PAD_CTL_CTS1_DTR_DCE1_DSR_DCE1 IOMUXC_(0x1EC)
#define SW_PAD_CTL_RXD1_TXD1_RTS1 IOMUXC_(0x1F0)
#define SW_PAD_CTL_CSPI2_SS2_CSPI2_SCLK_CSPI2_SPI_RDY IOMUXC_(0x1F4)
#define SW_PAD_CTL_CSPI2_MISO_CSPI2_SS0_CSPI2_SS1 IOMUXC_(0x1F8)
#define SW_PAD_CTL_CSPI1_SCLK_CSPI1_SPI_RDY_CSPI2_MOSI IOMUXC_(0x1FC)
#define SW_PAD_CTL_CSPI1_SS0_CSPI1_SS1_CSPI1_SS IOMUXC_(0x200)
#define SW_PAD_CTL_SFS6_CSPI1_MOSI_CSPI1_MISO IOMUXC_(0x204)
#define SW_PAD_CTL_STXD6_SRXD6_SCK6 IOMUXC_(0x208)
#define SW_PAD_CTL_SRXD5_SCK5_SFS5 IOMUXC_(0x20C)
#define SW_PAD_CTL_SCK4_SFS4_STXD5 IOMUXC_(0x210)
#define SW_PAD_CTL_SFS3_STXD4_SRXD4 IOMUXC_(0x214)
#define SW_PAD_CTL_STXD3_SRXD3_SCK3 IOMUXC_(0x218)
#define SW_PAD_CTL_CSI_PIXCLK_I2C_CLK_I2C_DAT IOMUXC_(0x21C)
#define SW_PAD_CTL_CSI_MCLK_CSI_VSYNC_CSI_HSYNC IOMUXC_(0x220)
#define SW_PAD_CTL_CSI_D13_CSI_D14_CSI_D15 IOMUXC_(0x224)
#define SW_PAD_CTL_CSI_D10_CSI_D11_CSI_D12 IOMUXC_(0x228)
#define SW_PAD_CTL_CSI_D7_CSI_D8_CSI_D9 IOMUXC_(0x22C)
#define SW_PAD_CTL_CSI_D4_CSI_D5_CSI_D6 IOMUXC_(0x230)
#define SW_PAD_CTL_PC_POE_M_REQUEST_M_GRANT IOMUXC_(0x234)
#define SW_PAD_CTL_PC_RST_IOIS16_PC_RW_B IOMUXC_(0x238)
#define SW_PAD_CTL_PC_VS2_PC_BVD1_PC_BVD2 IOMUXC_(0x23C)
#define SW_PAD_CTL_PC_READY_PC_PWRON_PC_VS1 IOMUXC_(0x240)
#define SW_PAD_CTL_PC_CD1_B_PC_CD2_B_PC_WAIT_B IOMUXC_(0x244)
#define SW_PAD_CTL_D2_D1_D0 IOMUXC_(0x248)
#define SW_PAD_CTL_D5_D4_D3 IOMUXC_(0x24C)
#define SW_PAD_CTL_D8_D7_D6 IOMUXC_(0x250)
#define SW_PAD_CTL_D11_D10_D9 IOMUXC_(0x254)
#define SW_PAD_CTL_D14_D13_D12 IOMUXC_(0x258)
#define SW_PAD_CTL_NFCE_B_NFRB_D15 IOMUXC_(0x25C)
#define SW_PAD_CTL_NFALE_NFCLE_NFWP_B IOMUXC_(0x260)
#define SW_PAD_CTL_SDQS3_NFWE_B_NFRE_B IOMUXC_(0x264)
#define SW_PAD_CTL_SDQS0_SDQS1_SDQS2 IOMUXC_(0x268)
#define SW_PAD_CTL_SDCKE1_SDCLK_SDCLK_B IOMUXC_(0x26C)
#define SW_PAD_CTL_CAS_SDWE_SDCKE0 IOMUXC_(0x270)
#define SW_PAD_CTL_BCLK_RW_RAS IOMUXC_(0x274)
#define SW_PAD_CTL_CS5_ECB_LBA IOMUXC_(0x278)
#define SW_PAD_CTL_CS2_CS3_CS4 IOMUXC_(0x27C)
#define SW_PAD_CTL_OE_CS0_CS1 IOMUXC_(0x280)
#define SW_PAD_CTL_DQM3_EB0_EB1 IOMUXC_(0x284)
#define SW_PAD_CTL_DQM0_DQM1_DQM2 IOMUXC_(0x288)
#define SW_PAD_CTL_SD29_SD30_SD31 IOMUXC_(0x28C)
#define SW_PAD_CTL_SD26_SD27_SD28 IOMUXC_(0x290)
#define SW_PAD_CTL_SD23_SD24_SD25 IOMUXC_(0x294)
#define SW_PAD_CTL_SD20_SD21_SD22 IOMUXC_(0x298)
#define SW_PAD_CTL_SD17_SD18_SD19 IOMUXC_(0x29C)
#define SW_PAD_CTL_SD14_SD15_SD16 IOMUXC_(0x2A0)
#define SW_PAD_CTL_SD11_SD12_SD13 IOMUXC_(0x2A4)
#define SW_PAD_CTL_SD8_SD9_SD10 IOMUXC_(0x2A8)
#define SW_PAD_CTL_SD5_SD6_SD7 IOMUXC_(0x2AC)
#define SW_PAD_CTL_SD2_SD3_SD4 IOMUXC_(0x2B0)
#define SW_PAD_CTL_SDBA0_SD0_SD1 IOMUXC_(0x2B4)
#define SW_PAD_CTL_A24_A25_SDBA1 IOMUXC_(0x2B8)
#define SW_PAD_CTL_A21_A22_A23 IOMUXC_(0x2BC)
#define SW_PAD_CTL_A18_A19_A20 IOMUXC_(0x2C0)
#define SW_PAD_CTL_A15_A16_A17 IOMUXC_(0x2C4)
#define SW_PAD_CTL_A12_A13_A14 IOMUXC_(0x2C8)
#define SW_PAD_CTL_A10_MA10_A11 IOMUXC_(0x2CC)
#define SW_PAD_CTL_A7_A8_A9 IOMUXC_(0x2D0)
#define SW_PAD_CTL_A4_A5_A6 IOMUXC_(0x2D4)
#define SW_PAD_CTL_A1_A2_A3 IOMUXC_(0x2D8)
#define SW_PAD_CTL_VPG0_VPG1_A0 IOMUXC_(0x2DC)
#define SW_PAD_CTL_VSTBY_DVFS0_DVFS1 IOMUXC_(0x2E0)
#define SW_PAD_CTL_BOOT_MODE4_CKIL_POWER_FAIL IOMUXC_(0x2E4)
#define SW_PAD_CTL_BOOT_MODE1_BOOT_MODE2_BOOT_MODE3 IOMUXC_(0x2E8)
#define SW_PAD_CTL_POR_B_CLKO_BOOT_MODE0 IOMUXC_(0x2EC)
#define SW_PAD_CTL_SIMPD0_CKIH_RESET_IN_B IOMUXC_(0x2F0)
#define SW_PAD_CTL_SVEN0_STX0_SRX0 IOMUXC_(0x2F4)
#define SW_PAD_CTL_GPIO3_1_SCLK0_SRST0 IOMUXC_(0x2F8)
#define SW_PAD_CTL_GPIO1_5_GPIO1_6_GPIO3_0 IOMUXC_(0x2FC)
#define SW_PAD_CTL_GPIO1_2_GPIO1_3_GPIO1_4 IOMUXC_(0x300)
#define SW_PAD_CTL_PWMO_GPIO1_0_GPIO1_1 IOMUXC_(0x304)
#define SW_PAD_CTL_CAPTURE_COMPARE_WATCHDOG_RST IOMUXC_(0x308)
/* SW_PAD_CTL flags */
#define SW_PAD_CTL_LOOPBACK (0x1 << 9) /* Route output to input */
/* SW_PAD_CTL_* */
#define IOMUXC_PAD_LOOPBACK (0x1 << 9) /* Route output to input */
/* Pullup, pulldown and keeper enable */
#define SW_PAD_CTL_PUE_PKE (0x3 << 7)
#define SW_PAD_CTL_PUE_PKE_DISABLE (0x0 << 7)
#define SW_PAD_CTL_PUE_PKE_DISABLE_2 (0x1 << 7) /* Same as 0x0 */
#define SW_PAD_CTL_PUE_PKE_KEEPER (0x2 << 7)
#define SW_PAD_CTL_PUE_PKE_PULLUPDOWN (0x3 << 7) /* Enb. Pull up or down */
#define IOMUXC_PAD_PUE_PKE (0x3 << 7)
#define IOMUXC_PAD_PUE_PKE_DISABLE (0x0 << 7)
#define IOMUXC_PAD_PUE_PKE_DISABLE_2 (0x1 << 7) /* Same as 0x0 */
#define IOMUXC_PAD_PUE_PKE_KEEPER (0x2 << 7)
#define IOMUXC_PAD_PUE_PKE_PULLUPDOWN (0x3 << 7) /* Enb. Pull up or down */
/* Pullup/down resistance */
#define SW_PAD_CTL_PUS (0x3 << 5)
#define SW_PAD_CTL_PUS_DOWN_100K (0x0 << 5)
#define SW_PAD_CTL_PUS_UP_100K (0x1 << 5)
#define IOMUXC_PAD_PUS (0x3 << 5)
#define IOMUXC_PAD_PUS_DOWN_100K (0x0 << 5)
#define IOMUXC_PAD_PUS_UP_100K (0x1 << 5)
#if 0 /* Completeness */
#define SW_PAD_CTL_PUS_UP_47K (0x2 << 5) /* Not in IMX31/L */
#define SW_PAD_CTL_PUS_UP_22K (0x3 << 5) /* Not in IMX31/L */
#define IOMUXC_PAD_PUS_UP_47K (0x2 << 5) /* Not in IMX31/L */
#define IOMUXC_PAD_PUS_UP_22K (0x3 << 5) /* Not in IMX31/L */
#endif
#define SW_PAD_CTL_HYS (0x1 << 4) /* Schmitt trigger input */
#define SW_PAD_CTL_ODE (0x1 << 3) /* Open drain output 0=CMOS pushpull*/
#define SW_PAD_CTL_DSE (0x3 << 1)
#define SW_PAD_CTL_DSE_STD (0x0 << 1) /* Drive strength */
#define SW_PAD_CTL_DSE_HIGH (0x1 << 1)
#define SW_PAD_CTL_DSE_MAX (0x2 << 1)
#define SW_PAD_CTL_DSE_MAX_2 (0x3 << 1) /* Same as 0x2 */
#define SW_PAD_CTL_SRE (0x1 << 0) /* Slew rate, 1=fast */
#define IOMUXC_PAD_HYS (0x1 << 4) /* Schmitt trigger input */
#define IOMUXC_PAD_ODE (0x1 << 3) /* Open drain output 0=CMOS pushpull*/
#define IOMUXC_PAD_DSE (0x3 << 1)
#define IOMUXC_PAD_DSE_STD (0x0 << 1) /* Drive strength */
#define IOMUXC_PAD_DSE_HIGH (0x1 << 1)
#define IOMUXC_PAD_DSE_MAX (0x2 << 1)
#define IOMUXC_PAD_DSE_MAX_2 (0x3 << 1) /* Same as 0x2 */
#define IOMUXC_PAD_SRE (0x1 << 0) /* Slew rate, 1=fast */
/* Masks for each IO field */
#define SW_PAD_CTL_IO1 (0x3ff << 0)
#define SW_PAD_CTL_IO2 (0x3ff << 10)
#define SW_PAD_CTL_IO3 (0x3ff << 20)
/* Shift above flags into one of the three fields in each register */
#define SW_PAD_CTL_IO1_POS (0)
#define SW_PAD_CTL_IO2_POS (10)
#define SW_PAD_CTL_IO3_POS (20)
#define IOMUXC_PAD_MASK (0x3ff)
/* RNGA */
#define RNGA_CONTROL (*(REG32_PTR_T)(RNGA_BASE_ADDR+0x00))

43
firmware/target/arm/imx31/gigabeat-s/fmradio-i2c-gigabeat-s.c
View file

@ -22,6 +22,7 @@
#include "config.h"
#include "system.h"
#include "mc13783.h"
#include "iomuxc-imx31.h"
#include "i2c-imx31.h"
#include "fmradio_i2c.h"
@ -48,36 +49,34 @@ void fmradio_i2c_init(void)
/* open-drain pins - external pullups on PCB. Pullup default but
* disabled */
imx31_regmod32(&SW_PAD_CTL_DSR_DTE1_RI_DTE1_DCD_DTE1,
/* RI_DTE1 (I2C2_SCLK) */
((SW_PAD_CTL_PUE_PKE_DISABLE | SW_PAD_CTL_PUS_UP_100K |
SW_PAD_CTL_HYS | SW_PAD_CTL_ODE) << SW_PAD_CTL_IO2_POS) |
/* DCD_DTE1 (I2C2_SDA) */
((SW_PAD_CTL_PUE_PKE_DISABLE | SW_PAD_CTL_PUS_UP_100K |
SW_PAD_CTL_HYS | SW_PAD_CTL_ODE) << SW_PAD_CTL_IO1_POS),
SW_PAD_CTL_IO2 | SW_PAD_CTL_IO1);
/* RI_DTE1 (I2C2_SCLK) */
iomuxc_set_pad_config(IOMUXC_RI_DTE1,
IOMUXC_PAD_PUE_PKE_DISABLE | IOMUXC_PAD_PUS_UP_100K |
IOMUXC_PAD_HYS | IOMUXC_PAD_ODE);
/* DCD_DTE1 (I2C2_SDA) */
iomuxc_set_pad_config(IOMUXC_DCD_DTE1,
IOMUXC_PAD_PUE_PKE_DISABLE | IOMUXC_PAD_PUS_UP_100K |
IOMUXC_PAD_HYS | IOMUXC_PAD_ODE);
/* set outputs to I2C2 */
imx31_regmod32(&SW_MUX_CTL_RI_DTE1_DCD_DTE1_DTR_DCE2_RXD2,
/* RI_DTE1 => I2C2_SCLK */
((SW_MUX_OUT_ALT2 | SW_MUX_IN_ALT2) << SW_MUX_CTL_SIG4_POS) |
/* DCD_DTE1 => I2C2_SDA */
((SW_MUX_OUT_ALT2 | SW_MUX_IN_ALT2) << SW_MUX_CTL_SIG3_POS),
SW_MUX_CTL_SIG4 | SW_MUX_CTL_SIG3);
/* RI_DTE1 => I2C2_SCLK */
iomuxc_set_pin_mux(IOMUXC_RI_DTE1,
IOMUXC_MUX_OUT_ALT2 | IOMUXC_MUX_IN_ALT2);
/* DCD_DTE1 => I2C2_SDA */
iomuxc_set_pin_mux(IOMUXC_DCD_DTE1,
IOMUXC_MUX_OUT_ALT2 | IOMUXC_MUX_IN_ALT2);
}
void fmradio_i2c_enable(bool enable)
{
if (enable)
{
uint32_t io_pin_mux = SW_MUX_CTL_RI_DTE1_DCD_DTE1_DTR_DCE2_RXD2;
/* place in GPIO mode to hold SDIO low during RESET release,
* SEN1 should be high already (pullup) and GPIO3 left alone */
imx31_regset32(&GPIO2_GDIR, (1 << 15)); /* SDIO OUT */
/* I2C2_SDA => MCU2_15 */
imx31_regmod32(&SW_MUX_CTL_RI_DTE1_DCD_DTE1_DTR_DCE2_RXD2,
(SW_MUX_OUT_GPIO_DR |
SW_MUX_IN_GPIO_PSR_ISR) << SW_MUX_CTL_SIG3_POS,
SW_MUX_CTL_SIG3);
iomuxc_set_pin_mux(IOMUXC_DCD_DTE1,
IOMUXC_MUX_OUT_GPIO | IOMUXC_MUX_IN_GPIO);
/* enable CLK32KMCU clock */
mc13783_set(MC13783_POWER_CONTROL0, MC13783_CLK32KMCUEN);
/* enable the fm chip (release RESET) */
@ -85,9 +84,9 @@ void fmradio_i2c_enable(bool enable)
sleep(HZ/100);
/* busmode should be selected - OK to release SDIO */
imx31_regclr32(&GPIO2_GDIR, (1 << 15)); /* SDIO IN */
/* restore pin mux (DCD_DTE1 => I2C2_SDA) */
imx31_regmod32(&SW_MUX_CTL_RI_DTE1_DCD_DTE1_DTR_DCE2_RXD2,
io_pin_mux, SW_MUX_CTL_SIG3);
/* restore pin mux (MCU2_15 => I2C2_SDA) */
iomuxc_set_pin_mux(IOMUXC_DCD_DTE1,
IOMUXC_MUX_OUT_ALT2 | IOMUXC_MUX_IN_ALT2);
/* the si4700 is the only thing connected to i2c2 so
we can diable the i2c module when not in use */
i2c_enable_node(&si4700_i2c_node, true);

50
firmware/target/arm/imx31/iomuxc-imx31.c Normal file
View file

@ -0,0 +1,50 @@
/***************************************************************************
* __________ __ ___.
* Open \______ \ ____ ____ | | _\_ |__ _______ ___
* Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
* \/ \/ \/ \/ \/
* $Id$
*
* Copyright (c) 2010 Michael Sevakis
*
* i.MX31 IOMUXC helper routines
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; either version 2
* of the License, or (at your option) any later version.
*
* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
* KIND, either express or implied.
*
****************************************************************************/
#include "config.h"
#include "system.h"
#include "iomuxc-imx31.h"
/* Set the pin multiplexing configuration (functional, GPIO, etc.) */
void iomuxc_set_pin_mux(enum IMX31_IOMUXC_PINS pin,
unsigned long mux)
{
unsigned long index = pin / 4;
unsigned int shift = 8*(pin % 4);
imx31_regmod32((unsigned long *)(IOMUXC_BASE_ADDR + 0xc) + index,
mux << shift, IOMUXC_MUX_MASK << shift);
}
/* Set the pin pad configuration (keeper, drive strength, etc.) */
void iomuxc_set_pad_config(enum IMX31_IOMUXC_PINS pin,
unsigned long config)
{
unsigned long padoffs = pin + 2;
unsigned long index = padoffs / 3;
unsigned int shift = 10*(padoffs % 3);
imx31_regmod32((unsigned long *)(IOMUXC_BASE_ADDR + 0x154) + index,
config << shift, IOMUXC_PAD_MASK << shift);
}

364
firmware/target/arm/imx31/iomuxc-imx31.h Normal file
View file

@ -0,0 +1,364 @@
/***************************************************************************
* __________ __ ___.
* Open \______ \ ____ ____ | | _\_ |__ _______ ___
* Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
* \/ \/ \/ \/ \/
* $Id$
*
* Copyright (c) 2010 Michael Sevakis
*
* i.MX31 IOMUXC helper routines
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; either version 2
* of the License, or (at your option) any later version.
*
* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
* KIND, either express or implied.
*
****************************************************************************/
#ifndef _IOMUXC_IMX31_H_
#define _IOMUXC_IMX31_H_
enum IMX31_IOMUXC_PINS
{
IOMUXC_TTM_PAD = 0,
IOMUXC_CSPI3_SPI_RDY = 1,
IOMUXC_CSPI3_SCLK = 2,
IOMUXC_CSPI3_MISO = 3,
IOMUXC_CSPI3_MOSI = 4,
IOMUXC_CLKSS = 5,
IOMUXC_CE_CONTROL = 6,
IOMUXC_ATA_RST_B = 7,
IOMUXC_ATA_DMACK = 8,
IOMUXC_ATA_DIOW = 9,
IOMUXC_ATA_DIOR = 10,
IOMUXC_ATA_CS1 = 11,
IOMUXC_ATA_CS0 = 12,
IOMUXC_SD1_DATA3 = 13,
IOMUXC_SD1_DATA2 = 14,
IOMUXC_SD1_DATA1 = 15,
IOMUXC_SD1_DATA0 = 16,
IOMUXC_SD1_CLK = 17,
IOMUXC_SD1_CMD = 18,
IOMUXC_D3_SPL = 19,
IOMUXC_D3_CLS = 20,
IOMUXC_D3_REV = 21,
IOMUXC_CONTRAST = 22,
IOMUXC_VSYNC3 = 23,
IOMUXC_READ = 24,
IOMUXC_WRITE = 25,
IOMUXC_PAR_RS = 26,
IOMUXC_SER_RS = 27,
IOMUXC_LCS1 = 28,
IOMUXC_LCS0 = 29,
IOMUXC_SD_D_CLK = 30,
IOMUXC_SD_D_IO = 31,
IOMUXC_SD_D_I = 32,
IOMUXC_DRDY0 = 33,
IOMUXC_FPSHIFT = 34,
IOMUXC_HSYNC = 35,
IOMUXC_VSYNC0 = 36,
IOMUXC_LD17 = 37,
IOMUXC_LD16 = 38,
IOMUXC_LD15 = 39,
IOMUXC_LD14 = 40,
IOMUXC_LD13 = 41,
IOMUXC_LD12 = 42,
IOMUXC_LD11 = 43,
IOMUXC_LD10 = 44,
IOMUXC_LD9 = 45,
IOMUXC_LD8 = 46,
IOMUXC_LD7 = 47,
IOMUXC_LD6 = 48,
IOMUXC_LD5 = 49,
IOMUXC_LD4 = 50,
IOMUXC_LD3 = 51,
IOMUXC_LD2 = 52,
IOMUXC_LD1 = 53,
IOMUXC_LD0 = 54,
IOMUXC_USBH2_DATA1 = 55,
IOMUXC_USBH2_DATA0 = 56,
IOMUXC_USBH2_NXT = 57,
IOMUXC_USBH2_STP = 58,
IOMUXC_USBH2_DIR = 59,
IOMUXC_USBH2_CLK = 60,
IOMUXC_USBOTG_DATA7 = 61,
IOMUXC_USBOTG_DATA6 = 62,
IOMUXC_USBOTG_DATA5 = 63,
IOMUXC_USBOTG_DATA4 = 64,
IOMUXC_USBOTG_DATA3 = 65,
IOMUXC_USBOTG_DATA2 = 66,
IOMUXC_USBOTG_DATA1 = 67,
IOMUXC_USBOTG_DATA0 = 68,
IOMUXC_USBOTG_NXT = 69,
IOMUXC_USBOTG_STP = 70,
IOMUXC_USBOTG_DIR = 71,
IOMUXC_USBOTG_CLK = 72,
IOMUXC_USB_BYP = 73,
IOMUXC_USB_OC = 74,
IOMUXC_USB_PWR = 75,
IOMUXC_SJC_MOD = 76,
IOMUXC_DE_B = 77,
IOMUXC_TRSTB = 78,
IOMUXC_TDO = 79,
IOMUXC_TDI = 80,
IOMUXC_TMS = 81,
IOMUXC_TCK = 82,
IOMUXC_RTCK = 83,
IOMUXC_KEY_COL7 = 84,
IOMUXC_KEY_COL6 = 85,
IOMUXC_KEY_COL5 = 86,
IOMUXC_KEY_COL4 = 87,
IOMUXC_KEY_COL3 = 88,
IOMUXC_KEY_COL2 = 89,
IOMUXC_KEY_COL1 = 90,
IOMUXC_KEY_COL0 = 91,
IOMUXC_KEY_ROW7 = 92,
IOMUXC_KEY_ROW6 = 93,
IOMUXC_KEY_ROW5 = 94,
IOMUXC_KEY_ROW4 = 95,
IOMUXC_KEY_ROW3 = 96,
IOMUXC_KEY_ROW2 = 97,
IOMUXC_KEY_ROW1 = 98,
IOMUXC_KEY_ROW0 = 99,
IOMUXC_BATT_LINE = 100,
IOMUXC_CTS2 = 101,
IOMUXC_RTS2 = 102,
IOMUXC_TXD2 = 103,
IOMUXC_RXD2 = 104,
IOMUXC_DTR_DCE2 = 105,
IOMUXC_DCD_DTE1 = 106,
IOMUXC_RI_DTE1 = 107,
IOMUXC_DSR_DTE1 = 108,
IOMUXC_DTR_DTE1 = 109,
IOMUXC_DCD_DCE1 = 110,
IOMUXC_RI_DCE1 = 111,
IOMUXC_DSR_DCE1 = 112,
IOMUXC_DTR_DCE1 = 113,
IOMUXC_CTS1 = 114,
IOMUXC_RTS1 = 115,
IOMUXC_TXD1 = 116,
IOMUXC_RXD1 = 117,
IOMUXC_CSPI2_SPI_RDY = 118,
IOMUXC_CSPI2_SCLK = 119,
IOMUXC_CSPI2_SS2 = 120,
IOMUXC_CSPI2_SS1 = 121,
IOMUXC_CSPI2_SS0 = 122,
IOMUXC_CSPI2_MISO = 123,
IOMUXC_CSPI2_MOSI = 124,
IOMUXC_CSPI1_SPI_RDY = 125,
IOMUXC_CSPI1_SCLK = 126,
IOMUXC_CSPI1_SS2 = 127,
IOMUXC_CSPI1_SS1 = 128,
IOMUXC_CSPI1_SS0 = 129,
IOMUXC_CSPI1_MISO = 130,
IOMUXC_CSPI1_MOSI = 131,
IOMUXC_SFS6 = 132,
IOMUXC_SCK6 = 133,
IOMUXC_SRXD6 = 134,
IOMUXC_STXD6 = 135,
IOMUXC_SFS5 = 136,
IOMUXC_SCK5 = 137,
IOMUXC_SRXD5 = 138,
IOMUXC_STXD5 = 139,
IOMUXC_SFS4 = 140,
IOMUXC_SCK4 = 141,
IOMUXC_SRXD4 = 142,
IOMUXC_STXD4 = 143,
IOMUXC_SFS3 = 144,
IOMUXC_SCK3 = 145,
IOMUXC_SRXD3 = 146,
IOMUXC_STXD3 = 147,
IOMUXC_I2C_DAT = 148,
IOMUXC_I2C_CLK = 149,
IOMUXC_CSI_PIXCLK = 150,
IOMUXC_CSI_HSYNC = 151,
IOMUXC_CSI_VSYNC = 152,
IOMUXC_CSI_MCLK = 153,
IOMUXC_CSI_D15 = 154,
IOMUXC_CSI_D14 = 155,
IOMUXC_CSI_D13 = 156,
IOMUXC_CSI_D12 = 157,
IOMUXC_CSI_D11 = 158,
IOMUXC_CSI_D10 = 159,
IOMUXC_CSI_D9 = 160,
IOMUXC_CSI_D8 = 161,
IOMUXC_CSI_D7 = 162,
IOMUXC_CSI_D6 = 163,
IOMUXC_CSI_D5 = 164,
IOMUXC_CSI_D4 = 165,
IOMUXC_M_GRANT = 166,
IOMUXC_M_REQUEST = 167,
IOMUXC_PC_POE = 168,
IOMUXC_PC_RW_B = 169,
IOMUXC_IOIS16 = 170,
IOMUXC_PC_RST = 171,
IOMUXC_PC_BVD2 = 172,
IOMUXC_PC_BVD1 = 173,
IOMUXC_PC_VS2 = 174,
IOMUXC_PC_VS1 = 175,
IOMUXC_PC_PWRON = 176,
IOMUXC_PC_READY = 177,
IOMUXC_PC_WAIT_B = 178,
IOMUXC_PC_CD2_B = 179,
IOMUXC_PC_CD1_B = 180,
IOMUXC_D0 = 181,
IOMUXC_D1 = 182,
IOMUXC_D2 = 183,
IOMUXC_D3 = 184,
IOMUXC_D4 = 185,
IOMUXC_D5 = 186,
IOMUXC_D6 = 187,
IOMUXC_D7 = 188,
IOMUXC_D8 = 189,
IOMUXC_D9 = 190,
IOMUXC_D10 = 191,
IOMUXC_D11 = 192,
IOMUXC_D12 = 193,
IOMUXC_D13 = 194,
IOMUXC_D14 = 195,
IOMUXC_D15 = 196,
IOMUXC_NFRB = 197,
IOMUXC_NFCE_B = 198,
IOMUXC_NFWP_B = 199,
IOMUXC_NFCLE = 200,
IOMUXC_NFALE = 201,
IOMUXC_NFRE_B = 202,
IOMUXC_NFWE_B = 203,
IOMUXC_SDQS3 = 204,
IOMUXC_SDQS2 = 205,
IOMUXC_SDQS1 = 206,
IOMUXC_SDQS0 = 207,
IOMUXC_RESERVED0 = 208,
IOMUXC_SDCLK = 209,
IOMUXC_SDCKE1 = 210,
IOMUXC_SDCKE0 = 211,
IOMUXC_SDWE = 212,
IOMUXC_CAS = 213,
IOMUXC_RAS = 214,
IOMUXC_RW = 215,
IOMUXC_BCLK = 216,
IOMUXC_LBA = 217,
IOMUXC_ECB = 218,
IOMUXC_CS5 = 219,
IOMUXC_CS4 = 220,
IOMUXC_CS3 = 221,
IOMUXC_CS2 = 222,
IOMUXC_CS1 = 223,
IOMUXC_CS0 = 224,
IOMUXC_OE = 225,
IOMUXC_EB1 = 226,
IOMUXC_EB0 = 227,
IOMUXC_DQM3 = 228,
IOMUXC_DQM2 = 229,
IOMUXC_DQM1 = 230,
IOMUXC_DQM0 = 231,
IOMUXC_SD31 = 232,
IOMUXC_SD30 = 233,
IOMUXC_SD29 = 234,
IOMUXC_SD28 = 235,
IOMUXC_SD27 = 236,
IOMUXC_SD26 = 237,
IOMUXC_SD25 = 238,
IOMUXC_SD24 = 239,
IOMUXC_SD23 = 240,
IOMUXC_SD22 = 241,
IOMUXC_SD21 = 242,
IOMUXC_SD20 = 243,
IOMUXC_SD19 = 244,
IOMUXC_SD18 = 245,
IOMUXC_SD17 = 246,
IOMUXC_SD16 = 247,
IOMUXC_SD15 = 248,
IOMUXC_SD14 = 249,
IOMUXC_SD13 = 250,
IOMUXC_SD12 = 251,
IOMUXC_SD11 = 252,
IOMUXC_SD10 = 253,
IOMUXC_SD9 = 254,
IOMUXC_SD8 = 255,
IOMUXC_SD7 = 256,
IOMUXC_SD6 = 257,
IOMUXC_SD5 = 258,
IOMUXC_SD4 = 259,
IOMUXC_SD3 = 260,
IOMUXC_SD2 = 261,
IOMUXC_SD1 = 262,
IOMUXC_SD0 = 263,
IOMUXC_SDBA0 = 264,
IOMUXC_SDBA1 = 265,
IOMUXC_A25 = 266,
IOMUXC_A24 = 267,
IOMUXC_A23 = 268,
IOMUXC_A22 = 269,
IOMUXC_A21 = 270,
IOMUXC_A20 = 271,
IOMUXC_A19 = 272,
IOMUXC_A18 = 273,
IOMUXC_A17 = 274,
IOMUXC_A16 = 275,
IOMUXC_A15 = 276,
IOMUXC_A14 = 277,
IOMUXC_A13 = 278,
IOMUXC_A12 = 279,
IOMUXC_A11 = 280,
IOMUXC_MA10 = 281,
IOMUXC_A10 = 282,
IOMUXC_A9 = 283,
IOMUXC_A8 = 284,
IOMUXC_A7 = 285,
IOMUXC_A6 = 286,
IOMUXC_A5 = 287,
IOMUXC_A4 = 288,
IOMUXC_A3 = 289,
IOMUXC_A2 = 290,
IOMUXC_A1 = 291,
IOMUXC_A0 = 292,
IOMUXC_VPG1 = 293,
IOMUXC_VPG0 = 294,
IOMUXC_DVFS1 = 295,
IOMUXC_DVFS0 = 296,
IOMUXC_VSTBY = 297,
IOMUXC_POWER_FAIL = 298,
IOMUXC_CKIL = 299,
IOMUXC_BOOT_MODE4 = 300,
IOMUXC_BOOT_MODE3 = 301,
IOMUXC_BOOT_MODE2 = 302,
IOMUXC_BOOT_MODE1 = 303,
IOMUXC_BOOT_MODE0 = 304,
IOMUXC_CLKO = 305,
IOMUXC_POR_B = 306,
IOMUXC_RESET_IN_B = 307,
IOMUXC_CKIH = 308,
IOMUXC_SIMPD0 = 309,
IOMUXC_SRX0 = 310,
IOMUXC_STX0 = 311,
IOMUXC_SVEN0 = 312,
IOMUXC_SRST0 = 313,
IOMUXC_SCLK0 = 314,
IOMUXC_GPIO3_1 = 315,
IOMUXC_GPIO3_0 = 316,
IOMUXC_GPIO1_6 = 317,
IOMUXC_GPIO1_5 = 318,
IOMUXC_GPIO1_4 = 319,
IOMUXC_GPIO1_3 = 320,
IOMUXC_GPIO1_2 = 321,
IOMUXC_GPIO1_1 = 322,
IOMUXC_GPIO1_0 = 323,
IOMUXC_PWMO = 324,
IOMUXC_WATCHDOG_RST = 325,
IOMUXC_COMPARE = 326,
IOMUXC_CAPTURE = 327,
};
/* Set the pin multiplexing configuration (functional, GPIO, etc.) */
void iomuxc_set_pin_mux(enum IMX31_IOMUXC_PINS pin, unsigned long mux);
/* Set the pin pad configuration (keeper, drive strength, etc.) */
void iomuxc_set_pad_config(enum IMX31_IOMUXC_PINS pin, unsigned long config);
#endif /* _IOMUXC_IMX31_H_ */