2003-12-12 13:29:34 +00:00
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#include "config.h"
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2002-05-02 14:05:51 +00:00
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ENTRY(start)
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2004-10-06 13:30:44 +00:00
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#if CONFIG_CPU == MCF5249
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OUTPUT_FORMAT(elf32-m68k)
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2005-02-10 15:25:16 +00:00
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#elif CONFIG_CPU == TCC730
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OUTPUT_FORMAT(elf32-calmrisc16)
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2004-10-06 13:30:44 +00:00
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#else
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2002-03-28 15:09:10 +00:00
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OUTPUT_FORMAT(elf32-sh)
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2004-10-06 13:30:44 +00:00
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#endif
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2002-05-29 09:12:34 +00:00
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INPUT(crt0.o)
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2002-08-01 08:12:17 +00:00
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2005-02-10 22:37:09 +00:00
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#if CONFIG_CPU == TCC730
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MEMORY
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{
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FIRMWARE : ORIGIN = LOADADDRESS, LENGTH = 256K
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FLASH (RX) : ORIGIN = 0x000000, LENGTH = 1024K
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ICMEM (RX) : ORIGIN = 0x3FC000, LENGTH = 32K
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IMEM1 : ORIGIN = 0x200000, LENGTH = 32K
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IMEM2 : ORIGIN = 0x210000, LENGTH = 32K
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IMEM3 : ORIGIN = 0x220000, LENGTH = 16K
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IMEM4 : ORIGIN = 0x230000, LENGTH = 16K
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DRAM : ORIGIN = 0x000000, LENGTH = 0x3F0000
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}
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SECTIONS
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{
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.text LOADADDRESS : {
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*(.init.text)
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*(.text)
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*(.icode) /* We don't put it in ICMEM coz crt1 uses LCD (now)*/
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}> FLASH AT> FIRMWARE
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.icode 0x3FC040: {
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*(.vectors)
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}> ICMEM AT> FIRMWARE
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2005-02-11 18:42:57 +00:00
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/* We start at 0x2000, to avoid overwriting Archos' loader datasegment.
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* If it turns out that we won't call back the loader, this can be set to 0.
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*/
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.bss 0x2000 : {
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*(.bss)
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. = ALIGN(2);
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}> DRAM
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2005-02-10 22:37:09 +00:00
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2005-02-11 18:42:57 +00:00
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/* Data is put after BSS, to have all strings addresses > VIRT_PTR + VIRT_SIZE.
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Strings are in rodata, so what we really assert is (.rodata > VIRT_PTR + VIRT_SIZE)
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See settings.h for details */
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.data ALIGN(2): {
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2005-02-10 22:37:09 +00:00
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*(.data)
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. = ALIGN(2);
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*(.rodata)
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. = ALIGN(2);
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*(.rodata.str1.2)
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. = ALIGN(2);
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}> DRAM AT> FIRMWARE
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.stack ALIGN(2) : {
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. = . + 0x2000;
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}> DRAM
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.idata 0x200000: {
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*(.idata)
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}> DRAM
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_codesize = SIZEOF(.text);
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_icodecopy = LOADADDR(.icode);
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_icodestart = ADDR(.icode);
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_icodesize = SIZEOF(.icode);
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_datacopy = LOADADDR(.data);
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_datastart = ADDR(.data);
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_datasize = SIZEOF(.data);
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_bssstart = ADDR(.bss);
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_bsssize = (SIZEOF(.bss) + 1) & ~ 1;
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_stackbegin = ADDR(.stack);
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_stackend = ADDR(.stack) + SIZEOF(.stack);
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_idatastart = ADDR(.idata);
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2005-02-11 10:25:15 +00:00
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/* FIXME: Where to put mp3 buffer? */
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_mp3buffer = 0;
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_mp3end = 0;
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/* Plugins are not supported on the Gmini*/
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_pluginbuf = 0;
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2005-02-10 22:37:09 +00:00
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}
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#else
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2005-02-15 14:00:37 +00:00
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#if MEMORYSIZE >= 32
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#define PLUGINSIZE 0xC0000
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#else
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2003-06-29 16:33:04 +00:00
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#define PLUGINSIZE 0x8000
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2005-02-15 14:00:37 +00:00
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#endif
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2003-06-29 16:33:04 +00:00
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2003-02-26 16:05:30 +00:00
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#ifdef DEBUG
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2004-10-06 13:30:44 +00:00
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#define STUBOFFSET 0x10000
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2003-02-26 16:05:30 +00:00
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#else
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2004-10-06 13:30:44 +00:00
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#define STUBOFFSET 0
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2003-02-26 16:05:30 +00:00
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#endif
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2004-10-06 13:30:44 +00:00
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#define DRAMSIZE (MEMORYSIZE * 0x100000) - PLUGINSIZE - STUBOFFSET
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2003-02-26 09:18:13 +00:00
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2004-10-06 13:30:44 +00:00
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#ifdef IRIVER_H100
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2004-10-08 08:02:50 +00:00
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#define DRAMORIG 0x30000000 + STUBOFFSET
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2004-10-06 13:30:44 +00:00
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#define IRAMORIG 0x10000000
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#define IRAMSIZE 0x18000
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#else
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#define DRAMORIG 0x09000000 + STUBOFFSET
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#define IRAMORIG 0x0f000000
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#define IRAMSIZE 0x1000
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#endif
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2004-10-06 13:48:25 +00:00
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#define ENDADDR (DRAMORIG + DRAMSIZE)
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2002-08-01 08:12:17 +00:00
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MEMORY
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{
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2004-10-06 13:30:44 +00:00
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DRAM : ORIGIN = DRAMORIG, LENGTH = DRAMSIZE
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IRAM : ORIGIN = IRAMORIG, LENGTH = IRAMSIZE
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2002-08-01 08:12:17 +00:00
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}
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2002-03-28 15:09:10 +00:00
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SECTIONS
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{
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2002-08-01 08:12:17 +00:00
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.vectors :
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2002-03-28 15:09:10 +00:00
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{
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2002-05-29 09:12:34 +00:00
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*(.resetvectors);
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2002-03-28 15:09:10 +00:00
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*(.vectors);
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2002-08-01 08:12:17 +00:00
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} > DRAM
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2002-05-02 14:05:51 +00:00
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.text :
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{
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2004-07-24 17:56:38 +00:00
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. = ALIGN(0x200);
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*(.init.text)
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2002-03-28 15:09:10 +00:00
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*(.text)
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2003-04-24 20:25:10 +00:00
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. = ALIGN(0x4);
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2002-08-01 08:12:17 +00:00
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} > DRAM
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2002-03-28 15:09:10 +00:00
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2004-07-24 17:56:38 +00:00
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.rodata :
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2002-05-02 14:05:51 +00:00
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{
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2004-07-24 17:56:38 +00:00
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*(.rodata)
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2004-10-07 08:37:25 +00:00
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*(.rodata.str1.1)
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2004-07-24 17:56:38 +00:00
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*(.rodata.str1.4)
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2004-01-28 20:43:31 +00:00
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. = ALIGN(0x4);
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2004-07-24 17:56:38 +00:00
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/* Pseudo-allocate the copies of the data sections */
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_datacopy = .;
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2002-08-01 08:12:17 +00:00
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} > DRAM
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2002-05-02 14:05:51 +00:00
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2004-07-24 17:56:38 +00:00
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/* TRICK ALERT! For RAM execution, we put the .data section at the
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same load address as the copy. Thus, we don't waste extra RAM
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when we don't actually need the copy. */
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.data : AT ( _datacopy )
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2002-05-02 14:05:51 +00:00
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{
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2004-07-24 17:56:38 +00:00
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_datastart = .;
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*(.data)
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2003-04-24 20:25:10 +00:00
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. = ALIGN(0x4);
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2004-07-24 17:56:38 +00:00
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_dataend = .;
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_iramcopy = .;
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2002-08-01 08:12:17 +00:00
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} > DRAM
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2002-05-24 15:37:26 +00:00
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2004-10-07 08:37:25 +00:00
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.iram IRAMORIG : AT ( _iramcopy)
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2004-07-24 17:56:38 +00:00
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{
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_iramstart = .;
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*(.icode)
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*(.idata)
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_iramend = .;
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} > IRAM
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/* TRICK ALERT! We want 0x2000 bytes of stack, but we set the section
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size smaller, and allow the stack to grow into the .iram copy */
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2004-08-09 21:35:57 +00:00
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.stack ADDR(.data) + SIZEOF(.data) + SIZEOF(.iram):
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2002-05-24 15:37:26 +00:00
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{
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*(.stack)
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2004-08-09 21:35:57 +00:00
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_stackbegin = . - SIZEOF(.iram);
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2004-10-15 02:14:45 +00:00
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stackbegin = . - SIZEOF(.iram);
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2004-08-09 21:35:57 +00:00
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. += 0x2000 - SIZEOF(.iram);
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2002-07-15 22:15:00 +00:00
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_stackend = .;
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2004-10-15 02:14:45 +00:00
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stackend = .;
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2002-08-01 08:12:17 +00:00
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} > DRAM
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2002-05-24 15:37:26 +00:00
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2002-08-01 08:58:17 +00:00
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.bss :
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{
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_edata = .;
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*(.bss)
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*(COMMON)
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_end = .;
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} > DRAM
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2002-05-24 15:37:26 +00:00
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.mp3buf :
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{
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2003-05-09 16:01:21 +00:00
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_mp3buffer = .;
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2005-02-03 08:36:18 +00:00
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mp3buffer = .;
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2002-08-01 08:12:17 +00:00
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} > DRAM
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2002-05-24 15:37:26 +00:00
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2003-10-12 16:40:45 +00:00
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.mp3end ENDADDR:
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2002-05-24 15:37:26 +00:00
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{
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2005-02-03 08:36:18 +00:00
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mp3end = .;
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2002-05-24 15:37:26 +00:00
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_mp3end = .;
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2002-08-01 08:12:17 +00:00
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} > DRAM
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2002-03-28 15:09:10 +00:00
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2003-06-29 16:33:04 +00:00
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.plugin ENDADDR:
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{
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_pluginbuf = .;
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2005-02-03 08:36:18 +00:00
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pluginbuf = .;
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2003-06-29 16:33:04 +00:00
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}
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2002-05-24 15:37:26 +00:00
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}
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2005-02-10 22:37:09 +00:00
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#endif
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