133 lines
4.3 KiB
C
133 lines
4.3 KiB
C
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/***************************************************************************
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* __________ __ ___.
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* Open \______ \ ____ ____ | | _\_ |__ _______ ___
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* Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
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* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
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* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
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* \/ \/ \/ \/ \/
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* $Id: $
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*
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* Copyright (C) 2008 by Bertrik Sikken
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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*
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* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
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* KIND, either express or implied.
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*
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****************************************************************************/
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/*
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Provides access to the codec/charger/rtc/adc part of the as3525.
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This part is on address 0x46 of the internal i2c bus in the as3525.
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Registers in the codec part seem to be nearly identical to the registers
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in the AS3514 (used in the "v1" versions of the sansa c200 and e200).
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I2C register description:
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* I2C2_CNTRL needs to be set to 0x51 for transfers to work at all.
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bit 1 indicates direction of transfer (0 = write, 1 = read)
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* I2C2_SR (status register) indicates in bit 0 if a transfer is busy.
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* I2C2_SLAD0 contains the i2c slave address to read from / write to.
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* I2C2_CPSR0/1 is the divider from the peripheral clock to the i2c clock.
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* I2C2_DACNT sets the number of bytes to transfer and actually starts it.
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When a transfer is attempted to a non-existing i2c slave address,
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interrupt bit 7 is raised and DACNT is not decremented after the transfer.
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*/
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#include "as3525-codec.h"
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#include "as3525.h"
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#define AUDIO_I2C_ADDR 0x46
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#define I2C2_DATA *((volatile unsigned int *)(I2C_AUDIO_BASE + 0x00))
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#define I2C2_SLAD0 *((volatile unsigned int *)(I2C_AUDIO_BASE + 0x04))
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#define I2C2_CNTRL *((volatile unsigned int *)(I2C_AUDIO_BASE + 0x0C))
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#define I2C2_DACNT *((volatile unsigned int *)(I2C_AUDIO_BASE + 0x10))
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#define I2C2_CPSR0 *((volatile unsigned int *)(I2C_AUDIO_BASE + 0x1C))
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#define I2C2_CPSR1 *((volatile unsigned int *)(I2C_AUDIO_BASE + 0x20))
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#define I2C2_IMR *((volatile unsigned int *)(I2C_AUDIO_BASE + 0x24))
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#define I2C2_RIS *((volatile unsigned int *)(I2C_AUDIO_BASE + 0x28))
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#define I2C2_MIS *((volatile unsigned int *)(I2C_AUDIO_BASE + 0x2C))
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#define I2C2_SR *((volatile unsigned int *)(I2C_AUDIO_BASE + 0x30))
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#define I2C2_INT_CLR *((volatile unsigned int *)(I2C_AUDIO_BASE + 0x40))
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#define I2C2_SADDR *((volatile unsigned int *)(I2C_AUDIO_BASE + 0x44))
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/* initialises the internal i2c bus and prepares for transfers to the codec */
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void as3525_codec_init(void)
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{
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/* reset device */
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CCU_SRC = CCU_SRC_I2C_AUDIO_EN;
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CCU_SRL = CCU_SRL_MAGIC_NUMBER;
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CCU_SRL = 0;
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/* enable clock */
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CGU_PERI |= CGU_I2C_AUDIO_MASTER_CLOCK_ENABLE;
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/* prescaler for i2c clock */
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I2C2_CPSR0 = 60; /* 24 MHz / 400 kHz */
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I2C2_CPSR1 = 0; /* MSB */
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/* set i2c slave address of codec part */
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I2C2_SLAD0 = AUDIO_I2C_ADDR << 1;
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I2C2_CNTRL = 0x51;
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}
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/* returns != 0 when busy */
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static int i2c_busy(void)
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{
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return (I2C2_SR & 1);
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}
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/* returns 0 on success, <0 otherwise */
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int as3525_codec_write(int index, int value)
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{
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if (index == 0x21) {
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/* prevent setting of the LREG_CP_not bit */
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value &= ~(1 << 5);
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}
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/* check if still busy */
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if (i2c_busy()) {
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return -1;
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}
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/* start transfer */
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I2C2_SADDR = index;
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I2C2_CNTRL &= ~(1 << 1);
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I2C2_DATA = value;
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I2C2_DACNT = 1;
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/* wait for transfer*/
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while (i2c_busy());
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return 0;
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}
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/* returns value read on success, <0 otherwise */
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int as3525_codec_read(int index)
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{
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/* check if still busy */
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if (i2c_busy()) {
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return -1;
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}
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/* start transfer */
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I2C2_SADDR = index;
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I2C2_CNTRL |= (1 << 1);
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I2C2_DACNT = 1;
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/* wait for transfer*/
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while (i2c_busy());
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return I2C2_DATA;
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}
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