2004-09-11 03:48:05 +00:00
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/***************************************************************************
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* __________ __ ___.
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* Open \______ \ ____ ____ | | _\_ |__ _______ ___
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* Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
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* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
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* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
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* \/ \/ \/ \/ \/
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* $Id$
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*
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2004-09-28 06:23:57 +00:00
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* Copyright (C) 2004 by Jens Arnold
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2004-09-11 03:48:05 +00:00
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*
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* All files in this archive are subject to the GNU General Public License.
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* See the file COPYING in the source tree root for full license agreement.
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*
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* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
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* KIND, either express or implied.
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*
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****************************************************************************/
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#include <stdbool.h>
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#include "ata.h"
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2004-10-06 20:43:12 +00:00
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#include "ata_mmc.h"
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2004-09-11 03:48:05 +00:00
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#include "kernel.h"
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#include "thread.h"
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#include "led.h"
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#include "sh7034.h"
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#include "system.h"
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#include "debug.h"
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#include "panic.h"
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#include "usb.h"
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#include "power.h"
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#include "string.h"
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#include "hwcompat.h"
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2004-09-11 09:06:58 +00:00
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#include "adc.h"
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2004-09-28 06:23:57 +00:00
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#include "bitswap.h"
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2004-09-11 03:48:05 +00:00
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#define SECTOR_SIZE 512
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2004-09-28 06:23:57 +00:00
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/* Command definitions */
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#define CMD_GO_IDLE_STATE 0x40 /* R1 */
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#define CMD_SEND_OP_COND 0x41 /* R1 */
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#define CMD_SEND_CSD 0x49 /* R1 */
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2004-10-03 23:32:09 +00:00
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#define CMD_SEND_CID 0x4a /* R1 */
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#define CMD_STOP_TRANSMISSION 0x4c /* R1 */
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#define CMD_SEND_STATUS 0x4d /* R2 */
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2004-09-28 06:23:57 +00:00
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#define CMD_READ_SINGLE_BLOCK 0x51 /* R1 */
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#define CMD_READ_MULTIPLE_BLOCK 0x52 /* R1 */
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#define CMD_WRITE_BLOCK 0x58 /* R1b */
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#define CMD_WRITE_MULTIPLE_BLOCK 0x59 /* R1b */
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2004-10-03 23:32:09 +00:00
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#define CMD_READ_OCR 0x7a /* R3 */
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2004-09-28 06:23:57 +00:00
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/* Response formats:
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R1 = single byte, msb=0, various error flags
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R1b = R1 + busy token(s)
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R2 = 2 bytes (1st byte identical to R1), additional flags
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R3 = 5 bytes (R1 + OCR register)
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*/
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#define R1_PARAMETER_ERR 0x40
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#define R1_ADDRESS_ERR 0x20
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#define R1_ERASE_SEQ_ERR 0x10
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#define R1_COM_CRC_ERR 0x08
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#define R1_ILLEGAL_CMD 0x04
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#define R1_ERASE_RESET 0x02
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#define R1_IN_IDLE_STATE 0x01
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#define R2_OUT_OF_RANGE 0x80
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#define R2_ERASE_PARAM 0x40
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#define R2_WP_VIOLATION 0x20
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#define R2_CARD_ECC_FAIL 0x10
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#define R2_CC_ERROR 0x08
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#define R2_ERROR 0x04
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#define R2_ERASE_SKIP 0x02
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#define R2_CARD_LOCKED 0x01
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2004-10-03 23:32:09 +00:00
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/* Data start tokens */
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#define DT_START_BLOCK 0xfe
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#define DT_START_WRITE_MULTIPLE 0xfc
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#define DT_STOP_TRAN 0xfd
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2004-09-11 03:48:05 +00:00
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/* for compatibility */
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bool old_recorder = false; /* FIXME: get rid of this cross-dependency */
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int ata_spinup_time = 0;
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char ata_device = 0; /* device 0 (master) or 1 (slave) */
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int ata_io_address = 0; /* 0x300 or 0x200, only valid on recorder */
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2004-09-28 06:23:57 +00:00
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long last_disk_activity = -1;
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2004-09-11 03:48:05 +00:00
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2004-09-28 06:23:57 +00:00
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/* private variables */
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2004-09-11 03:48:05 +00:00
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2004-10-03 23:32:09 +00:00
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static struct mutex mmc_mutex;
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2004-09-11 03:48:05 +00:00
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static bool initialized = false;
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2004-10-04 22:29:06 +00:00
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static bool delayed_write = false;
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static unsigned char delayed_sector[SECTOR_SIZE];
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static int delayed_sector_num;
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2004-10-09 01:14:55 +00:00
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static enum {
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SER_POLL_WRITE,
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SER_POLL_READ,
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SER_DISABLED
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} serial_mode;
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2004-09-28 06:23:57 +00:00
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static const unsigned char dummy[] = {
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0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF
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};
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2004-10-09 01:14:55 +00:00
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/* 2 buffers for writing, include start token and dummy crc and an extra
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* byte to keep word alignment */
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static unsigned char sector_buffer[2][(SECTOR_SIZE+4)];
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static int current_buffer = 0;
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2004-09-28 06:23:57 +00:00
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static tCardInfo card_info[2];
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2004-10-09 01:14:55 +00:00
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static int current_card = 0;
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2004-10-10 00:35:19 +00:00
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static bool last_mmc_status = false;
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static int countdown; /* for mmc switch debouncing */
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2004-09-28 06:23:57 +00:00
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/* private function declarations */
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static int select_card(int card_no);
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static void deselect_card(void);
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static void setup_sci1(int bitrate_register);
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2004-10-09 01:14:55 +00:00
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static void set_sci1_poll_read(void);
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2004-09-28 06:23:57 +00:00
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static void write_transfer(const unsigned char *buf, int len)
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__attribute__ ((section(".icode")));
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static void read_transfer(unsigned char *buf, int len)
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__attribute__ ((section(".icode")));
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static unsigned char poll_byte(int timeout);
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2004-10-03 23:32:09 +00:00
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static unsigned char poll_busy(int timeout);
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2004-09-28 06:23:57 +00:00
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static int send_cmd(int cmd, unsigned long parameter, unsigned char *response);
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2004-10-09 01:14:55 +00:00
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static int receive_cxd(unsigned char *buf);
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2004-09-28 06:23:57 +00:00
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static int initialize_card(int card_no);
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2004-10-09 01:14:55 +00:00
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static int receive_sector(unsigned char *inbuf, unsigned char *swapbuf,
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int timeout);
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static void swapcopy_sector(const unsigned char *buf);
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static int send_sector(const unsigned char *nextbuf, int timeout);
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static int send_single_sector(const unsigned char *buf, int timeout);
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2004-09-28 06:23:57 +00:00
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2004-10-10 00:35:19 +00:00
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static void mmc_tick(void);
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2004-09-28 06:23:57 +00:00
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/* implementation */
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2004-10-10 19:51:11 +00:00
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void mmc_select_clock(int card_no)
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2004-09-28 06:23:57 +00:00
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{
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2004-10-01 17:01:40 +00:00
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if (card_no == 0) /* internal */
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or_b(0x10, &PADRH); /* set clock gate PA12 CHECKME: mask? */
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else /* external */
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and_b(~0x10, &PADRH); /* clear clock gate PA12 CHECKME: mask?*/
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2004-10-10 19:51:11 +00:00
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}
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static int select_card(int card_no)
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{
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mmc_select_clock(card_no);
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2004-10-06 20:43:12 +00:00
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last_disk_activity = current_tick;
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2004-10-01 17:01:40 +00:00
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2004-09-29 00:50:40 +00:00
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if (!card_info[card_no].initialized)
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{
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2004-09-29 01:10:32 +00:00
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setup_sci1(7); /* Initial rate: 375 kbps (need <= 400 per mmc specs) */
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2004-09-29 00:50:40 +00:00
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write_transfer(dummy, 10); /* allow the card to synchronize */
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while (!(SSR1 & SCI_TEND));
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}
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2004-10-01 17:01:40 +00:00
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if (card_no == 0) /* internal */
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2004-09-28 06:23:57 +00:00
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and_b(~0x04, &PADRH); /* assert CS */
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2004-10-01 17:01:40 +00:00
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else /* external */
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2004-09-28 06:23:57 +00:00
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and_b(~0x02, &PADRH); /* assert CS */
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2004-09-11 03:48:05 +00:00
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2004-09-28 06:23:57 +00:00
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if (card_info[card_no].initialized)
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{
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setup_sci1(card_info[card_no].bitrate_register);
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return 0;
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}
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else
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{
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return initialize_card(card_no);
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}
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}
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static void deselect_card(void)
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{
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2004-09-29 00:50:40 +00:00
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while (!(SSR1 & SCI_TEND)); /* wait for end of transfer */
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2004-09-28 06:23:57 +00:00
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or_b(0x06, &PADRH); /* deassert CS (both cards) */
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2004-10-06 20:43:12 +00:00
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last_disk_activity = current_tick;
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2004-09-28 06:23:57 +00:00
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}
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static void setup_sci1(int bitrate_register)
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{
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2004-09-29 00:50:40 +00:00
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while (!(SSR1 & SCI_TEND)); /* wait for end of transfer */
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2004-09-28 06:23:57 +00:00
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SCR1 = 0; /* disable serial port */
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SMR1 = SYNC_MODE; /* no prescale */
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BRR1 = bitrate_register;
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SSR1 = 0;
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2004-10-09 01:14:55 +00:00
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SCR1 = SCI_TE; /* enable transmitter */
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serial_mode = SER_POLL_WRITE;
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}
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static void set_sci1_poll_read(void)
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{
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2004-11-14 07:35:48 +00:00
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while (!(SSR1 & SCI_TEND)); /* wait for end of transfer */
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2004-10-09 01:14:55 +00:00
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SCR1 = 0; /* disable transmitter (& receiver) */
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SCR1 = (SCI_TE|SCI_RE); /* re-enable transmitter & receiver */
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2004-11-14 07:35:48 +00:00
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while (!(SSR1 & SCI_TEND)); /* wait for SCI init completion (!) */
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2004-10-09 01:14:55 +00:00
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serial_mode = SER_POLL_READ;
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TDR1 = 0xFF; /* send do-nothing while reading */
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2004-09-28 06:23:57 +00:00
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}
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static void write_transfer(const unsigned char *buf, int len)
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{
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const unsigned char *buf_end = buf + len;
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2004-10-04 17:53:53 +00:00
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register unsigned char data;
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2004-09-28 06:23:57 +00:00
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2004-10-09 01:14:55 +00:00
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if (serial_mode != SER_POLL_WRITE)
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{
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2004-11-14 07:35:48 +00:00
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while (!(SSR1 & SCI_TEND)); /* wait for end of transfer */
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2004-10-09 01:14:55 +00:00
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SCR1 = 0; /* disable transmitter & receiver */
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SSR1 = 0; /* clear all flags */
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SCR1 = SCI_TE; /* enable transmitter only */
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serial_mode = SER_POLL_WRITE;
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}
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2004-09-28 06:23:57 +00:00
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while (buf < buf_end)
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{
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2004-10-04 17:53:53 +00:00
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data = fliptable[(signed char)(*buf++)]; /* bitswap */
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2004-10-09 01:14:55 +00:00
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while (!(SSR1 & SCI_TDRE)); /* wait for end of transfer */
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2004-10-04 17:53:53 +00:00
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TDR1 = data; /* write byte */
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2004-09-28 06:23:57 +00:00
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SSR1 = 0; /* start transmitting */
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}
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}
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2004-10-04 17:53:53 +00:00
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/* don't call this with len == 0 */
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2004-09-28 06:23:57 +00:00
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static void read_transfer(unsigned char *buf, int len)
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{
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2004-10-04 17:53:53 +00:00
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unsigned char *buf_end = buf + len - 1;
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register signed char data;
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2004-09-28 06:23:57 +00:00
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2004-10-09 01:14:55 +00:00
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if (serial_mode != SER_POLL_READ)
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set_sci1_poll_read();
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2004-09-28 06:23:57 +00:00
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2004-10-04 17:53:53 +00:00
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SSR1 = 0; /* start receiving first byte */
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2004-09-28 06:23:57 +00:00
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while (buf < buf_end)
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{
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2004-10-04 17:53:53 +00:00
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while (!(SSR1 & SCI_RDRF)); /* wait for data */
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data = RDR1; /* read byte */
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SSR1 = 0; /* start receiving */
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*buf++ = fliptable[data]; /* bitswap */
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2004-09-28 06:23:57 +00:00
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}
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2004-10-04 17:53:53 +00:00
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while (!(SSR1 & SCI_RDRF)); /* wait for last byte */
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*buf = fliptable[(signed char)(RDR1)]; /* read & bitswap */
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2004-09-28 06:23:57 +00:00
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}
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2004-10-09 22:48:10 +00:00
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/* returns 0xFF on timeout, timeout is in bytes */
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static unsigned char poll_byte(int timeout)
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2004-09-28 06:23:57 +00:00
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{
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int i;
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unsigned char data = 0; /* stop the compiler complaining */
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2004-10-09 01:14:55 +00:00
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if (serial_mode != SER_POLL_READ)
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set_sci1_poll_read();
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2004-09-28 06:23:57 +00:00
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i = 0;
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do {
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SSR1 = 0; /* start receiving */
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while (!(SSR1 & SCI_RDRF)); /* wait for data */
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data = RDR1; /* read byte */
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} while ((data == 0xFF) && (++i < timeout));
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return fliptable[(signed char)data];
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}
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2004-09-11 03:48:05 +00:00
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2004-10-09 22:48:10 +00:00
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/* returns 0 on timeout, timeout is in bytes */
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static unsigned char poll_busy(int timeout)
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2004-09-29 00:50:40 +00:00
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{
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int i;
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2004-09-29 22:44:02 +00:00
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unsigned char data, dummy;
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2004-09-29 00:50:40 +00:00
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2004-10-09 01:14:55 +00:00
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if (serial_mode != SER_POLL_READ)
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set_sci1_poll_read();
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2004-09-29 22:44:02 +00:00
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/* get data response */
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SSR1 = 0; /* start receiving */
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while (!(SSR1 & SCI_RDRF)); /* wait for data */
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2004-10-04 22:29:06 +00:00
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data = fliptable[(signed char)(RDR1)]; /* read byte */
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2004-09-29 22:44:02 +00:00
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/* wait until the card is ready again */
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2004-09-29 00:50:40 +00:00
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i = 0;
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do {
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SSR1 = 0; /* start receiving */
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while (!(SSR1 & SCI_RDRF)); /* wait for data */
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2004-09-29 22:44:02 +00:00
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dummy = RDR1; /* read byte */
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} while ((dummy != 0xFF) && (++i < timeout));
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|
|
2004-10-09 22:48:10 +00:00
|
|
|
return (dummy == 0xFF) ? data : 0;
|
2004-09-29 00:50:40 +00:00
|
|
|
}
|
|
|
|
|
2004-10-09 01:14:55 +00:00
|
|
|
/* Send MMC command and get response */
|
2004-09-28 06:23:57 +00:00
|
|
|
static int send_cmd(int cmd, unsigned long parameter, unsigned char *response)
|
|
|
|
{
|
2004-10-03 23:32:09 +00:00
|
|
|
unsigned char command[] = {0x40, 0x00, 0x00, 0x00, 0x00, 0x95, 0xFF};
|
2004-09-28 06:23:57 +00:00
|
|
|
|
|
|
|
command[0] = cmd;
|
|
|
|
|
|
|
|
if (parameter != 0)
|
|
|
|
{
|
|
|
|
command[1] = (parameter >> 24) & 0xFF;
|
|
|
|
command[2] = (parameter >> 16) & 0xFF;
|
|
|
|
command[3] = (parameter >> 8) & 0xFF;
|
|
|
|
command[4] = parameter & 0xFF;
|
|
|
|
}
|
|
|
|
|
2004-10-03 23:32:09 +00:00
|
|
|
write_transfer(command, 7);
|
2004-09-28 06:23:57 +00:00
|
|
|
|
2004-09-29 00:50:40 +00:00
|
|
|
response[0] = poll_byte(20);
|
2004-10-09 01:14:55 +00:00
|
|
|
|
2004-09-28 06:23:57 +00:00
|
|
|
if (response[0] != 0x00)
|
|
|
|
{
|
|
|
|
write_transfer(dummy, 1);
|
2004-11-07 22:40:24 +00:00
|
|
|
return -10;
|
2004-09-28 06:23:57 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
switch (cmd)
|
|
|
|
{
|
|
|
|
case CMD_SEND_CSD: /* R1 response, leave open */
|
|
|
|
case CMD_SEND_CID:
|
|
|
|
case CMD_READ_SINGLE_BLOCK:
|
2004-10-03 23:32:09 +00:00
|
|
|
case CMD_READ_MULTIPLE_BLOCK:
|
2004-09-28 06:23:57 +00:00
|
|
|
break;
|
|
|
|
|
|
|
|
case CMD_SEND_STATUS: /* R2 response, close with dummy */
|
|
|
|
read_transfer(response + 1, 1);
|
|
|
|
write_transfer(dummy, 1);
|
|
|
|
break;
|
|
|
|
|
|
|
|
case CMD_READ_OCR: /* R3 response, close with dummy */
|
|
|
|
read_transfer(response + 1, 4);
|
|
|
|
write_transfer(dummy, 1);
|
|
|
|
break;
|
|
|
|
|
|
|
|
default: /* R1 response, close with dummy */
|
|
|
|
write_transfer(dummy, 1);
|
|
|
|
break; /* also catches block writes */
|
|
|
|
}
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2004-10-09 01:14:55 +00:00
|
|
|
/* Receive CID/ CSD data (16 bytes) */
|
|
|
|
static int receive_cxd(unsigned char *buf)
|
2004-09-28 06:23:57 +00:00
|
|
|
{
|
2004-10-09 01:14:55 +00:00
|
|
|
if (poll_byte(20) != DT_START_BLOCK)
|
2004-09-28 06:23:57 +00:00
|
|
|
{
|
|
|
|
write_transfer(dummy, 1);
|
2004-11-07 22:40:24 +00:00
|
|
|
return -11; /* not start of data */
|
2004-09-28 06:23:57 +00:00
|
|
|
}
|
2004-09-29 00:50:40 +00:00
|
|
|
|
2004-10-09 01:14:55 +00:00
|
|
|
read_transfer(buf, 16);
|
|
|
|
write_transfer(dummy, 3); /* 2 bytes dontcare crc + 1 byte trailer */
|
|
|
|
return 0;
|
2004-09-29 00:50:40 +00:00
|
|
|
}
|
|
|
|
|
2004-10-06 20:43:12 +00:00
|
|
|
/* helper function to extract n (<=32) bits from an arbitrary position.
|
|
|
|
counting from MSB to LSB */
|
|
|
|
unsigned long mmc_extract_bits(
|
|
|
|
const unsigned long *p, /* the start of the bitfield array */
|
|
|
|
unsigned int start, /* bit no. to start reading */
|
|
|
|
unsigned int size) /* how many bits to read */
|
|
|
|
{
|
|
|
|
unsigned int bit_index;
|
|
|
|
unsigned int bits_to_use;
|
|
|
|
unsigned long mask;
|
|
|
|
unsigned long result;
|
|
|
|
|
|
|
|
if (size == 1)
|
|
|
|
{ /* short cut */
|
|
|
|
return ((p[start/32] >> (31 - (start % 32))) & 1);
|
|
|
|
}
|
|
|
|
|
|
|
|
result = 0;
|
|
|
|
while (size)
|
|
|
|
{
|
|
|
|
bit_index = start % 32;
|
|
|
|
bits_to_use = MIN(32 - bit_index, size);
|
|
|
|
mask = 0xFFFFFFFF >> (32 - bits_to_use);
|
|
|
|
|
|
|
|
result <<= bits_to_use; /* start last round */
|
|
|
|
result |= (p[start/32] >> (32 - bits_to_use - bit_index)) & mask;
|
|
|
|
|
|
|
|
start += bits_to_use;
|
|
|
|
size -= bits_to_use;
|
|
|
|
}
|
|
|
|
|
|
|
|
return result;
|
|
|
|
}
|
|
|
|
|
2004-09-28 06:23:57 +00:00
|
|
|
static int initialize_card(int card_no)
|
|
|
|
{
|
|
|
|
int i, temp;
|
2004-10-06 20:43:12 +00:00
|
|
|
unsigned char response[5];
|
2004-09-28 06:23:57 +00:00
|
|
|
tCardInfo *card = &card_info[card_no];
|
|
|
|
|
|
|
|
static const char mantissa[] = { /* *10 */
|
|
|
|
0, 10, 12, 13, 15, 20, 25, 30,
|
|
|
|
35, 40, 45, 50, 55, 60, 70, 80
|
|
|
|
};
|
2004-10-06 20:43:12 +00:00
|
|
|
static const int exponent[] = { /* use varies */
|
|
|
|
1, 10, 100, 1000, 10000, 100000, 1000000,
|
|
|
|
10000000, 100000000, 1000000000
|
2004-09-28 06:23:57 +00:00
|
|
|
};
|
|
|
|
|
|
|
|
/* switch to SPI mode */
|
2004-10-06 20:43:12 +00:00
|
|
|
send_cmd(CMD_GO_IDLE_STATE, 0, response);
|
|
|
|
if (response[0] != 0x01)
|
2004-09-28 06:23:57 +00:00
|
|
|
return -1; /* error response */
|
|
|
|
|
|
|
|
/* initialize card */
|
|
|
|
i = 0;
|
2004-11-14 07:35:48 +00:00
|
|
|
while (send_cmd(CMD_SEND_OP_COND, 0, response) && (++i < 500));
|
2004-10-06 20:43:12 +00:00
|
|
|
if (response[0] != 0x00)
|
2004-09-28 06:23:57 +00:00
|
|
|
return -2; /* not ready */
|
2004-10-06 20:43:12 +00:00
|
|
|
|
|
|
|
/* get OCR register */
|
|
|
|
if (send_cmd(CMD_READ_OCR, 0, response))
|
2004-09-28 06:23:57 +00:00
|
|
|
return -3;
|
2004-10-06 20:43:12 +00:00
|
|
|
card->ocr = (response[1] << 24) + (response[2] << 16)
|
|
|
|
+ (response[3] << 8) + response[4];
|
2004-09-28 06:23:57 +00:00
|
|
|
|
2004-10-06 20:43:12 +00:00
|
|
|
/* check voltage */
|
|
|
|
if (!(card->ocr & 0x00100000)) /* 3.2 .. 3.3 V */
|
|
|
|
return -4;
|
|
|
|
|
|
|
|
/* get CSD register */
|
|
|
|
if (send_cmd(CMD_SEND_CSD, 0, response))
|
2004-09-28 06:23:57 +00:00
|
|
|
return -5;
|
2004-10-09 01:14:55 +00:00
|
|
|
if (receive_cxd((unsigned char*)card->csd))
|
2004-10-06 20:43:12 +00:00
|
|
|
return -6;
|
2004-09-28 06:23:57 +00:00
|
|
|
|
2004-10-06 20:43:12 +00:00
|
|
|
/* check block size */
|
|
|
|
if ((1 << mmc_extract_bits(card->csd, 44, 4)) != SECTOR_SIZE)
|
|
|
|
return -7;
|
|
|
|
|
|
|
|
/* max transmission speed, clock divider */
|
|
|
|
temp = mmc_extract_bits(card->csd, 29, 3);
|
|
|
|
temp = (temp > 3) ? 3 : temp;
|
|
|
|
card->speed = mantissa[mmc_extract_bits(card->csd, 25, 4)]
|
|
|
|
* exponent[temp + 4];
|
2004-09-28 06:23:57 +00:00
|
|
|
card->bitrate_register = (FREQ/4-1) / card->speed;
|
|
|
|
|
2004-10-06 20:43:12 +00:00
|
|
|
/* NSAC, TSAC, read timeout */
|
|
|
|
card->nsac = 100 * mmc_extract_bits(card->csd, 16, 8);
|
|
|
|
card->tsac = mantissa[mmc_extract_bits(card->csd, 9, 4)];
|
|
|
|
temp = mmc_extract_bits(card->csd, 13, 3);
|
|
|
|
card->read_timeout = ((FREQ/4) / (card->bitrate_register + 1)
|
|
|
|
* card->tsac / exponent[9 - temp]
|
|
|
|
+ (10 * card->nsac));
|
|
|
|
card->read_timeout /= 8; /* clocks -> bytes */
|
|
|
|
card->tsac *= exponent[temp];
|
|
|
|
|
|
|
|
/* r2w_factor, write timeout */
|
|
|
|
temp = mmc_extract_bits(card->csd, 99, 3);
|
|
|
|
temp = (temp > 5) ? 5 : temp;
|
|
|
|
card->r2w_factor = 1 << temp;
|
|
|
|
card->write_timeout = card->read_timeout * card->r2w_factor;
|
2004-09-28 06:23:57 +00:00
|
|
|
|
|
|
|
/* switch to full speed */
|
|
|
|
setup_sci1(card->bitrate_register);
|
|
|
|
|
|
|
|
/* get CID register */
|
2004-10-06 20:43:12 +00:00
|
|
|
if (send_cmd(CMD_SEND_CID, 0, response))
|
|
|
|
return -8;
|
2004-10-09 01:14:55 +00:00
|
|
|
if (receive_cxd((unsigned char*)card->cid))
|
2004-10-06 20:43:12 +00:00
|
|
|
return -9;
|
2004-09-28 06:23:57 +00:00
|
|
|
|
|
|
|
card->initialized = true;
|
|
|
|
return 0;
|
|
|
|
}
|
2004-09-11 03:48:05 +00:00
|
|
|
|
2004-10-06 20:43:12 +00:00
|
|
|
tCardInfo *mmc_card_info(int card_no)
|
|
|
|
{
|
|
|
|
tCardInfo *card = &card_info[card_no];
|
|
|
|
|
2004-10-10 00:35:19 +00:00
|
|
|
if (!card->initialized && ((card_no == 0) || mmc_detect()))
|
2004-10-06 20:43:12 +00:00
|
|
|
{
|
2004-10-10 00:35:19 +00:00
|
|
|
mutex_lock(&mmc_mutex);
|
2004-10-06 20:43:12 +00:00
|
|
|
select_card(card_no);
|
|
|
|
deselect_card();
|
2004-10-10 00:35:19 +00:00
|
|
|
mutex_unlock(&mmc_mutex);
|
2004-10-06 20:43:12 +00:00
|
|
|
}
|
|
|
|
return card;
|
|
|
|
}
|
|
|
|
|
2004-10-09 01:14:55 +00:00
|
|
|
/* Receive one sector with dma, possibly swapping the previously received
|
|
|
|
* sector in the background */
|
|
|
|
static int receive_sector(unsigned char *inbuf, unsigned char *swapbuf,
|
|
|
|
int timeout)
|
|
|
|
{
|
|
|
|
if (poll_byte(timeout) != DT_START_BLOCK)
|
|
|
|
{
|
|
|
|
write_transfer(dummy, 1);
|
2004-11-07 22:40:24 +00:00
|
|
|
return -12; /* not start of data */
|
2004-10-09 01:14:55 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
while (!(SSR1 & SCI_TEND)); /* wait for end of transfer */
|
|
|
|
|
|
|
|
SCR1 = 0; /* disable serial */
|
|
|
|
SSR1 = 0; /* clear all flags */
|
|
|
|
|
|
|
|
/* setup DMA channel 2 */
|
|
|
|
CHCR2 = 0; /* disable */
|
|
|
|
SAR2 = RDR1_ADDR;
|
|
|
|
DAR2 = (unsigned long) inbuf;
|
|
|
|
DTCR2 = SECTOR_SIZE;
|
|
|
|
CHCR2 = 0x4601; /* fixed source address, RXI1, enable */
|
|
|
|
DMAOR = 0x0001;
|
|
|
|
SCR1 = (SCI_RE|SCI_RIE); /* kick off DMA */
|
|
|
|
|
|
|
|
/* dma receives 2 bytes more than DTCR2, but the last 2 bytes are not
|
|
|
|
* stored. The first extra byte is available from RDR1 after the DMA ends,
|
|
|
|
* the second one is lost because of the SCI overrun. However, this
|
|
|
|
* behaviour conveniently discards the crc. */
|
|
|
|
|
|
|
|
if (swapbuf != NULL) /* bitswap previous sector */
|
|
|
|
bitswap(swapbuf, SECTOR_SIZE);
|
|
|
|
yield(); /* be nice */
|
|
|
|
|
|
|
|
while (!(CHCR2 & 0x0002)); /* wait for end of DMA */
|
|
|
|
while (!(SSR1 & SCI_ORER)); /* wait for the trailing bytes */
|
|
|
|
SCR1 = 0;
|
|
|
|
serial_mode = SER_DISABLED;
|
|
|
|
|
|
|
|
write_transfer(dummy, 1); /* send trailer */
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* copies one sector into the next-current write buffer, then bitswaps */
|
|
|
|
static void swapcopy_sector(const unsigned char *buf)
|
|
|
|
{
|
|
|
|
unsigned char *curbuf;
|
|
|
|
|
|
|
|
current_buffer ^= 1; /* toggles between 0 and 1 */
|
|
|
|
|
|
|
|
curbuf = sector_buffer[current_buffer];
|
|
|
|
curbuf[1] = DT_START_WRITE_MULTIPLE;
|
|
|
|
curbuf[(SECTOR_SIZE+2)] = curbuf[(SECTOR_SIZE+3)] = 0xFF; /* dummy crc */
|
|
|
|
memcpy(curbuf + 2, buf, SECTOR_SIZE);
|
|
|
|
bitswap(curbuf + 1, (SECTOR_SIZE+1));
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Send one sector with dma from the current sector buffer, possibly preparing
|
|
|
|
* the next sector within the other sector buffer in the background. Use
|
|
|
|
* for multisector transfer only */
|
|
|
|
static int send_sector(const unsigned char *nextbuf, int timeout)
|
|
|
|
{
|
|
|
|
int ret = 0;
|
|
|
|
|
|
|
|
while (!(SSR1 & SCI_TEND)); /* wait for end of transfer */
|
|
|
|
|
|
|
|
SCR1 = 0; /* disable serial */
|
|
|
|
SSR1 = 0; /* clear all flags */
|
|
|
|
|
|
|
|
/* setup DMA channel 2 */
|
|
|
|
CHCR2 = 0; /* disable */
|
|
|
|
SAR2 = (unsigned long)(sector_buffer[current_buffer] + 1);
|
|
|
|
DAR2 = TDR1_ADDR;
|
|
|
|
DTCR2 = (SECTOR_SIZE+3);
|
|
|
|
CHCR2 = 0x1701; /* fixed dest. address, TXI1, enable */
|
|
|
|
DMAOR = 0x0001;
|
|
|
|
SCR1 = (SCI_TE|SCI_TIE); /* kick off DMA */
|
|
|
|
|
|
|
|
if (nextbuf != NULL) /* prepare next sector */
|
|
|
|
swapcopy_sector(nextbuf);
|
|
|
|
yield(); /* be nice */
|
|
|
|
|
|
|
|
while (!(CHCR2 & 0x0002)); /* wait for end of DMA */
|
|
|
|
while (!(SSR1 & SCI_TEND)); /* wait for end of transfer */
|
|
|
|
SCR1 = 0;
|
|
|
|
serial_mode = SER_DISABLED;
|
|
|
|
|
|
|
|
if ((poll_busy(timeout) & 0x1F) != 0x05) /* something went wrong */
|
2004-11-07 22:40:24 +00:00
|
|
|
ret = -13;
|
2004-10-09 01:14:55 +00:00
|
|
|
|
|
|
|
write_transfer(dummy, 1);
|
|
|
|
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Send one sector with polled i/o. Use for single sector transfers only. */
|
|
|
|
static int send_single_sector(const unsigned char *buf, int timeout)
|
|
|
|
{
|
|
|
|
int ret = 0;
|
|
|
|
unsigned char start_token = DT_START_BLOCK;
|
|
|
|
|
|
|
|
write_transfer(&start_token, 1);
|
|
|
|
write_transfer(buf, SECTOR_SIZE);
|
|
|
|
write_transfer(dummy, 2); /* crc - dontcare */
|
|
|
|
|
|
|
|
if ((poll_busy(timeout) & 0x1F) != 0x05) /* something went wrong */
|
2004-11-07 22:40:24 +00:00
|
|
|
ret = -14;
|
2004-10-09 01:14:55 +00:00
|
|
|
|
|
|
|
write_transfer(dummy, 1);
|
|
|
|
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
2004-10-03 23:32:09 +00:00
|
|
|
int ata_read_sectors(unsigned long start,
|
|
|
|
int incount,
|
|
|
|
void* inbuf)
|
|
|
|
{
|
|
|
|
int ret = 0;
|
|
|
|
int i;
|
|
|
|
unsigned long addr;
|
|
|
|
unsigned char response;
|
2004-10-09 01:14:55 +00:00
|
|
|
void *inbuf_prev = NULL;
|
2004-10-03 23:32:09 +00:00
|
|
|
tCardInfo *card = &card_info[current_card];
|
2004-10-09 01:14:55 +00:00
|
|
|
|
2004-10-03 23:32:09 +00:00
|
|
|
addr = start * SECTOR_SIZE;
|
|
|
|
|
|
|
|
mutex_lock(&mmc_mutex);
|
|
|
|
ret = select_card(current_card);
|
|
|
|
|
|
|
|
if (ret == 0)
|
|
|
|
{
|
|
|
|
if (incount == 1)
|
|
|
|
{
|
|
|
|
ret = send_cmd(CMD_READ_SINGLE_BLOCK, addr, &response);
|
|
|
|
if (ret == 0)
|
2004-10-09 01:14:55 +00:00
|
|
|
{
|
|
|
|
ret = receive_sector(inbuf, inbuf_prev, card->read_timeout);
|
|
|
|
inbuf_prev = inbuf;
|
2004-10-06 20:43:12 +00:00
|
|
|
last_disk_activity = current_tick;
|
2004-10-09 01:14:55 +00:00
|
|
|
}
|
2004-10-03 23:32:09 +00:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
ret = send_cmd(CMD_READ_MULTIPLE_BLOCK, addr, &response);
|
|
|
|
for (i = 0; (i < incount) && (ret == 0); i++)
|
|
|
|
{
|
2004-10-09 01:14:55 +00:00
|
|
|
ret = receive_sector(inbuf, inbuf_prev, card->read_timeout);
|
|
|
|
inbuf_prev = inbuf;
|
2004-10-03 23:32:09 +00:00
|
|
|
inbuf += SECTOR_SIZE;
|
2004-10-06 20:43:12 +00:00
|
|
|
last_disk_activity = current_tick;
|
2004-10-03 23:32:09 +00:00
|
|
|
}
|
|
|
|
if (ret == 0)
|
|
|
|
ret = send_cmd(CMD_STOP_TRANSMISSION, 0, &response);
|
|
|
|
}
|
2004-10-09 01:14:55 +00:00
|
|
|
if (ret == 0)
|
|
|
|
bitswap(inbuf_prev, SECTOR_SIZE);
|
2004-10-03 23:32:09 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
deselect_card();
|
|
|
|
mutex_unlock(&mmc_mutex);
|
2004-09-11 03:48:05 +00:00
|
|
|
|
2004-10-04 22:29:06 +00:00
|
|
|
/* only flush if reading went ok */
|
|
|
|
if ( (ret == 0) && delayed_write )
|
|
|
|
ata_flush();
|
|
|
|
|
2004-10-03 23:32:09 +00:00
|
|
|
return ret;
|
|
|
|
}
|
2004-09-11 03:48:05 +00:00
|
|
|
|
|
|
|
int ata_write_sectors(unsigned long start,
|
|
|
|
int count,
|
|
|
|
const void* buf)
|
|
|
|
{
|
|
|
|
int ret = 0;
|
2004-09-29 00:50:40 +00:00
|
|
|
int i;
|
|
|
|
unsigned long addr;
|
|
|
|
unsigned char response;
|
|
|
|
tCardInfo *card = &card_info[current_card];
|
2004-09-11 03:48:05 +00:00
|
|
|
|
|
|
|
if (start == 0)
|
|
|
|
panicf("Writing on sector 0\n");
|
|
|
|
|
2004-10-03 23:32:09 +00:00
|
|
|
addr = start * SECTOR_SIZE;
|
|
|
|
|
|
|
|
mutex_lock(&mmc_mutex);
|
2004-09-29 00:50:40 +00:00
|
|
|
ret = select_card(current_card);
|
2004-09-11 03:48:05 +00:00
|
|
|
|
2004-10-03 23:32:09 +00:00
|
|
|
if (ret == 0)
|
2004-09-29 00:50:40 +00:00
|
|
|
{
|
2004-10-03 23:32:09 +00:00
|
|
|
if (count == 1)
|
|
|
|
{
|
|
|
|
ret = send_cmd(CMD_WRITE_BLOCK, addr, &response);
|
|
|
|
if (ret == 0)
|
2004-10-09 01:14:55 +00:00
|
|
|
ret = send_single_sector(buf, card->write_timeout);
|
2004-10-06 20:43:12 +00:00
|
|
|
last_disk_activity = current_tick;
|
2004-10-03 23:32:09 +00:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
2004-10-09 01:14:55 +00:00
|
|
|
swapcopy_sector(buf); /* prepare first sector */
|
2004-10-03 23:32:09 +00:00
|
|
|
ret = send_cmd(CMD_WRITE_MULTIPLE_BLOCK, addr, &response);
|
2004-10-09 01:14:55 +00:00
|
|
|
for (i = 1; (i < count) && (ret == 0); i++)
|
2004-10-03 23:32:09 +00:00
|
|
|
{
|
|
|
|
buf += SECTOR_SIZE;
|
2004-10-09 01:14:55 +00:00
|
|
|
ret = send_sector(buf, card->write_timeout);
|
2004-10-06 20:43:12 +00:00
|
|
|
last_disk_activity = current_tick;
|
2004-10-03 23:32:09 +00:00
|
|
|
}
|
|
|
|
if (ret == 0)
|
|
|
|
{
|
2004-10-09 01:14:55 +00:00
|
|
|
ret = send_sector(NULL, card->write_timeout);
|
|
|
|
if (ret == 0)
|
|
|
|
{
|
|
|
|
response = DT_STOP_TRAN;
|
|
|
|
write_transfer(&response, 1);
|
|
|
|
poll_busy(card->write_timeout);
|
|
|
|
}
|
2004-10-06 20:43:12 +00:00
|
|
|
last_disk_activity = current_tick;
|
2004-10-03 23:32:09 +00:00
|
|
|
}
|
|
|
|
}
|
2004-09-29 00:50:40 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
deselect_card();
|
2004-10-03 23:32:09 +00:00
|
|
|
mutex_unlock(&mmc_mutex);
|
|
|
|
|
2004-10-04 22:29:06 +00:00
|
|
|
/* only flush if writing went ok */
|
|
|
|
if ( (ret == 0) && delayed_write )
|
|
|
|
ata_flush();
|
|
|
|
|
2004-09-11 03:48:05 +00:00
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
2004-10-04 22:29:06 +00:00
|
|
|
/* While there is no spinup, the delayed write is still here to avoid
|
|
|
|
wearing the flash unnecessarily */
|
2004-09-11 03:48:05 +00:00
|
|
|
extern void ata_delayed_write(unsigned long sector, const void* buf)
|
|
|
|
{
|
2004-10-04 22:29:06 +00:00
|
|
|
memcpy(delayed_sector, buf, SECTOR_SIZE);
|
|
|
|
delayed_sector_num = sector;
|
|
|
|
delayed_write = true;
|
2004-09-11 03:48:05 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
extern void ata_flush(void)
|
|
|
|
{
|
2004-10-04 22:29:06 +00:00
|
|
|
if ( delayed_write ) {
|
|
|
|
DEBUGF("ata_flush()\n");
|
|
|
|
delayed_write = false;
|
|
|
|
ata_write_sectors(delayed_sector_num, 1, delayed_sector);
|
|
|
|
}
|
2004-09-11 03:48:05 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
void ata_spindown(int seconds)
|
|
|
|
{
|
2004-09-28 06:23:57 +00:00
|
|
|
(void)seconds;
|
2004-09-11 03:48:05 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
bool ata_disk_is_active(void)
|
2004-10-09 22:48:10 +00:00
|
|
|
{
|
2004-10-03 23:32:09 +00:00
|
|
|
/* this is correct unless early return from write gets implemented */
|
|
|
|
return mmc_mutex.locked;
|
2004-09-11 03:48:05 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
int ata_standby(int time)
|
|
|
|
{
|
|
|
|
(void)time;
|
|
|
|
|
2004-10-01 21:41:44 +00:00
|
|
|
return 0;
|
2004-09-11 03:48:05 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
int ata_sleep(void)
|
|
|
|
{
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
void ata_spin(void)
|
|
|
|
{
|
|
|
|
}
|
|
|
|
|
2004-10-10 19:51:11 +00:00
|
|
|
bool mmc_detect(void)
|
2004-09-11 03:48:05 +00:00
|
|
|
{
|
2004-10-10 00:35:19 +00:00
|
|
|
return adc_read(ADC_MMC_SWITCH) < 0x200 ? true : false;
|
|
|
|
}
|
2004-09-28 06:23:57 +00:00
|
|
|
|
2004-10-10 00:35:19 +00:00
|
|
|
static void mmc_tick(void)
|
|
|
|
{
|
|
|
|
bool current_status;
|
2004-09-11 03:48:05 +00:00
|
|
|
|
2004-10-10 00:35:19 +00:00
|
|
|
current_status = mmc_detect();
|
|
|
|
|
|
|
|
/* Only report when the status has changed */
|
|
|
|
if (current_status != last_mmc_status)
|
|
|
|
{
|
|
|
|
last_mmc_status = current_status;
|
|
|
|
countdown = 30;
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* Count down until it gets negative */
|
|
|
|
if (countdown >= 0)
|
|
|
|
countdown--;
|
|
|
|
|
|
|
|
if (countdown == 0)
|
|
|
|
{
|
|
|
|
if (current_status)
|
|
|
|
{
|
|
|
|
queue_broadcast(SYS_MMC_INSERTED, NULL);
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
queue_broadcast(SYS_MMC_EXTRACTED, NULL);
|
|
|
|
card_info[1].initialized = false;
|
|
|
|
}
|
2004-09-11 03:48:05 +00:00
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
int ata_soft_reset(void)
|
|
|
|
{
|
2004-10-09 01:14:55 +00:00
|
|
|
return 0;
|
2004-09-11 03:48:05 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
void ata_enable(bool on)
|
|
|
|
{
|
2004-09-28 06:23:57 +00:00
|
|
|
PBCR1 &= ~0x0CF0; /* PB13, PB11 and PB10 become GPIOs, if not modified below */
|
2004-10-01 16:57:54 +00:00
|
|
|
PACR2 &= ~0x4000; /* use PA7 (bridge reset) as GPIO */
|
2004-09-11 15:18:10 +00:00
|
|
|
if (on)
|
|
|
|
{
|
2004-09-28 06:23:57 +00:00
|
|
|
PBCR1 |= 0x08A0; /* as SCK1, TxD1, RxD1 */
|
2004-09-29 00:50:40 +00:00
|
|
|
IPRE &= 0x0FFF; /* disable SCI1 interrupts for the CPU */
|
2004-09-11 15:18:10 +00:00
|
|
|
}
|
2004-09-29 00:50:40 +00:00
|
|
|
and_b(~0x80, &PADRL); /* assert reset */
|
|
|
|
sleep(HZ/20);
|
|
|
|
or_b(0x80, &PADRL); /* de-assert reset */
|
|
|
|
sleep(HZ/20);
|
|
|
|
card_info[0].initialized = false;
|
|
|
|
card_info[1].initialized = false;
|
2004-09-11 03:48:05 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
int ata_init(void)
|
|
|
|
{
|
|
|
|
int rc = 0;
|
|
|
|
|
2004-10-03 23:32:09 +00:00
|
|
|
mutex_init(&mmc_mutex);
|
2004-09-11 03:48:05 +00:00
|
|
|
|
|
|
|
led(false);
|
|
|
|
|
2004-09-11 09:06:58 +00:00
|
|
|
/* Port setup */
|
2004-10-01 16:57:54 +00:00
|
|
|
PACR1 &= ~0x0F00; /* GPIO function for PA12, /IRQ1 for PA13 */
|
|
|
|
PACR1 |= 0x0400;
|
2004-09-28 06:23:57 +00:00
|
|
|
PADR |= 0x0680; /* set all the selects + reset high (=inactive) */
|
|
|
|
PAIOR |= 0x1680; /* make outputs for them and the PA12 clock gate */
|
|
|
|
|
|
|
|
PBDR |= 0x2C00; /* SCK1, TxD1 and RxD1 high when GPIO CHECKME: mask */
|
|
|
|
PBIOR |= 0x2000; /* SCK1 output */
|
|
|
|
PBIOR &= ~0x0C00; /* TxD1, RxD1 input */
|
2004-09-11 09:06:58 +00:00
|
|
|
|
2004-10-10 00:35:19 +00:00
|
|
|
last_mmc_status = mmc_detect();
|
|
|
|
if (last_mmc_status)
|
2004-09-11 09:06:58 +00:00
|
|
|
{ /* MMC inserted */
|
2004-09-28 06:23:57 +00:00
|
|
|
current_card = 1;
|
2004-09-11 09:06:58 +00:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{ /* no MMC, use internal memory */
|
2004-09-28 06:23:57 +00:00
|
|
|
current_card = 0;
|
2004-09-11 09:06:58 +00:00
|
|
|
}
|
2004-09-11 03:48:05 +00:00
|
|
|
|
|
|
|
ata_enable(true);
|
2004-10-09 01:14:55 +00:00
|
|
|
|
2004-10-10 00:35:19 +00:00
|
|
|
if ( !initialized )
|
|
|
|
{
|
|
|
|
tick_add_task(mmc_tick);
|
2004-09-11 03:48:05 +00:00
|
|
|
initialized = true;
|
|
|
|
}
|
|
|
|
|
|
|
|
return rc;
|
|
|
|
}
|
|
|
|
|