2004-09-11 03:48:05 +00:00
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/***************************************************************************
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* __________ __ ___.
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* Open \______ \ ____ ____ | | _\_ |__ _______ ___
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* Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
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* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
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* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
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* \/ \/ \/ \/ \/
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* $Id$
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*
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2004-09-28 06:23:57 +00:00
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* Copyright (C) 2004 by Jens Arnold
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2004-09-11 03:48:05 +00:00
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*
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* All files in this archive are subject to the GNU General Public License.
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* See the file COPYING in the source tree root for full license agreement.
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*
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* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
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* KIND, either express or implied.
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*
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****************************************************************************/
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#include <stdbool.h>
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#include "ata.h"
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#include "kernel.h"
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#include "thread.h"
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#include "led.h"
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#include "sh7034.h"
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#include "system.h"
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#include "debug.h"
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#include "panic.h"
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#include "usb.h"
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#include "power.h"
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#include "string.h"
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#include "hwcompat.h"
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2004-09-11 09:06:58 +00:00
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#include "adc.h"
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2004-09-11 03:48:05 +00:00
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2004-09-28 06:23:57 +00:00
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#include "bitswap.h"
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2004-09-11 03:48:05 +00:00
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/* use file for an MMC-based system, FIXME in makefile */
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2004-09-28 06:23:57 +00:00
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#ifdef HAVE_MMC
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2004-09-11 03:48:05 +00:00
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#define SECTOR_SIZE 512
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2004-09-28 06:23:57 +00:00
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/* Command definitions */
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#define CMD_GO_IDLE_STATE 0x40 /* R1 */
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#define CMD_SEND_OP_COND 0x41 /* R1 */
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#define CMD_SEND_CSD 0x49 /* R1 */
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2004-10-03 23:32:09 +00:00
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#define CMD_SEND_CID 0x4a /* R1 */
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#define CMD_STOP_TRANSMISSION 0x4c /* R1 */
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#define CMD_SEND_STATUS 0x4d /* R2 */
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2004-09-28 06:23:57 +00:00
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#define CMD_READ_SINGLE_BLOCK 0x51 /* R1 */
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#define CMD_READ_MULTIPLE_BLOCK 0x52 /* R1 */
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#define CMD_WRITE_BLOCK 0x58 /* R1b */
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#define CMD_WRITE_MULTIPLE_BLOCK 0x59 /* R1b */
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2004-10-03 23:32:09 +00:00
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#define CMD_READ_OCR 0x7a /* R3 */
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2004-09-28 06:23:57 +00:00
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/* Response formats:
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R1 = single byte, msb=0, various error flags
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R1b = R1 + busy token(s)
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R2 = 2 bytes (1st byte identical to R1), additional flags
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R3 = 5 bytes (R1 + OCR register)
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*/
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#define R1_PARAMETER_ERR 0x40
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#define R1_ADDRESS_ERR 0x20
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#define R1_ERASE_SEQ_ERR 0x10
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#define R1_COM_CRC_ERR 0x08
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#define R1_ILLEGAL_CMD 0x04
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#define R1_ERASE_RESET 0x02
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#define R1_IN_IDLE_STATE 0x01
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#define R2_OUT_OF_RANGE 0x80
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#define R2_ERASE_PARAM 0x40
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#define R2_WP_VIOLATION 0x20
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#define R2_CARD_ECC_FAIL 0x10
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#define R2_CC_ERROR 0x08
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#define R2_ERROR 0x04
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#define R2_ERASE_SKIP 0x02
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#define R2_CARD_LOCKED 0x01
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2004-10-03 23:32:09 +00:00
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/* Data start tokens */
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#define DT_START_BLOCK 0xfe
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#define DT_START_WRITE_MULTIPLE 0xfc
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#define DT_STOP_TRAN 0xfd
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2004-09-28 06:23:57 +00:00
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// DEBUG
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#include "../../apps/screens.h"
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2004-09-11 03:48:05 +00:00
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/* for compatibility */
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bool old_recorder = false; /* FIXME: get rid of this cross-dependency */
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int ata_spinup_time = 0;
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char ata_device = 0; /* device 0 (master) or 1 (slave) */
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int ata_io_address = 0; /* 0x300 or 0x200, only valid on recorder */
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2004-09-28 06:23:57 +00:00
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long last_disk_activity = -1;
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2004-09-11 03:48:05 +00:00
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2004-09-28 06:23:57 +00:00
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/* private variables */
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2004-09-11 03:48:05 +00:00
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2004-10-03 23:32:09 +00:00
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static struct mutex mmc_mutex;
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2004-09-11 03:48:05 +00:00
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2004-09-28 06:23:57 +00:00
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static char mmc_stack[DEFAULT_STACK_SIZE];
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static const char mmc_thread_name[] = "mmc";
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static struct event_queue mmc_queue;
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2004-09-11 03:48:05 +00:00
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static bool initialized = false;
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2004-09-28 06:23:57 +00:00
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static int current_card = 0;
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static const unsigned char dummy[] = {
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0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF
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};
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typedef struct
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{
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bool initialized;
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unsigned char bitrate_register;
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unsigned char rev;
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unsigned char rev_fract;
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unsigned int speed; /* bps */
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unsigned int read_timeout; /* n * 8 clock cycles */
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unsigned int write_timeout; /* n * 8 clock cycles */
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unsigned int size; /* in bytes */
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unsigned int manuf_month;
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unsigned int manuf_year;
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unsigned long serial_number;
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unsigned char name[7];
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} tCardInfo;
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static tCardInfo card_info[2];
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/* private function declarations */
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static int select_card(int card_no);
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static void deselect_card(void);
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static void setup_sci1(int bitrate_register);
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static void write_transfer(const unsigned char *buf, int len)
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__attribute__ ((section(".icode")));
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static void read_transfer(unsigned char *buf, int len)
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__attribute__ ((section(".icode")));
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static unsigned char poll_byte(int timeout);
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2004-10-03 23:32:09 +00:00
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static unsigned char poll_busy(int timeout);
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2004-09-28 06:23:57 +00:00
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static int send_cmd(int cmd, unsigned long parameter, unsigned char *response);
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static int receive_data(unsigned char *buf, int len, int timeout);
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2004-10-03 23:32:09 +00:00
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static int send_data(char start_token, const unsigned char *buf, int len,
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int timeout);
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2004-09-28 06:23:57 +00:00
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static int initialize_card(int card_no);
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/* implementation */
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static int select_card(int card_no)
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{
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2004-10-01 17:01:40 +00:00
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if (card_no == 0) /* internal */
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or_b(0x10, &PADRH); /* set clock gate PA12 CHECKME: mask? */
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else /* external */
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and_b(~0x10, &PADRH); /* clear clock gate PA12 CHECKME: mask?*/
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2004-09-29 00:50:40 +00:00
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if (!card_info[card_no].initialized)
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{
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2004-09-29 01:10:32 +00:00
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setup_sci1(7); /* Initial rate: 375 kbps (need <= 400 per mmc specs) */
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2004-09-29 00:50:40 +00:00
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write_transfer(dummy, 10); /* allow the card to synchronize */
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while (!(SSR1 & SCI_TEND));
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}
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2004-10-01 17:01:40 +00:00
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if (card_no == 0) /* internal */
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2004-09-28 06:23:57 +00:00
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and_b(~0x04, &PADRH); /* assert CS */
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2004-10-01 17:01:40 +00:00
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else /* external */
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2004-09-28 06:23:57 +00:00
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and_b(~0x02, &PADRH); /* assert CS */
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2004-09-11 03:48:05 +00:00
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2004-09-28 06:23:57 +00:00
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if (card_info[card_no].initialized)
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{
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setup_sci1(card_info[card_no].bitrate_register);
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return 0;
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}
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else
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{
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return initialize_card(card_no);
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}
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}
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static void deselect_card(void)
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{
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2004-09-29 00:50:40 +00:00
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while (!(SSR1 & SCI_TEND)); /* wait for end of transfer */
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2004-09-28 06:23:57 +00:00
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or_b(0x06, &PADRH); /* deassert CS (both cards) */
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}
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static void setup_sci1(int bitrate_register)
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{
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int i;
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2004-09-29 00:50:40 +00:00
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while (!(SSR1 & SCI_TEND)); /* wait for end of transfer */
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2004-09-28 06:23:57 +00:00
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SCR1 = 0; /* disable serial port */
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SMR1 = SYNC_MODE; /* no prescale */
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BRR1 = bitrate_register;
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SCR1 = SCI_CKE0;
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SSR1 = 0;
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for (i = 0; i <= bitrate_register; i++); /* wait at least one bit time */
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or_b((SCI_TE|SCI_RE), &SCR1); /* enable transmitter & receiver */
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}
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static void write_transfer(const unsigned char *buf, int len)
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{
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const unsigned char *buf_end = buf + len;
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/* TODO: DMA */
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2004-09-29 00:50:40 +00:00
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2004-09-28 06:23:57 +00:00
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while (buf < buf_end)
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{
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2004-09-29 00:50:40 +00:00
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while (!(SSR1 & SCI_TEND)); /* wait for end of transfer */
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2004-09-28 06:23:57 +00:00
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TDR1 = fliptable[(signed char)(*buf++)]; /* write byte */
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SSR1 = 0; /* start transmitting */
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}
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}
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static void read_transfer(unsigned char *buf, int len)
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{
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unsigned char *buf_end = buf + len;
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/* TODO: DMA */
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2004-09-29 00:50:40 +00:00
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while (!(SSR1 & SCI_TEND)); /* wait for end of transfer */
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2004-09-28 06:23:57 +00:00
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TDR1 = 0xFF; /* send do-nothing data in parallel */
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while (buf < buf_end)
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{
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SSR1 = 0; /* start receiving */
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while (!(SSR1 & SCI_RDRF)); /* wait for data */
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*buf++ = fliptable[(signed char)(RDR1)]; /* read byte */
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}
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}
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/* timeout is in bytes */
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static unsigned char poll_byte(int timeout)
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{
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int i;
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unsigned char data = 0; /* stop the compiler complaining */
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2004-09-29 00:50:40 +00:00
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while (!(SSR1 & SCI_TEND)); /* wait for end of transfer */
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2004-09-28 06:23:57 +00:00
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TDR1 = 0xFF; /* send do-nothing data in parallel */
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i = 0;
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do {
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SSR1 = 0; /* start receiving */
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while (!(SSR1 & SCI_RDRF)); /* wait for data */
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data = RDR1; /* read byte */
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} while ((data == 0xFF) && (++i < timeout));
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return fliptable[(signed char)data];
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}
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2004-09-11 03:48:05 +00:00
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2004-09-29 00:50:40 +00:00
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static unsigned char poll_busy(int timeout)
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{
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int i;
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2004-09-29 22:44:02 +00:00
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unsigned char data, dummy;
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2004-09-29 00:50:40 +00:00
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while (!(SSR1 &SCI_TEND)); /* wait for end of transfer */
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TDR1 = 0xFF; /* send do-nothing data in parallel */
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2004-09-29 22:44:02 +00:00
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/* get data response */
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SSR1 = 0; /* start receiving */
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while (!(SSR1 & SCI_RDRF)); /* wait for data */
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data = RDR1; /* read byte */
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/* wait until the card is ready again */
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2004-09-29 00:50:40 +00:00
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i = 0;
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do {
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SSR1 = 0; /* start receiving */
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while (!(SSR1 & SCI_RDRF)); /* wait for data */
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2004-09-29 22:44:02 +00:00
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dummy = RDR1; /* read byte */
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} while ((dummy != 0xFF) && (++i < timeout));
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2004-09-29 00:50:40 +00:00
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return fliptable[(signed char)data];
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}
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2004-09-28 06:23:57 +00:00
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static int send_cmd(int cmd, unsigned long parameter, unsigned char *response)
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{
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2004-10-03 23:32:09 +00:00
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unsigned char command[] = {0x40, 0x00, 0x00, 0x00, 0x00, 0x95, 0xFF};
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2004-09-28 06:23:57 +00:00
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command[0] = cmd;
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if (parameter != 0)
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{
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command[1] = (parameter >> 24) & 0xFF;
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command[2] = (parameter >> 16) & 0xFF;
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command[3] = (parameter >> 8) & 0xFF;
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command[4] = parameter & 0xFF;
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}
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2004-10-03 23:32:09 +00:00
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write_transfer(command, 7);
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2004-09-28 06:23:57 +00:00
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2004-09-29 00:50:40 +00:00
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response[0] = poll_byte(20);
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2004-09-28 06:23:57 +00:00
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if (response[0] != 0x00)
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{
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write_transfer(dummy, 1);
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return -1;
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}
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switch (cmd)
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{
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case CMD_SEND_CSD: /* R1 response, leave open */
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case CMD_SEND_CID:
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case CMD_READ_SINGLE_BLOCK:
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2004-10-03 23:32:09 +00:00
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case CMD_READ_MULTIPLE_BLOCK:
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2004-09-28 06:23:57 +00:00
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break;
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case CMD_SEND_STATUS: /* R2 response, close with dummy */
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read_transfer(response + 1, 1);
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write_transfer(dummy, 1);
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break;
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case CMD_READ_OCR: /* R3 response, close with dummy */
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read_transfer(response + 1, 4);
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write_transfer(dummy, 1);
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break;
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default: /* R1 response, close with dummy */
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write_transfer(dummy, 1);
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break; /* also catches block writes */
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}
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return 0;
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}
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static int receive_data(unsigned char *buf, int len, int timeout)
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{
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unsigned char crc[2]; /* unused */
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|
2004-10-03 23:32:09 +00:00
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if (poll_byte(timeout) != DT_START_BLOCK)
|
2004-09-28 06:23:57 +00:00
|
|
|
{
|
|
|
|
write_transfer(dummy, 1);
|
|
|
|
return -1; /* not start of data */
|
|
|
|
}
|
|
|
|
|
|
|
|
read_transfer(buf, len);
|
|
|
|
read_transfer(crc, 2); /* throw away */
|
|
|
|
write_transfer(dummy, 1);
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2004-10-03 23:32:09 +00:00
|
|
|
static int send_data(char start_token, const unsigned char *buf, int len,
|
|
|
|
int timeout)
|
2004-09-29 00:50:40 +00:00
|
|
|
{
|
|
|
|
int ret = 0;
|
|
|
|
|
2004-10-03 23:32:09 +00:00
|
|
|
write_transfer(&start_token, 1);
|
2004-09-29 00:50:40 +00:00
|
|
|
write_transfer(buf, len);
|
|
|
|
write_transfer(dummy, 2); /* crc - dontcare */
|
|
|
|
|
|
|
|
if ((poll_busy(timeout) & 0x1F) != 0x05) /* something went wrong */
|
|
|
|
ret = -1;
|
|
|
|
|
|
|
|
write_transfer(dummy, 1);
|
|
|
|
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
2004-09-28 06:23:57 +00:00
|
|
|
static int initialize_card(int card_no)
|
|
|
|
{
|
|
|
|
int i, temp;
|
|
|
|
unsigned char response;
|
|
|
|
unsigned char cxd[16];
|
|
|
|
tCardInfo *card = &card_info[card_no];
|
|
|
|
|
|
|
|
static const char mantissa[] = { /* *10 */
|
|
|
|
0, 10, 12, 13, 15, 20, 25, 30,
|
|
|
|
35, 40, 45, 50, 55, 60, 70, 80
|
|
|
|
};
|
|
|
|
static const int speed_exponent[] = { /* /10 */
|
|
|
|
10000, 100000, 1000000, 10000000, 0, 0, 0, 0
|
|
|
|
};
|
|
|
|
|
|
|
|
static const int time_exponent[] = { /* reciprocal */
|
|
|
|
1000000000, 100000000, 10000000, 1000000, 100000, 10000, 1000, 100
|
|
|
|
};
|
|
|
|
|
|
|
|
/* switch to SPI mode */
|
|
|
|
send_cmd(CMD_GO_IDLE_STATE, 0, &response);
|
|
|
|
if (response != 0x01)
|
|
|
|
return -1; /* error response */
|
|
|
|
|
|
|
|
/* initialize card */
|
|
|
|
i = 0;
|
2004-09-29 00:50:40 +00:00
|
|
|
while (send_cmd(CMD_SEND_OP_COND, 0, &response) && (++i < 200));
|
2004-09-28 06:23:57 +00:00
|
|
|
if (response != 0x00)
|
|
|
|
return -2; /* not ready */
|
|
|
|
|
|
|
|
/* get CSD register */
|
|
|
|
if (send_cmd(CMD_SEND_CSD, 0, &response))
|
|
|
|
return -3;
|
|
|
|
if (receive_data(cxd, 16, 50))
|
|
|
|
return -4;
|
|
|
|
|
|
|
|
/* check block size */
|
|
|
|
if (1 << (cxd[5] & 0x0F) != SECTOR_SIZE)
|
|
|
|
return -5;
|
|
|
|
|
|
|
|
/* max transmission speed the card is capable of */
|
|
|
|
card->speed = mantissa[(cxd[3] & 0x78) >> 3]
|
|
|
|
* speed_exponent[(cxd[3] & 0x07)];
|
|
|
|
|
|
|
|
/* calculate the clock divider */
|
|
|
|
card->bitrate_register = (FREQ/4-1) / card->speed;
|
|
|
|
|
|
|
|
/* calculate read timeout in clock cycles from TSAC, NSAC and the actual
|
|
|
|
* clock frequency */
|
|
|
|
temp = (FREQ/4) / (card->bitrate_register + 1); /* actual frequency */
|
|
|
|
card->read_timeout =
|
|
|
|
(temp * mantissa[(cxd[1] & 0x78) >> 3] + (1000 * cxd[2]))
|
|
|
|
/ (time_exponent[cxd[1] & 0x07] * 8);
|
|
|
|
|
|
|
|
/* calculate write timeout */
|
|
|
|
temp = (cxd[12] & 0x1C) >> 2;
|
|
|
|
if (temp > 5)
|
|
|
|
temp = 5;
|
|
|
|
card->write_timeout = card->read_timeout * (1 << temp);
|
|
|
|
|
|
|
|
/* calculate size */
|
|
|
|
card->size = ((unsigned int)(cxd[6] & 0x03) << 10)
|
|
|
|
+ ((unsigned int)cxd[7] << 2)
|
|
|
|
+ ((unsigned int)(cxd[8] & 0xC0) >> 6);
|
|
|
|
temp = ((cxd[9] & 0x03) << 1) + ((cxd[10] & 0x80) >> 7) + 2;
|
|
|
|
card->size *= (SECTOR_SIZE << temp);
|
|
|
|
|
|
|
|
/* switch to full speed */
|
|
|
|
setup_sci1(card->bitrate_register);
|
|
|
|
|
|
|
|
/* get CID register */
|
|
|
|
if (send_cmd(CMD_SEND_CID, 0, &response))
|
|
|
|
return -6;
|
|
|
|
if (receive_data(cxd, 16, 50))
|
|
|
|
return -7;
|
|
|
|
|
|
|
|
/* get data from CID */
|
|
|
|
strncpy(card->name, &cxd[3], 6);
|
|
|
|
card->name[6] = '\0';
|
|
|
|
|
|
|
|
card->rev = (cxd[9] & 0xF0) >> 4;
|
|
|
|
card->rev_fract = cxd[9] & 0x0F;
|
2004-09-29 01:10:32 +00:00
|
|
|
|
2004-09-28 06:23:57 +00:00
|
|
|
card->manuf_month = (cxd[14] & 0xF0) >> 4;
|
|
|
|
card->manuf_year = (cxd[14] & 0x0F) + 1997;
|
|
|
|
|
|
|
|
card->serial_number = ((unsigned long)cxd[10] << 24)
|
|
|
|
+ ((unsigned long)cxd[11] << 16)
|
|
|
|
+ ((unsigned long)cxd[12] << 8)
|
|
|
|
+ (unsigned long)cxd[13];
|
|
|
|
|
|
|
|
card->initialized = true;
|
|
|
|
return 0;
|
|
|
|
}
|
2004-09-11 03:48:05 +00:00
|
|
|
|
2004-10-03 23:32:09 +00:00
|
|
|
int ata_read_sectors(unsigned long start,
|
|
|
|
int incount,
|
|
|
|
void* inbuf)
|
|
|
|
{
|
|
|
|
int ret = 0;
|
|
|
|
int i;
|
|
|
|
unsigned long addr;
|
|
|
|
unsigned char response;
|
|
|
|
tCardInfo *card = &card_info[current_card];
|
|
|
|
|
|
|
|
if (incount <= 0)
|
|
|
|
return ret;
|
|
|
|
|
|
|
|
addr = start * SECTOR_SIZE;
|
|
|
|
|
|
|
|
mutex_lock(&mmc_mutex);
|
|
|
|
ret = select_card(current_card);
|
|
|
|
|
|
|
|
if (ret == 0)
|
|
|
|
{
|
|
|
|
if (incount == 1)
|
|
|
|
{
|
|
|
|
ret = send_cmd(CMD_READ_SINGLE_BLOCK, addr, &response);
|
|
|
|
if (ret == 0)
|
|
|
|
ret = receive_data(inbuf, SECTOR_SIZE, card->read_timeout);
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
ret = send_cmd(CMD_READ_MULTIPLE_BLOCK, addr, &response);
|
|
|
|
for (i = 0; (i < incount) && (ret == 0); i++)
|
|
|
|
{
|
|
|
|
ret = receive_data(inbuf, SECTOR_SIZE, card->read_timeout);
|
|
|
|
inbuf += SECTOR_SIZE;
|
|
|
|
}
|
|
|
|
if (ret == 0)
|
|
|
|
ret = send_cmd(CMD_STOP_TRANSMISSION, 0, &response);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
deselect_card();
|
|
|
|
mutex_unlock(&mmc_mutex);
|
2004-09-11 03:48:05 +00:00
|
|
|
|
2004-10-03 23:32:09 +00:00
|
|
|
return ret;
|
|
|
|
}
|
2004-09-11 03:48:05 +00:00
|
|
|
|
|
|
|
int ata_write_sectors(unsigned long start,
|
|
|
|
int count,
|
|
|
|
const void* buf)
|
|
|
|
{
|
|
|
|
int ret = 0;
|
2004-09-29 00:50:40 +00:00
|
|
|
int i;
|
|
|
|
unsigned long addr;
|
|
|
|
unsigned char response;
|
|
|
|
tCardInfo *card = &card_info[current_card];
|
2004-09-11 03:48:05 +00:00
|
|
|
|
|
|
|
if (start == 0)
|
|
|
|
panicf("Writing on sector 0\n");
|
|
|
|
|
2004-10-03 23:32:09 +00:00
|
|
|
if (count <= 0)
|
|
|
|
return ret;
|
2004-09-29 00:50:40 +00:00
|
|
|
|
2004-10-03 23:32:09 +00:00
|
|
|
addr = start * SECTOR_SIZE;
|
|
|
|
|
|
|
|
mutex_lock(&mmc_mutex);
|
2004-09-29 00:50:40 +00:00
|
|
|
ret = select_card(current_card);
|
2004-09-11 03:48:05 +00:00
|
|
|
|
2004-10-03 23:32:09 +00:00
|
|
|
if (ret == 0)
|
2004-09-29 00:50:40 +00:00
|
|
|
{
|
2004-10-03 23:32:09 +00:00
|
|
|
if (count == 1)
|
|
|
|
{
|
|
|
|
ret = send_cmd(CMD_WRITE_BLOCK, addr, &response);
|
|
|
|
if (ret == 0)
|
|
|
|
ret = send_data(DT_START_BLOCK, buf, SECTOR_SIZE,
|
|
|
|
card->write_timeout);
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
ret = send_cmd(CMD_WRITE_MULTIPLE_BLOCK, addr, &response);
|
|
|
|
for (i = 0; (i < count) && (ret == 0); i++)
|
|
|
|
{
|
|
|
|
ret = send_data(DT_START_WRITE_MULTIPLE, buf, SECTOR_SIZE,
|
|
|
|
card->write_timeout);
|
|
|
|
buf += SECTOR_SIZE;
|
|
|
|
}
|
|
|
|
if (ret == 0)
|
|
|
|
{
|
|
|
|
response = DT_STOP_TRAN;
|
|
|
|
write_transfer(&response, 1);
|
|
|
|
poll_busy(card->write_timeout);
|
|
|
|
}
|
|
|
|
}
|
2004-09-29 00:50:40 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
deselect_card();
|
2004-10-03 23:32:09 +00:00
|
|
|
mutex_unlock(&mmc_mutex);
|
|
|
|
|
2004-09-11 03:48:05 +00:00
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
2004-09-28 06:23:57 +00:00
|
|
|
/* no need to delay with flash memory. There is no spinup :) */
|
2004-09-11 03:48:05 +00:00
|
|
|
extern void ata_delayed_write(unsigned long sector, const void* buf)
|
|
|
|
{
|
2004-09-28 06:23:57 +00:00
|
|
|
ata_write_sectors(sector, 1, buf);
|
2004-09-11 03:48:05 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
extern void ata_flush(void)
|
|
|
|
{
|
|
|
|
}
|
|
|
|
|
|
|
|
void ata_spindown(int seconds)
|
|
|
|
{
|
2004-09-28 06:23:57 +00:00
|
|
|
(void)seconds;
|
2004-09-11 03:48:05 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
bool ata_disk_is_active(void)
|
2004-10-03 23:32:09 +00:00
|
|
|
{
|
|
|
|
/* this is correct unless early return from write gets implemented */
|
|
|
|
return mmc_mutex.locked;
|
2004-09-11 03:48:05 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
int ata_standby(int time)
|
|
|
|
{
|
|
|
|
(void)time;
|
|
|
|
|
2004-10-01 21:41:44 +00:00
|
|
|
return 0;
|
2004-09-11 03:48:05 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
int ata_sleep(void)
|
|
|
|
{
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
void ata_spin(void)
|
|
|
|
{
|
|
|
|
}
|
|
|
|
|
2004-09-28 06:23:57 +00:00
|
|
|
static void mmc_thread(void)
|
2004-09-11 03:48:05 +00:00
|
|
|
{
|
|
|
|
struct event ev;
|
2004-09-28 06:23:57 +00:00
|
|
|
|
2004-09-11 03:48:05 +00:00
|
|
|
while (1) {
|
2004-09-28 06:23:57 +00:00
|
|
|
while ( queue_empty( &mmc_queue ) ) {
|
2004-09-11 03:48:05 +00:00
|
|
|
|
|
|
|
sleep(HZ/4);
|
|
|
|
}
|
2004-09-28 06:23:57 +00:00
|
|
|
queue_wait(&mmc_queue, &ev);
|
2004-09-11 03:48:05 +00:00
|
|
|
switch ( ev.id ) {
|
|
|
|
#ifndef USB_NONE
|
|
|
|
case SYS_USB_CONNECTED:
|
|
|
|
/* Tell the USB thread that we are safe */
|
2004-09-28 06:23:57 +00:00
|
|
|
DEBUGF("mmc_thread got SYS_USB_CONNECTED\n");
|
2004-09-11 03:48:05 +00:00
|
|
|
usb_acknowledge(SYS_USB_CONNECTED_ACK);
|
|
|
|
|
|
|
|
/* Wait until the USB cable is extracted again */
|
2004-09-28 06:23:57 +00:00
|
|
|
usb_wait_for_disconnect(&mmc_queue);
|
2004-09-11 03:48:05 +00:00
|
|
|
break;
|
|
|
|
#endif
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
int ata_soft_reset(void)
|
|
|
|
{
|
|
|
|
int ret = 0;
|
|
|
|
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
void ata_enable(bool on)
|
|
|
|
{
|
2004-09-28 06:23:57 +00:00
|
|
|
PBCR1 &= ~0x0CF0; /* PB13, PB11 and PB10 become GPIOs, if not modified below */
|
2004-10-01 16:57:54 +00:00
|
|
|
PACR2 &= ~0x4000; /* use PA7 (bridge reset) as GPIO */
|
2004-09-11 15:18:10 +00:00
|
|
|
if (on)
|
|
|
|
{
|
2004-09-28 06:23:57 +00:00
|
|
|
PBCR1 |= 0x08A0; /* as SCK1, TxD1, RxD1 */
|
2004-09-29 00:50:40 +00:00
|
|
|
IPRE &= 0x0FFF; /* disable SCI1 interrupts for the CPU */
|
2004-09-11 15:18:10 +00:00
|
|
|
}
|
2004-09-29 00:50:40 +00:00
|
|
|
and_b(~0x80, &PADRL); /* assert reset */
|
|
|
|
sleep(HZ/20);
|
|
|
|
or_b(0x80, &PADRL); /* de-assert reset */
|
|
|
|
sleep(HZ/20);
|
|
|
|
card_info[0].initialized = false;
|
|
|
|
card_info[1].initialized = false;
|
2004-09-11 03:48:05 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
int ata_init(void)
|
|
|
|
{
|
|
|
|
int rc = 0;
|
|
|
|
|
2004-10-03 23:32:09 +00:00
|
|
|
mutex_init(&mmc_mutex);
|
2004-09-11 03:48:05 +00:00
|
|
|
|
|
|
|
led(false);
|
|
|
|
|
2004-09-11 09:06:58 +00:00
|
|
|
/* Port setup */
|
2004-10-01 16:57:54 +00:00
|
|
|
PACR1 &= ~0x0F00; /* GPIO function for PA12, /IRQ1 for PA13 */
|
|
|
|
PACR1 |= 0x0400;
|
2004-09-28 06:23:57 +00:00
|
|
|
PADR |= 0x0680; /* set all the selects + reset high (=inactive) */
|
|
|
|
PAIOR |= 0x1680; /* make outputs for them and the PA12 clock gate */
|
|
|
|
|
|
|
|
PBDR |= 0x2C00; /* SCK1, TxD1 and RxD1 high when GPIO CHECKME: mask */
|
|
|
|
PBIOR |= 0x2000; /* SCK1 output */
|
|
|
|
PBIOR &= ~0x0C00; /* TxD1, RxD1 input */
|
2004-09-11 09:06:58 +00:00
|
|
|
|
|
|
|
if(adc_read(ADC_MMC_SWITCH) < 0x200)
|
|
|
|
{ /* MMC inserted */
|
2004-09-28 06:23:57 +00:00
|
|
|
current_card = 1;
|
2004-09-11 09:06:58 +00:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{ /* no MMC, use internal memory */
|
2004-09-28 06:23:57 +00:00
|
|
|
current_card = 0;
|
2004-09-11 09:06:58 +00:00
|
|
|
}
|
2004-09-11 03:48:05 +00:00
|
|
|
|
|
|
|
ata_enable(true);
|
|
|
|
|
|
|
|
if ( !initialized ) {
|
|
|
|
|
2004-09-28 06:23:57 +00:00
|
|
|
queue_init(&mmc_queue);
|
2004-09-11 03:48:05 +00:00
|
|
|
|
2004-09-28 06:23:57 +00:00
|
|
|
create_thread(mmc_thread, mmc_stack,
|
|
|
|
sizeof(mmc_stack), mmc_thread_name);
|
2004-09-11 03:48:05 +00:00
|
|
|
initialized = true;
|
|
|
|
}
|
|
|
|
|
|
|
|
return rc;
|
|
|
|
}
|
|
|
|
|
|
|
|
#endif /* #ifdef HAVE_MMC */
|
2004-10-01 16:57:54 +00:00
|
|
|
|