2002-03-28 15:09:10 +00:00
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/***************************************************************************
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* __________ __ ___.
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* Open \______ \ ____ ____ | | _\_ |__ _______ ___
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* Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
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* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
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* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
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* \/ \/ \/ \/ \/
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* $Id$
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*
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* Copyright (C) 2002 by Alan Korr
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*
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* All files in this archive are subject to the GNU General Public License.
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* See the file COPYING in the source tree root for full license agreement.
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*
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* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
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* KIND, either express or implied.
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*
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****************************************************************************/
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2002-05-24 15:22:33 +00:00
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#include <stdio.h>
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2002-04-16 14:02:26 +00:00
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#include "config.h"
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2004-10-15 11:33:58 +00:00
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#include <stdbool.h>
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2004-11-02 22:24:30 +00:00
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#include "lcd.h"
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#include "font.h"
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2005-01-24 00:01:37 +00:00
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#include "system.h"
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2005-03-01 14:35:10 +00:00
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#include "kernel.h"
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2005-10-03 09:24:36 +00:00
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#include "timer.h"
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2006-08-05 20:19:10 +00:00
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#include "inttypes.h"
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#include "string.h"
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2005-03-01 14:35:10 +00:00
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#ifndef SIMULATOR
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long cpu_frequency = CPU_FREQ;
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#endif
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2002-04-16 14:02:26 +00:00
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2005-03-03 16:29:02 +00:00
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#ifdef HAVE_ADJUSTABLE_CPU_FREQ
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2006-10-05 10:07:03 +00:00
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static int boost_counter = 0;
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static bool cpu_idle = false;
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int get_cpu_boost_counter(void)
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{
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return boost_counter;
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}
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2006-12-05 20:01:48 +00:00
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void cpu_boost(bool on_off)
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2005-03-03 16:29:02 +00:00
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{
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if(on_off)
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{
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/* Boost the frequency if not already boosted */
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2005-03-07 10:51:43 +00:00
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if(boost_counter++ == 0)
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2005-03-03 16:29:02 +00:00
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set_cpu_frequency(CPUFREQ_MAX);
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}
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else
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{
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/* Lower the frequency if the counter reaches 0 */
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2005-03-07 10:51:43 +00:00
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if(--boost_counter == 0)
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2005-03-03 16:29:02 +00:00
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{
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2005-07-05 07:58:19 +00:00
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if(cpu_idle)
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set_cpu_frequency(CPUFREQ_DEFAULT);
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else
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set_cpu_frequency(CPUFREQ_NORMAL);
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2005-03-03 16:29:02 +00:00
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}
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/* Safety measure */
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2005-03-07 10:51:43 +00:00
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if(boost_counter < 0)
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boost_counter = 0;
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2005-03-03 16:29:02 +00:00
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}
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}
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2005-07-05 07:58:19 +00:00
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void cpu_idle_mode(bool on_off)
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{
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cpu_idle = on_off;
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/* We need to adjust the frequency immediately if the CPU
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isn't boosted */
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if(boost_counter == 0)
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{
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if(cpu_idle)
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set_cpu_frequency(CPUFREQ_DEFAULT);
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else
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set_cpu_frequency(CPUFREQ_NORMAL);
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}
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}
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2006-12-05 20:01:48 +00:00
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#endif /* HAVE_ADJUSTABLE_CPU_FREQ */
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2005-07-05 07:58:19 +00:00
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2006-08-12 08:01:54 +00:00
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#if CONFIG_CPU == S3C2440
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2005-03-03 16:29:02 +00:00
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2006-08-12 08:01:54 +00:00
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void system_reboot(void) {
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}
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2006-12-29 02:49:12 +00:00
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void system_init(void)
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{
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/* Turn off un-needed devices */
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/* Turn off all of the UARTS */
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CLKCON &= ~( (1<<10) | (1<<11) |(1<<12) );
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/* Turn off AC97 and Camera */
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CLKCON &= ~( (1<<19) | (1<<20) );
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2006-08-12 08:01:54 +00:00
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}
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#endif
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2006-11-08 18:33:06 +00:00
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2006-08-05 20:19:10 +00:00
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bool detect_flashed_rockbox(void)
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{
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2006-11-08 18:33:06 +00:00
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#ifdef HAVE_FLASHED_ROCKBOX
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2006-08-05 20:19:10 +00:00
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struct flash_header hdr;
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uint8_t *src = (uint8_t *)FLASH_ENTRYPOINT;
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2006-08-21 17:35:35 +00:00
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2006-11-08 18:33:06 +00:00
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#ifndef BOOTLOADER
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int oldmode = system_memory_guard(MEMGUARD_NONE);
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#endif
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2006-08-21 17:35:35 +00:00
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2006-08-05 20:19:10 +00:00
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memcpy(&hdr, src, sizeof(struct flash_header));
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2006-08-21 17:35:35 +00:00
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2006-11-08 18:33:06 +00:00
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#ifndef BOOTLOADER
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2006-08-11 10:13:16 +00:00
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system_memory_guard(oldmode);
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2006-11-08 18:33:06 +00:00
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#endif
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2006-08-21 17:35:35 +00:00
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2006-08-05 20:19:10 +00:00
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if (hdr.magic != FLASH_MAGIC)
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return false;
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2006-08-21 17:35:35 +00:00
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2006-08-05 20:19:10 +00:00
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return true;
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#else
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return false;
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2006-11-08 18:33:06 +00:00
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#endif /* HAVE_FLASHED_ROCKBOX */
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2006-08-05 20:19:10 +00:00
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}
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2006-11-10 20:26:01 +00:00
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#if CONFIG_CPU == SH7034
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2002-04-28 21:40:24 +00:00
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#include "led.h"
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2002-04-29 14:23:21 +00:00
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#include "system.h"
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2003-06-29 15:09:01 +00:00
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#include "rolo.h"
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2002-03-28 15:09:10 +00:00
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2004-07-20 21:37:36 +00:00
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static const char* const irqname[] = {
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2002-05-28 13:38:42 +00:00
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"", "", "", "", "IllInstr", "", "IllSltIn","","",
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"CPUAdrEr", "DMAAdrEr", "NMI", "UserBrk",
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"","","","","","","","","","","","","","","","","","","",
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"Trap32","Trap33","Trap34","Trap35","Trap36","Trap37","Trap38","Trap39",
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"Trap40","Trap41","Trap42","Trap43","Trap44","Trap45","Trap46","Trap47",
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"Trap48","Trap49","Trap50","Trap51","Trap52","Trap53","Trap54","Trap55",
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"Trap56","Trap57","Trap58","Trap59","Trap60","Trap61","Trap62","Trap63",
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"Irq0","Irq1","Irq2","Irq3","Irq4","Irq5","Irq6","Irq7",
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"Dma0","","Dma1","","Dma2","","Dma3","",
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"IMIA0","IMIB0","OVI0","", "IMIA1","IMIB1","OVI1","",
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"IMIA2","IMIB2","OVI2","", "IMIA3","IMIB3","OVI3","",
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"IMIA4","IMIB4","OVI4","",
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"Ser0Err","Ser0Rx","Ser0Tx","Ser0TE",
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"Ser1Err","Ser1Rx","Ser1Tx","Ser1TE",
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"ParityEr","A/D conv","","","Watchdog","DRAMRefr"
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};
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2006-04-29 12:42:55 +00:00
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#define RESERVE_INTERRUPT(number) "\t.long\t_UIE" #number "\n"
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#define DEFAULT_INTERRUPT(name, number) "\t.weak\t_" #name \
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"\n\t.set\t_" #name ",_UIE" #number \
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"\n\t.long\t_" #name "\n"
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2006-05-01 22:15:36 +00:00
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asm (
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2006-08-21 17:35:35 +00:00
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/* Vector table.
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2006-04-29 13:18:40 +00:00
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* Handled in asm because gcc 4.x doesn't allow weak aliases to symbols
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* defined in an asm block -- silly.
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* Reset vectors (0..3) are handled in crt0.S */
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2006-05-01 22:15:36 +00:00
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2006-04-29 12:42:55 +00:00
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".section\t.vectors,\"aw\",@progbits\n"
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DEFAULT_INTERRUPT (GII, 4)
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RESERVE_INTERRUPT ( 5)
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DEFAULT_INTERRUPT (ISI, 6)
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RESERVE_INTERRUPT ( 7)
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RESERVE_INTERRUPT ( 8)
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DEFAULT_INTERRUPT (CPUAE, 9)
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DEFAULT_INTERRUPT (DMAAE, 10)
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DEFAULT_INTERRUPT (NMI, 11)
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DEFAULT_INTERRUPT (UB, 12)
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RESERVE_INTERRUPT ( 13)
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RESERVE_INTERRUPT ( 14)
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RESERVE_INTERRUPT ( 15)
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RESERVE_INTERRUPT ( 16) /* TCB #0 */
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RESERVE_INTERRUPT ( 17) /* TCB #1 */
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RESERVE_INTERRUPT ( 18) /* TCB #2 */
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RESERVE_INTERRUPT ( 19) /* TCB #3 */
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RESERVE_INTERRUPT ( 20) /* TCB #4 */
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RESERVE_INTERRUPT ( 21) /* TCB #5 */
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RESERVE_INTERRUPT ( 22) /* TCB #6 */
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RESERVE_INTERRUPT ( 23) /* TCB #7 */
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RESERVE_INTERRUPT ( 24) /* TCB #8 */
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RESERVE_INTERRUPT ( 25) /* TCB #9 */
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RESERVE_INTERRUPT ( 26) /* TCB #10 */
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RESERVE_INTERRUPT ( 27) /* TCB #11 */
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RESERVE_INTERRUPT ( 28) /* TCB #12 */
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RESERVE_INTERRUPT ( 29) /* TCB #13 */
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RESERVE_INTERRUPT ( 30) /* TCB #14 */
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RESERVE_INTERRUPT ( 31) /* TCB #15 */
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DEFAULT_INTERRUPT (TRAPA32, 32)
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DEFAULT_INTERRUPT (TRAPA33, 33)
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DEFAULT_INTERRUPT (TRAPA34, 34)
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DEFAULT_INTERRUPT (TRAPA35, 35)
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DEFAULT_INTERRUPT (TRAPA36, 36)
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DEFAULT_INTERRUPT (TRAPA37, 37)
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DEFAULT_INTERRUPT (TRAPA38, 38)
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DEFAULT_INTERRUPT (TRAPA39, 39)
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DEFAULT_INTERRUPT (TRAPA40, 40)
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DEFAULT_INTERRUPT (TRAPA41, 41)
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DEFAULT_INTERRUPT (TRAPA42, 42)
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DEFAULT_INTERRUPT (TRAPA43, 43)
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DEFAULT_INTERRUPT (TRAPA44, 44)
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DEFAULT_INTERRUPT (TRAPA45, 45)
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DEFAULT_INTERRUPT (TRAPA46, 46)
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DEFAULT_INTERRUPT (TRAPA47, 47)
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DEFAULT_INTERRUPT (TRAPA48, 48)
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DEFAULT_INTERRUPT (TRAPA49, 49)
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DEFAULT_INTERRUPT (TRAPA50, 50)
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DEFAULT_INTERRUPT (TRAPA51, 51)
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DEFAULT_INTERRUPT (TRAPA52, 52)
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DEFAULT_INTERRUPT (TRAPA53, 53)
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DEFAULT_INTERRUPT (TRAPA54, 54)
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DEFAULT_INTERRUPT (TRAPA55, 55)
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DEFAULT_INTERRUPT (TRAPA56, 56)
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DEFAULT_INTERRUPT (TRAPA57, 57)
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DEFAULT_INTERRUPT (TRAPA58, 58)
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DEFAULT_INTERRUPT (TRAPA59, 59)
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DEFAULT_INTERRUPT (TRAPA60, 60)
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DEFAULT_INTERRUPT (TRAPA61, 61)
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DEFAULT_INTERRUPT (TRAPA62, 62)
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DEFAULT_INTERRUPT (TRAPA63, 63)
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DEFAULT_INTERRUPT (IRQ0, 64)
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DEFAULT_INTERRUPT (IRQ1, 65)
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DEFAULT_INTERRUPT (IRQ2, 66)
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DEFAULT_INTERRUPT (IRQ3, 67)
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DEFAULT_INTERRUPT (IRQ4, 68)
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DEFAULT_INTERRUPT (IRQ5, 69)
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DEFAULT_INTERRUPT (IRQ6, 70)
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DEFAULT_INTERRUPT (IRQ7, 71)
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DEFAULT_INTERRUPT (DEI0, 72)
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RESERVE_INTERRUPT ( 73)
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DEFAULT_INTERRUPT (DEI1, 74)
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RESERVE_INTERRUPT ( 75)
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DEFAULT_INTERRUPT (DEI2, 76)
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RESERVE_INTERRUPT ( 77)
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DEFAULT_INTERRUPT (DEI3, 78)
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RESERVE_INTERRUPT ( 79)
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DEFAULT_INTERRUPT (IMIA0, 80)
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DEFAULT_INTERRUPT (IMIB0, 81)
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DEFAULT_INTERRUPT (OVI0, 82)
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RESERVE_INTERRUPT ( 83)
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DEFAULT_INTERRUPT (IMIA1, 84)
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DEFAULT_INTERRUPT (IMIB1, 85)
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DEFAULT_INTERRUPT (OVI1, 86)
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RESERVE_INTERRUPT ( 87)
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DEFAULT_INTERRUPT (IMIA2, 88)
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DEFAULT_INTERRUPT (IMIB2, 89)
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DEFAULT_INTERRUPT (OVI2, 90)
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RESERVE_INTERRUPT ( 91)
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DEFAULT_INTERRUPT (IMIA3, 92)
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DEFAULT_INTERRUPT (IMIB3, 93)
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DEFAULT_INTERRUPT (OVI3, 94)
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RESERVE_INTERRUPT ( 95)
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DEFAULT_INTERRUPT (IMIA4, 96)
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DEFAULT_INTERRUPT (IMIB4, 97)
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DEFAULT_INTERRUPT (OVI4, 98)
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RESERVE_INTERRUPT ( 99)
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DEFAULT_INTERRUPT (REI0, 100)
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DEFAULT_INTERRUPT (RXI0, 101)
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DEFAULT_INTERRUPT (TXI0, 102)
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DEFAULT_INTERRUPT (TEI0, 103)
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DEFAULT_INTERRUPT (REI1, 104)
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DEFAULT_INTERRUPT (RXI1, 105)
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DEFAULT_INTERRUPT (TXI1, 106)
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DEFAULT_INTERRUPT (TEI1, 107)
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RESERVE_INTERRUPT ( 108)
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DEFAULT_INTERRUPT (ADITI, 109)
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2006-04-29 13:18:40 +00:00
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2006-08-21 17:35:35 +00:00
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/* UIE# block.
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2006-05-01 22:15:36 +00:00
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* Must go into the same section as the UIE() handler */
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"\t.text\n"
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2006-04-29 12:42:55 +00:00
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"_UIE4:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\n"
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"_UIE5:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\n"
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"_UIE6:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\n"
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|
|
"_UIE7:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\n"
|
|
|
|
|
"_UIE8:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\n"
|
|
|
|
|
"_UIE9:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\n"
|
|
|
|
|
"_UIE10:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\n"
|
|
|
|
|
"_UIE11:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\n"
|
|
|
|
|
"_UIE12:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\n"
|
|
|
|
|
"_UIE13:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\n"
|
|
|
|
|
"_UIE14:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\n"
|
|
|
|
|
"_UIE15:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\n"
|
|
|
|
|
"_UIE16:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\n"
|
|
|
|
|
"_UIE17:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\n"
|
|
|
|
|
"_UIE18:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\n"
|
|
|
|
|
"_UIE19:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\n"
|
|
|
|
|
"_UIE20:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\n"
|
|
|
|
|
"_UIE21:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\n"
|
|
|
|
|
"_UIE22:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\n"
|
|
|
|
|
"_UIE23:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\n"
|
|
|
|
|
"_UIE24:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\n"
|
|
|
|
|
"_UIE25:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\n"
|
|
|
|
|
"_UIE26:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\n"
|
|
|
|
|
"_UIE27:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\n"
|
|
|
|
|
"_UIE28:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\n"
|
|
|
|
|
"_UIE29:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\n"
|
|
|
|
|
"_UIE30:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\n"
|
|
|
|
|
"_UIE31:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\n"
|
|
|
|
|
"_UIE32:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\n"
|
|
|
|
|
"_UIE33:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\n"
|
|
|
|
|
"_UIE34:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\n"
|
|
|
|
|
"_UIE35:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\n"
|
|
|
|
|
"_UIE36:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\n"
|
|
|
|
|
"_UIE37:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\n"
|
|
|
|
|
"_UIE38:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\n"
|
|
|
|
|
"_UIE39:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\n"
|
|
|
|
|
"_UIE40:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\n"
|
|
|
|
|
"_UIE41:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\n"
|
|
|
|
|
"_UIE42:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\n"
|
|
|
|
|
"_UIE43:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\n"
|
|
|
|
|
"_UIE44:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\n"
|
|
|
|
|
"_UIE45:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\n"
|
|
|
|
|
"_UIE46:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\n"
|
|
|
|
|
"_UIE47:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\n"
|
|
|
|
|
"_UIE48:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\n"
|
|
|
|
|
"_UIE49:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\n"
|
|
|
|
|
"_UIE50:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\n"
|
|
|
|
|
"_UIE51:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\n"
|
|
|
|
|
"_UIE52:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\n"
|
|
|
|
|
"_UIE53:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\n"
|
|
|
|
|
"_UIE54:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\n"
|
|
|
|
|
"_UIE55:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\n"
|
|
|
|
|
"_UIE56:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\n"
|
|
|
|
|
"_UIE57:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\n"
|
|
|
|
|
"_UIE58:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\n"
|
|
|
|
|
"_UIE59:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\n"
|
|
|
|
|
"_UIE60:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\n"
|
|
|
|
|
"_UIE61:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\n"
|
|
|
|
|
"_UIE62:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\n"
|
|
|
|
|
"_UIE63:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\n"
|
|
|
|
|
"_UIE64:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\n"
|
|
|
|
|
"_UIE65:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\n"
|
|
|
|
|
"_UIE66:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\n"
|
|
|
|
|
"_UIE67:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\n"
|
|
|
|
|
"_UIE68:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\n"
|
|
|
|
|
"_UIE69:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\n"
|
|
|
|
|
"_UIE70:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\n"
|
|
|
|
|
"_UIE71:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\n"
|
|
|
|
|
"_UIE72:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\n"
|
|
|
|
|
"_UIE73:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\n"
|
|
|
|
|
"_UIE74:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\n"
|
|
|
|
|
"_UIE75:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\n"
|
|
|
|
|
"_UIE76:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\n"
|
|
|
|
|
"_UIE77:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\n"
|
|
|
|
|
"_UIE78:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\n"
|
|
|
|
|
"_UIE79:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\n"
|
|
|
|
|
"_UIE80:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\n"
|
|
|
|
|
"_UIE81:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\n"
|
|
|
|
|
"_UIE82:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\n"
|
|
|
|
|
"_UIE83:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\n"
|
|
|
|
|
"_UIE84:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\n"
|
|
|
|
|
"_UIE85:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\n"
|
|
|
|
|
"_UIE86:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\n"
|
|
|
|
|
"_UIE87:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\n"
|
|
|
|
|
"_UIE88:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\n"
|
|
|
|
|
"_UIE89:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\n"
|
|
|
|
|
"_UIE90:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\n"
|
|
|
|
|
"_UIE91:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\n"
|
|
|
|
|
"_UIE92:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\n"
|
|
|
|
|
"_UIE93:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\n"
|
|
|
|
|
"_UIE94:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\n"
|
|
|
|
|
"_UIE95:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\n"
|
|
|
|
|
"_UIE96:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\n"
|
|
|
|
|
"_UIE97:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\n"
|
|
|
|
|
"_UIE98:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\n"
|
|
|
|
|
"_UIE99:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\n"
|
|
|
|
|
"_UIE100:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\n"
|
|
|
|
|
"_UIE101:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\n"
|
|
|
|
|
"_UIE102:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\n"
|
|
|
|
|
"_UIE103:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\n"
|
|
|
|
|
"_UIE104:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\n"
|
|
|
|
|
"_UIE105:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\n"
|
|
|
|
|
"_UIE106:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\n"
|
|
|
|
|
"_UIE107:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\n"
|
|
|
|
|
"_UIE108:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\n"
|
|
|
|
|
"_UIE109:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\n"
|
2006-05-01 22:15:36 +00:00
|
|
|
|
2006-04-29 12:42:55 +00:00
|
|
|
);
|
|
|
|
|
|
2006-05-01 22:15:36 +00:00
|
|
|
extern void UIE4(void); /* needed for calculating the UIE number */
|
|
|
|
|
|
|
|
|
|
void UIE (unsigned int pc) __attribute__((section(".text")));
|
|
|
|
|
void UIE (unsigned int pc) /* Unexpected Interrupt or Exception */
|
|
|
|
|
{
|
|
|
|
|
#if CONFIG_LED == LED_REAL
|
2006-10-08 21:34:26 +00:00
|
|
|
bool state = false;
|
|
|
|
|
int i = 0;
|
2006-05-01 22:15:36 +00:00
|
|
|
#endif
|
|
|
|
|
unsigned int n;
|
|
|
|
|
char str[32];
|
|
|
|
|
|
|
|
|
|
asm volatile ("sts\tpr,%0" : "=r"(n));
|
2006-08-21 17:35:35 +00:00
|
|
|
|
2006-05-01 22:15:36 +00:00
|
|
|
/* clear screen */
|
|
|
|
|
lcd_clear_display ();
|
|
|
|
|
#ifdef HAVE_LCD_BITMAP
|
|
|
|
|
lcd_setfont(FONT_SYSFIXED);
|
|
|
|
|
#endif
|
|
|
|
|
/* output exception */
|
2006-05-02 07:36:39 +00:00
|
|
|
n = (n - (unsigned)UIE4 + 12)>>2; /* get exception or interrupt number */
|
2006-05-01 22:15:36 +00:00
|
|
|
snprintf(str,sizeof(str),"I%02x:%s",n,irqname[n]);
|
|
|
|
|
lcd_puts(0,0,str);
|
|
|
|
|
snprintf(str,sizeof(str),"at %08x",pc);
|
|
|
|
|
lcd_puts(0,1,str);
|
|
|
|
|
|
|
|
|
|
#ifdef HAVE_LCD_BITMAP
|
|
|
|
|
lcd_update ();
|
|
|
|
|
#endif
|
|
|
|
|
|
|
|
|
|
while (1)
|
|
|
|
|
{
|
|
|
|
|
#if CONFIG_LED == LED_REAL
|
2006-10-08 21:34:26 +00:00
|
|
|
if (--i <= 0)
|
|
|
|
|
{
|
|
|
|
|
state = !state;
|
|
|
|
|
led(state);
|
|
|
|
|
i = 240000;
|
|
|
|
|
}
|
2006-05-01 22:15:36 +00:00
|
|
|
#endif
|
|
|
|
|
|
|
|
|
|
/* try to restart firmware if ON is pressed */
|
|
|
|
|
#if CONFIG_KEYPAD == PLAYER_PAD
|
|
|
|
|
if (!(PADRL & 0x20))
|
|
|
|
|
#elif CONFIG_KEYPAD == RECORDER_PAD
|
|
|
|
|
#ifdef HAVE_FMADC
|
|
|
|
|
if (!(PCDR & 0x0008))
|
|
|
|
|
#else
|
|
|
|
|
if (!(PBDRH & 0x01))
|
|
|
|
|
#endif
|
|
|
|
|
#elif CONFIG_KEYPAD == ONDIO_PAD
|
|
|
|
|
if (!(PCDR & 0x0008))
|
|
|
|
|
#endif
|
2006-08-21 17:35:35 +00:00
|
|
|
{
|
2006-05-01 22:15:36 +00:00
|
|
|
/* enable the watchguard timer, but don't service it */
|
|
|
|
|
RSTCSR_W = 0x5a40; /* Reset enabled, power-on reset */
|
|
|
|
|
TCSR_W = 0xa560; /* Watchdog timer mode, timer enabled, sysclk/2 */
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
2002-05-29 09:11:04 +00:00
|
|
|
void system_init(void)
|
|
|
|
|
{
|
|
|
|
|
/* Disable all interrupts */
|
|
|
|
|
IPRA = 0;
|
|
|
|
|
IPRB = 0;
|
|
|
|
|
IPRC = 0;
|
|
|
|
|
IPRD = 0;
|
|
|
|
|
IPRE = 0;
|
|
|
|
|
|
|
|
|
|
/* NMI level low, falling edge on all interrupts */
|
|
|
|
|
ICR = 0;
|
2002-09-05 07:22:37 +00:00
|
|
|
|
2004-03-13 11:44:48 +00:00
|
|
|
/* Enable burst and RAS down mode on DRAM */
|
|
|
|
|
DCR |= 0x5000;
|
2002-09-05 10:21:48 +00:00
|
|
|
|
|
|
|
|
/* Activate Warp mode (simultaneous internal and external mem access) */
|
|
|
|
|
BCR |= 0x2000;
|
2003-10-27 10:30:12 +00:00
|
|
|
|
|
|
|
|
/* Bus state controller initializations. These are only necessary when
|
2004-10-12 09:09:16 +00:00
|
|
|
running from flash. */
|
|
|
|
|
WCR1 = 0x40FD; /* Long wait states for CS6 (ATA), short for the rest. */
|
2003-10-27 10:30:12 +00:00
|
|
|
WCR3 = 0x8000; /* WAIT is pulled up, 1 state inserted for CS6 */
|
2004-08-30 19:52:45 +00:00
|
|
|
}
|
|
|
|
|
|
2005-10-08 20:09:07 +00:00
|
|
|
void system_reboot (void)
|
|
|
|
|
{
|
|
|
|
|
set_irq_level(HIGHEST_IRQ_LEVEL);
|
|
|
|
|
|
|
|
|
|
asm volatile ("ldc\t%0,vbr" : : "r"(0));
|
|
|
|
|
|
|
|
|
|
PACR2 |= 0x4000; /* for coldstart detection */
|
|
|
|
|
IPRA = 0;
|
|
|
|
|
IPRB = 0;
|
|
|
|
|
IPRC = 0;
|
|
|
|
|
IPRD = 0;
|
|
|
|
|
IPRE = 0;
|
|
|
|
|
ICR = 0;
|
|
|
|
|
|
|
|
|
|
asm volatile ("jmp @%0; mov.l @%1,r15" : :
|
|
|
|
|
"r"(*(int*)0),"r"(4));
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/* Utilise the user break controller to catch invalid memory accesses. */
|
2004-08-30 19:52:45 +00:00
|
|
|
int system_memory_guard(int newmode)
|
|
|
|
|
{
|
|
|
|
|
static const struct {
|
|
|
|
|
unsigned long addr;
|
|
|
|
|
unsigned long mask;
|
|
|
|
|
unsigned short bbr;
|
|
|
|
|
} modes[MAXMEMGUARD] = {
|
|
|
|
|
/* catch nothing */
|
|
|
|
|
{ 0x00000000, 0x00000000, 0x0000 },
|
|
|
|
|
/* catch writes to area 02 (flash ROM) */
|
|
|
|
|
{ 0x02000000, 0x00FFFFFF, 0x00F8 },
|
|
|
|
|
/* catch all accesses to areas 00 (internal ROM) and 01 (free) */
|
|
|
|
|
{ 0x00000000, 0x01FFFFFF, 0x00FC }
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
int oldmode = MEMGUARD_NONE;
|
|
|
|
|
int i;
|
2006-08-21 17:35:35 +00:00
|
|
|
|
2004-08-30 19:52:45 +00:00
|
|
|
/* figure out the old mode from what is in the UBC regs. If the register
|
|
|
|
|
values don't match any mode, assume MEMGUARD_NONE */
|
|
|
|
|
for (i = MEMGUARD_NONE; i < MAXMEMGUARD; i++)
|
|
|
|
|
{
|
|
|
|
|
if (BAR == modes[i].addr && BAMR == modes[i].mask &&
|
|
|
|
|
BBR == modes[i].bbr)
|
|
|
|
|
{
|
|
|
|
|
oldmode = i;
|
|
|
|
|
break;
|
|
|
|
|
}
|
|
|
|
|
}
|
2006-08-21 17:35:35 +00:00
|
|
|
|
2004-08-30 19:52:45 +00:00
|
|
|
if (newmode == MEMGUARD_KEEP)
|
|
|
|
|
newmode = oldmode;
|
|
|
|
|
|
|
|
|
|
BBR = 0; /* switch off everything first */
|
|
|
|
|
|
|
|
|
|
/* always set the UBC according to the mode, in case the old settings
|
|
|
|
|
didn't match any valid mode */
|
|
|
|
|
BAR = modes[newmode].addr;
|
|
|
|
|
BAMR = modes[newmode].mask;
|
|
|
|
|
BBR = modes[newmode].bbr;
|
2006-08-21 17:35:35 +00:00
|
|
|
|
2004-08-30 19:52:45 +00:00
|
|
|
return oldmode;
|
2002-05-29 09:11:04 +00:00
|
|
|
}
|
2006-01-24 23:32:16 +00:00
|
|
|
#elif defined(CPU_ARM)
|
2005-11-07 23:07:19 +00:00
|
|
|
|
2006-01-19 15:03:34 +00:00
|
|
|
static const char* const uiename[] = {
|
|
|
|
|
"Undefined instruction", "Prefetch abort", "Data abort"
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
/* Unexpected Interrupt or Exception handler. Currently only deals with
|
|
|
|
|
exceptions, but will deal with interrupts later.
|
|
|
|
|
*/
|
|
|
|
|
void UIE(unsigned int pc, unsigned int num)
|
|
|
|
|
{
|
|
|
|
|
char str[32];
|
2006-08-21 17:35:35 +00:00
|
|
|
|
2006-01-19 15:03:34 +00:00
|
|
|
lcd_clear_display();
|
|
|
|
|
#ifdef HAVE_LCD_BITMAP
|
|
|
|
|
lcd_setfont(FONT_SYSFIXED);
|
|
|
|
|
#endif
|
|
|
|
|
lcd_puts(0, 0, uiename[num]);
|
|
|
|
|
snprintf(str, sizeof(str), "at %08x", pc);
|
|
|
|
|
lcd_puts(0, 1, str);
|
|
|
|
|
lcd_update();
|
2006-08-21 17:35:35 +00:00
|
|
|
|
2006-01-19 15:03:34 +00:00
|
|
|
while (1)
|
|
|
|
|
{
|
|
|
|
|
/* TODO: perhaps add button handling in here when we get a polling
|
|
|
|
|
driver some day.
|
|
|
|
|
*/
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
2006-11-22 00:49:16 +00:00
|
|
|
#if CONFIG_CPU==PP5020 || CONFIG_CPU==PP5024
|
2006-01-24 23:32:16 +00:00
|
|
|
|
2006-01-31 09:40:21 +00:00
|
|
|
unsigned int ipod_hw_rev;
|
|
|
|
|
|
2006-01-24 23:32:16 +00:00
|
|
|
#ifndef BOOTLOADER
|
|
|
|
|
extern void TIMER1(void);
|
2006-03-17 00:08:39 +00:00
|
|
|
extern void TIMER2(void);
|
2006-02-27 12:35:05 +00:00
|
|
|
|
2006-03-30 18:14:08 +00:00
|
|
|
#if defined(IPOD_MINI) /* mini 1 only, mini 2G uses iPod 4G code */
|
2006-02-27 12:35:05 +00:00
|
|
|
extern void ipod_mini_button_int(void);
|
|
|
|
|
|
|
|
|
|
void irq(void)
|
|
|
|
|
{
|
|
|
|
|
if (CPU_INT_STAT & TIMER1_MASK)
|
|
|
|
|
TIMER1();
|
2006-03-17 00:18:22 +00:00
|
|
|
else if (CPU_INT_STAT & TIMER2_MASK)
|
2006-03-17 00:08:39 +00:00
|
|
|
TIMER2();
|
2006-02-27 12:35:05 +00:00
|
|
|
else if (CPU_HI_INT_STAT & GPIO_MASK)
|
2006-08-21 17:35:35 +00:00
|
|
|
ipod_mini_button_int();
|
2006-02-27 12:35:05 +00:00
|
|
|
}
|
2006-11-22 00:49:16 +00:00
|
|
|
#elif (defined IRIVER_H10) || (defined IRIVER_H10_5GB) || defined(ELIO_TPJ1022) \
|
|
|
|
|
|| (defined SANSA_E200)
|
2006-08-20 23:05:47 +00:00
|
|
|
/* TODO: this should really be in the target tree, but moving it there caused
|
|
|
|
|
crt0.S not to find it while linking */
|
2006-11-22 00:49:16 +00:00
|
|
|
/* TODO: Even if it isn't in the target tree, this should be the default case */
|
2006-08-20 23:05:47 +00:00
|
|
|
void irq(void)
|
|
|
|
|
{
|
|
|
|
|
if (CPU_INT_STAT & TIMER1_MASK)
|
|
|
|
|
TIMER1();
|
|
|
|
|
else if (CPU_INT_STAT & TIMER2_MASK)
|
2006-08-21 17:35:35 +00:00
|
|
|
TIMER2();
|
2006-08-20 23:05:47 +00:00
|
|
|
}
|
2006-02-27 12:35:05 +00:00
|
|
|
#else
|
2006-01-24 23:32:16 +00:00
|
|
|
extern void ipod_4g_button_int(void);
|
|
|
|
|
|
|
|
|
|
void irq(void)
|
|
|
|
|
{
|
2006-08-21 17:35:35 +00:00
|
|
|
if (CPU_INT_STAT & TIMER1_MASK)
|
2006-01-24 23:32:16 +00:00
|
|
|
TIMER1();
|
2006-03-17 00:18:22 +00:00
|
|
|
else if (CPU_INT_STAT & TIMER2_MASK)
|
2006-03-17 00:08:39 +00:00
|
|
|
TIMER2();
|
2006-01-24 23:32:16 +00:00
|
|
|
else if (CPU_HI_INT_STAT & I2C_MASK)
|
|
|
|
|
ipod_4g_button_int();
|
|
|
|
|
}
|
|
|
|
|
#endif
|
2006-02-27 12:35:05 +00:00
|
|
|
#endif /* BOOTLOADER */
|
2006-01-24 23:32:16 +00:00
|
|
|
|
2006-08-21 17:35:35 +00:00
|
|
|
unsigned int current_core(void)
|
|
|
|
|
{
|
|
|
|
|
if(((*(volatile unsigned long *)(0x60000000)) & 0xff) == 0x55)
|
|
|
|
|
{
|
|
|
|
|
return CPU;
|
|
|
|
|
}
|
|
|
|
|
return COP;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
2005-12-17 19:11:43 +00:00
|
|
|
/* TODO: The following two function have been lifted straight from IPL, and
|
|
|
|
|
hence have a lot of numeric addresses used straight. I'd like to use
|
|
|
|
|
#defines for these, but don't know what most of them are for or even what
|
|
|
|
|
they should be named. Because of this I also have no way of knowing how
|
2006-08-21 17:35:35 +00:00
|
|
|
to extend the funtions to do alternate cache configurations and/or
|
2005-12-17 19:11:43 +00:00
|
|
|
some other CPU frequency scaling. */
|
|
|
|
|
|
2006-01-05 17:02:48 +00:00
|
|
|
#ifndef BOOTLOADER
|
2005-12-17 19:11:43 +00:00
|
|
|
static void ipod_init_cache(void)
|
|
|
|
|
{
|
2006-01-05 17:02:48 +00:00
|
|
|
/* Initialising the cache in the iPod bootloader prevents Rockbox from starting */
|
2005-12-17 19:11:43 +00:00
|
|
|
unsigned i;
|
|
|
|
|
|
|
|
|
|
/* cache init mode? */
|
|
|
|
|
outl(0x4, 0x6000C000);
|
|
|
|
|
|
|
|
|
|
/* PP5002 has 8KB cache */
|
|
|
|
|
for (i = 0xf0004000; i < 0xf0006000; i += 16) {
|
|
|
|
|
outl(0x0, i);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
outl(0x0, 0xf000f040);
|
|
|
|
|
outl(0x3fc0, 0xf000f044);
|
|
|
|
|
|
|
|
|
|
/* enable cache */
|
|
|
|
|
outl(0x1, 0x6000C000);
|
|
|
|
|
|
|
|
|
|
for (i = 0x10000000; i < 0x10002000; i += 16)
|
|
|
|
|
inb(i);
|
|
|
|
|
}
|
2006-03-17 02:44:55 +00:00
|
|
|
#endif
|
|
|
|
|
|
2006-03-17 14:27:09 +00:00
|
|
|
/* Not all iPod targets support CPU freq. boosting yet */
|
|
|
|
|
#ifdef HAVE_ADJUSTABLE_CPU_FREQ
|
2006-03-17 02:02:13 +00:00
|
|
|
void set_cpu_frequency(long frequency)
|
2005-12-17 19:11:43 +00:00
|
|
|
{
|
2006-03-17 02:02:13 +00:00
|
|
|
unsigned long postmult;
|
|
|
|
|
|
|
|
|
|
if (frequency == CPUFREQ_NORMAL)
|
|
|
|
|
postmult = CPUFREQ_NORMAL_MULT;
|
|
|
|
|
else if (frequency == CPUFREQ_MAX)
|
|
|
|
|
postmult = CPUFREQ_MAX_MULT;
|
|
|
|
|
else
|
|
|
|
|
postmult = CPUFREQ_DEFAULT_MULT;
|
|
|
|
|
cpu_frequency = frequency;
|
2005-12-17 19:11:43 +00:00
|
|
|
|
2006-03-17 02:02:13 +00:00
|
|
|
/* Enable PLL? */
|
2006-03-17 02:13:49 +00:00
|
|
|
outl(inl(0x70000020) | (1<<30), 0x70000020);
|
2006-03-17 02:02:13 +00:00
|
|
|
|
|
|
|
|
/* Select 24MHz crystal as clock source? */
|
2005-12-17 19:11:43 +00:00
|
|
|
outl((inl(0x60006020) & 0x0fffff0f) | 0x20000020, 0x60006020);
|
|
|
|
|
|
2006-03-17 02:02:13 +00:00
|
|
|
/* Clock frequency = (24/8)*postmult */
|
|
|
|
|
outl(0xaa020000 | 8 | (postmult << 8), 0x60006034);
|
2006-04-07 12:16:27 +00:00
|
|
|
|
2006-03-17 02:02:13 +00:00
|
|
|
/* Wait for PLL relock? */
|
2006-03-17 02:13:49 +00:00
|
|
|
udelay(2000);
|
2005-12-17 19:11:43 +00:00
|
|
|
|
2006-03-17 02:02:13 +00:00
|
|
|
/* Select PLL as clock source? */
|
2006-03-17 02:13:49 +00:00
|
|
|
outl((inl(0x60006020) & 0x0fffff0f) | 0x20000070, 0x60006020);
|
2006-04-07 12:16:27 +00:00
|
|
|
|
2006-08-30 15:36:55 +00:00
|
|
|
#if defined(IPOD_COLOR) || defined(IPOD_4G) || defined(IPOD_MINI) || defined(IRIVER_H10) || defined(IRIVER_H10_5GB)
|
2006-04-07 12:16:27 +00:00
|
|
|
/* We don't know why the timer interrupt gets disabled on the PP5020
|
|
|
|
|
based ipods, but without the following line, the 4Gs will freeze
|
2006-08-21 17:35:35 +00:00
|
|
|
when CPU frequency changing is enabled.
|
2006-04-07 12:16:27 +00:00
|
|
|
|
|
|
|
|
Note also that a simple "CPU_INT_EN = TIMER1_MASK;" (as used
|
|
|
|
|
elsewhere to enable interrupts) doesn't work, we need "|=".
|
|
|
|
|
|
|
|
|
|
It's not needed on the PP5021 and PP5022 ipods.
|
|
|
|
|
*/
|
|
|
|
|
|
|
|
|
|
/* unmask interrupt source */
|
|
|
|
|
CPU_INT_EN |= TIMER1_MASK;
|
|
|
|
|
#endif
|
2006-03-17 02:02:13 +00:00
|
|
|
}
|
2006-03-17 02:44:55 +00:00
|
|
|
#elif !defined(BOOTLOADER)
|
2006-03-17 02:02:13 +00:00
|
|
|
void ipod_set_cpu_frequency(void)
|
|
|
|
|
{
|
|
|
|
|
/* Enable PLL? */
|
2006-03-17 02:13:49 +00:00
|
|
|
outl(inl(0x70000020) | (1<<30), 0x70000020);
|
2006-03-17 02:02:13 +00:00
|
|
|
|
|
|
|
|
/* Select 24MHz crystal as clock source? */
|
|
|
|
|
outl((inl(0x60006020) & 0x0fffff0f) | 0x20000020, 0x60006020);
|
|
|
|
|
|
|
|
|
|
/* Clock frequency = (24/8)*25 = 75MHz */
|
|
|
|
|
outl(0xaa020000 | 8 | (25 << 8), 0x60006034);
|
|
|
|
|
/* Wait for PLL relock? */
|
2006-03-17 02:13:49 +00:00
|
|
|
udelay(2000);
|
2006-03-17 02:02:13 +00:00
|
|
|
|
|
|
|
|
/* Select PLL as clock source? */
|
2006-03-17 02:13:49 +00:00
|
|
|
outl((inl(0x60006020) & 0x0fffff0f) | 0x20000070, 0x60006020);
|
2005-12-17 19:11:43 +00:00
|
|
|
}
|
2006-01-05 17:02:48 +00:00
|
|
|
#endif
|
2005-12-17 19:11:43 +00:00
|
|
|
|
2005-12-12 13:53:22 +00:00
|
|
|
void system_init(void)
|
|
|
|
|
{
|
2006-01-05 17:02:48 +00:00
|
|
|
#ifndef BOOTLOADER
|
2006-01-31 01:50:07 +00:00
|
|
|
/* The hw revision is written to the last 4 bytes of SDRAM by the
|
|
|
|
|
bootloader - we save it before Rockbox overwrites it. */
|
|
|
|
|
ipod_hw_rev = (*((volatile unsigned long*)(0x01fffffc)));
|
|
|
|
|
|
2005-12-12 13:53:22 +00:00
|
|
|
/* disable all irqs */
|
|
|
|
|
outl(-1, 0x60001138);
|
|
|
|
|
outl(-1, 0x60001128);
|
|
|
|
|
outl(-1, 0x6000111c);
|
|
|
|
|
|
|
|
|
|
outl(-1, 0x60001038);
|
|
|
|
|
outl(-1, 0x60001028);
|
|
|
|
|
outl(-1, 0x6000101c);
|
2006-03-17 14:27:09 +00:00
|
|
|
#ifndef HAVE_ADJUSTABLE_CPU_FREQ
|
2006-03-17 02:02:13 +00:00
|
|
|
ipod_set_cpu_frequency();
|
|
|
|
|
#endif
|
2006-03-17 02:13:49 +00:00
|
|
|
ipod_init_cache();
|
2006-01-05 17:02:48 +00:00
|
|
|
#endif
|
2005-12-12 13:53:22 +00:00
|
|
|
}
|
2005-11-07 23:07:19 +00:00
|
|
|
|
2005-12-12 13:53:22 +00:00
|
|
|
void system_reboot(void)
|
|
|
|
|
{
|
2006-09-20 23:21:59 +00:00
|
|
|
/* Reboot */
|
|
|
|
|
DEV_RS |= DEV_SYSTEM;
|
2005-11-07 23:07:19 +00:00
|
|
|
}
|
|
|
|
|
|
2006-02-05 17:34:49 +00:00
|
|
|
int system_memory_guard(int newmode)
|
|
|
|
|
{
|
|
|
|
|
(void)newmode;
|
|
|
|
|
return 0;
|
|
|
|
|
}
|
|
|
|
|
#elif CONFIG_CPU==PP5002
|
|
|
|
|
unsigned int ipod_hw_rev;
|
|
|
|
|
#ifndef BOOTLOADER
|
|
|
|
|
extern void TIMER1(void);
|
2006-03-17 00:08:39 +00:00
|
|
|
extern void TIMER2(void);
|
2006-02-05 17:34:49 +00:00
|
|
|
|
|
|
|
|
void irq(void)
|
|
|
|
|
{
|
2006-08-21 17:35:35 +00:00
|
|
|
if (CPU_INT_STAT & TIMER1_MASK)
|
2006-02-05 17:34:49 +00:00
|
|
|
TIMER1();
|
2006-08-21 17:35:35 +00:00
|
|
|
else if (CPU_INT_STAT & TIMER2_MASK)
|
2006-03-17 00:08:39 +00:00
|
|
|
TIMER2();
|
2006-02-24 20:54:09 +00:00
|
|
|
}
|
|
|
|
|
|
2006-02-05 17:34:49 +00:00
|
|
|
#endif
|
|
|
|
|
|
2006-08-21 17:35:35 +00:00
|
|
|
unsigned int current_core(void)
|
|
|
|
|
{
|
|
|
|
|
if(((*(volatile unsigned long *)(0xc4000000)) & 0xff) == 0x55)
|
|
|
|
|
{
|
|
|
|
|
return CPU;
|
|
|
|
|
}
|
|
|
|
|
return COP;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
2006-02-05 17:34:49 +00:00
|
|
|
/* TODO: The following two function have been lifted straight from IPL, and
|
|
|
|
|
hence have a lot of numeric addresses used straight. I'd like to use
|
|
|
|
|
#defines for these, but don't know what most of them are for or even what
|
|
|
|
|
they should be named. Because of this I also have no way of knowing how
|
2006-08-21 17:35:35 +00:00
|
|
|
to extend the funtions to do alternate cache configurations and/or
|
2006-02-05 17:34:49 +00:00
|
|
|
some other CPU frequency scaling. */
|
|
|
|
|
|
|
|
|
|
#ifndef BOOTLOADER
|
|
|
|
|
static void ipod_init_cache(void)
|
|
|
|
|
{
|
|
|
|
|
int i =0;
|
|
|
|
|
/* Initialising the cache in the iPod bootloader prevents Rockbox from starting */
|
|
|
|
|
outl(inl(0xcf004050) & ~0x700, 0xcf004050);
|
|
|
|
|
outl(0x4000, 0xcf004020);
|
|
|
|
|
|
|
|
|
|
outl(0x2, 0xcf004024);
|
|
|
|
|
|
|
|
|
|
/* PP5002 has 8KB cache */
|
2006-02-24 20:54:09 +00:00
|
|
|
for (i = 0xf0004000; i < (int)(0xf0006000); i += 16) {
|
2006-02-05 17:34:49 +00:00
|
|
|
outl(0x0, i);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
outl(0x0, 0xf000f020);
|
|
|
|
|
outl(0x3fc0, 0xf000f024);
|
|
|
|
|
|
|
|
|
|
outl(0x3, 0xcf004024);
|
|
|
|
|
}
|
2006-07-24 22:49:06 +00:00
|
|
|
#endif
|
|
|
|
|
|
|
|
|
|
#ifdef HAVE_ADJUSTABLE_CPU_FREQ
|
|
|
|
|
void set_cpu_frequency(long frequency)
|
|
|
|
|
{
|
|
|
|
|
unsigned long postmult;
|
|
|
|
|
|
|
|
|
|
if (frequency == CPUFREQ_NORMAL)
|
|
|
|
|
postmult = CPUFREQ_NORMAL_MULT;
|
|
|
|
|
else if (frequency == CPUFREQ_MAX)
|
|
|
|
|
postmult = CPUFREQ_MAX_MULT;
|
|
|
|
|
else
|
|
|
|
|
postmult = CPUFREQ_DEFAULT_MULT;
|
|
|
|
|
cpu_frequency = frequency;
|
2006-08-21 17:35:35 +00:00
|
|
|
|
2006-07-24 22:49:06 +00:00
|
|
|
outl(0x02, 0xcf005008);
|
|
|
|
|
outl(0x55, 0xcf00500c);
|
|
|
|
|
outl(0x6000, 0xcf005010);
|
|
|
|
|
|
|
|
|
|
/* Clock frequency = (24/8)*postmult */
|
|
|
|
|
outl(8, 0xcf005018);
|
|
|
|
|
outl(postmult, 0xcf00501c);
|
|
|
|
|
|
|
|
|
|
outl(0xe000, 0xcf005010);
|
|
|
|
|
|
|
|
|
|
/* Wait for PLL relock? */
|
|
|
|
|
udelay(2000);
|
|
|
|
|
|
|
|
|
|
/* Select PLL as clock source? */
|
|
|
|
|
outl(0xa8, 0xcf00500c);
|
|
|
|
|
}
|
|
|
|
|
#elif !defined(BOOTLOADER)
|
2006-02-05 17:34:49 +00:00
|
|
|
static void ipod_set_cpu_speed(void)
|
|
|
|
|
{
|
|
|
|
|
outl(0x02, 0xcf005008);
|
|
|
|
|
outl(0x55, 0xcf00500c);
|
|
|
|
|
outl(0x6000, 0xcf005010);
|
|
|
|
|
#if 1
|
|
|
|
|
// 75 MHz (24/24 * 75) (default)
|
|
|
|
|
outl(24, 0xcf005018);
|
|
|
|
|
outl(75, 0xcf00501c);
|
|
|
|
|
#endif
|
|
|
|
|
|
|
|
|
|
#if 0
|
|
|
|
|
// 66 MHz (24/3 * 8)
|
|
|
|
|
outl(3, 0xcf005018);
|
|
|
|
|
outl(8, 0xcf00501c);
|
|
|
|
|
#endif
|
|
|
|
|
|
|
|
|
|
outl(0xe000, 0xcf005010);
|
|
|
|
|
|
|
|
|
|
udelay(2000);
|
|
|
|
|
|
|
|
|
|
outl(0xa8, 0xcf00500c);
|
|
|
|
|
}
|
|
|
|
|
#endif
|
|
|
|
|
|
|
|
|
|
void system_init(void)
|
|
|
|
|
{
|
|
|
|
|
#ifndef BOOTLOADER
|
|
|
|
|
ipod_hw_rev = (*((volatile unsigned long*)(0x01fffffc)));
|
|
|
|
|
outl(-1, 0xcf00101c);
|
|
|
|
|
outl(-1, 0xcf001028);
|
|
|
|
|
outl(-1, 0xcf001038);
|
2006-07-24 22:49:06 +00:00
|
|
|
#ifndef HAVE_ADJUSTABLE_CPU_FREQ
|
2006-02-05 17:34:49 +00:00
|
|
|
ipod_set_cpu_speed();
|
2006-07-24 22:49:06 +00:00
|
|
|
#endif
|
2006-02-05 17:34:49 +00:00
|
|
|
ipod_init_cache();
|
|
|
|
|
#endif
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
void system_reboot(void)
|
|
|
|
|
{
|
|
|
|
|
outl(inl(0xcf005030) | 0x4, 0xcf005030);
|
|
|
|
|
}
|
|
|
|
|
|
2005-11-12 15:29:43 +00:00
|
|
|
int system_memory_guard(int newmode)
|
|
|
|
|
{
|
|
|
|
|
(void)newmode;
|
|
|
|
|
return 0;
|
|
|
|
|
}
|
2005-11-07 23:07:19 +00:00
|
|
|
|
2006-01-12 00:35:50 +00:00
|
|
|
#elif CONFIG_CPU==PNX0101
|
|
|
|
|
|
|
|
|
|
interrupt_handler_t interrupt_vector[0x1d] __attribute__ ((section(".idata")));
|
|
|
|
|
|
|
|
|
|
#define IRQ_REG(reg) (*(volatile unsigned long *)(0x80300000 + (reg)))
|
|
|
|
|
|
|
|
|
|
static inline unsigned long irq_read(int reg)
|
|
|
|
|
{
|
|
|
|
|
unsigned long v, v2;
|
|
|
|
|
do
|
|
|
|
|
{
|
|
|
|
|
v = IRQ_REG(reg);
|
|
|
|
|
v2 = IRQ_REG(reg);
|
|
|
|
|
} while (v != v2);
|
|
|
|
|
return v;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
#define IRQ_WRITE_WAIT(reg, val, cond) \
|
|
|
|
|
do { unsigned long v, v2; \
|
|
|
|
|
do { \
|
|
|
|
|
IRQ_REG(reg) = (val); \
|
|
|
|
|
v = IRQ_REG(reg); \
|
|
|
|
|
v2 = IRQ_REG(reg); \
|
|
|
|
|
} while ((v != v2) || !(cond)); \
|
|
|
|
|
} while (0);
|
|
|
|
|
|
2006-01-24 23:32:16 +00:00
|
|
|
static void undefined_int(void)
|
|
|
|
|
{
|
|
|
|
|
}
|
2006-01-12 00:35:50 +00:00
|
|
|
|
|
|
|
|
void irq(void)
|
|
|
|
|
{
|
|
|
|
|
int n = irq_read(0x100) >> 3;
|
|
|
|
|
(*(interrupt_vector[n]))();
|
|
|
|
|
}
|
|
|
|
|
|
2006-02-03 23:26:14 +00:00
|
|
|
void fiq(void)
|
|
|
|
|
{
|
|
|
|
|
}
|
|
|
|
|
|
2006-01-12 00:35:50 +00:00
|
|
|
void irq_enable_int(int n)
|
|
|
|
|
{
|
|
|
|
|
IRQ_WRITE_WAIT(0x404 + n * 4, 0x4010000, v & 0x10000);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
void irq_set_int_handler(int n, interrupt_handler_t handler)
|
|
|
|
|
{
|
|
|
|
|
interrupt_vector[n + 1] = handler;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
void system_init(void)
|
|
|
|
|
{
|
|
|
|
|
int i;
|
|
|
|
|
|
|
|
|
|
/* turn off watchdog */
|
|
|
|
|
(*(volatile unsigned long *)0x80002804) = 0;
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
IRQ_WRITE_WAIT(0x100, 0, v == 0);
|
|
|
|
|
IRQ_WRITE_WAIT(0x104, 0, v == 0);
|
|
|
|
|
IRQ_WRITE_WAIT(0, 0, v == 0);
|
|
|
|
|
IRQ_WRITE_WAIT(4, 0, v == 0);
|
|
|
|
|
*/
|
2006-08-21 17:35:35 +00:00
|
|
|
|
2006-01-12 00:35:50 +00:00
|
|
|
for (i = 0; i < 0x1c; i++)
|
|
|
|
|
{
|
|
|
|
|
IRQ_WRITE_WAIT(0x404 + i * 4, 0x1e000001, (v & 0x3010f) == 1);
|
|
|
|
|
IRQ_WRITE_WAIT(0x404 + i * 4, 0x4000000, (v & 0x10000) == 0);
|
|
|
|
|
IRQ_WRITE_WAIT(0x404 + i * 4, 0x10000001, (v & 0xf) == 1);
|
2006-01-24 23:32:16 +00:00
|
|
|
interrupt_vector[i + 1] = undefined_int;
|
2006-01-12 00:35:50 +00:00
|
|
|
}
|
2006-01-24 23:32:16 +00:00
|
|
|
interrupt_vector[0] = undefined_int;
|
2006-01-12 00:35:50 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
void system_reboot(void)
|
|
|
|
|
{
|
|
|
|
|
(*(volatile unsigned long *)0x80002804) = 1;
|
|
|
|
|
while (1);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
int system_memory_guard(int newmode)
|
|
|
|
|
{
|
|
|
|
|
(void)newmode;
|
|
|
|
|
return 0;
|
|
|
|
|
}
|
|
|
|
|
|
2006-01-24 23:32:16 +00:00
|
|
|
#endif /* CPU_ARM */
|
2005-10-08 20:09:07 +00:00
|
|
|
#endif /* CONFIG_CPU */
|
2005-02-02 21:56:03 +00:00
|
|
|
|
