SH1: Moved exception vector table generation and weak aliasing into an asm block. Allows building with gcc 4.x

git-svn-id: svn://svn.rockbox.org/rockbox/trunk@9832 a1c6a512-1295-4272-9138-f99709370657
This commit is contained in:
Jens Arnold 2006-04-29 12:42:55 +00:00
parent 4bfdd1fca1
commit 03cff5779b

View file

@ -665,11 +665,6 @@ void set_cpu_frequency(long frequency)
#include "system.h"
#include "rolo.h"
#define default_interrupt(name,number) \
extern __attribute__((weak,alias("UIE" #number))) void name (void); void UIE##number (void)
#define reserve_interrupt(number) \
void UIE##number (void)
static const char* const irqname[] = {
"", "", "", "", "IllInstr", "", "IllSltIn","","",
"CPUAdrEr", "DMAAdrEr", "NMI", "UserBrk",
@ -688,183 +683,240 @@ static const char* const irqname[] = {
"ParityEr","A/D conv","","","Watchdog","DRAMRefr"
};
reserve_interrupt ( 0);
reserve_interrupt ( 1);
reserve_interrupt ( 2);
reserve_interrupt ( 3);
default_interrupt (GII, 4);
reserve_interrupt ( 5);
default_interrupt (ISI, 6);
reserve_interrupt ( 7);
reserve_interrupt ( 8);
default_interrupt (CPUAE, 9);
default_interrupt (DMAAE, 10);
default_interrupt (NMI, 11);
default_interrupt (UB, 12);
reserve_interrupt ( 13);
reserve_interrupt ( 14);
reserve_interrupt ( 15);
reserve_interrupt ( 16); /* TCB #0 */
reserve_interrupt ( 17); /* TCB #1 */
reserve_interrupt ( 18); /* TCB #2 */
reserve_interrupt ( 19); /* TCB #3 */
reserve_interrupt ( 20); /* TCB #4 */
reserve_interrupt ( 21); /* TCB #5 */
reserve_interrupt ( 22); /* TCB #6 */
reserve_interrupt ( 23); /* TCB #7 */
reserve_interrupt ( 24); /* TCB #8 */
reserve_interrupt ( 25); /* TCB #9 */
reserve_interrupt ( 26); /* TCB #10 */
reserve_interrupt ( 27); /* TCB #11 */
reserve_interrupt ( 28); /* TCB #12 */
reserve_interrupt ( 29); /* TCB #13 */
reserve_interrupt ( 30); /* TCB #14 */
reserve_interrupt ( 31); /* TCB #15 */
default_interrupt (TRAPA32, 32);
default_interrupt (TRAPA33, 33);
default_interrupt (TRAPA34, 34);
default_interrupt (TRAPA35, 35);
default_interrupt (TRAPA36, 36);
default_interrupt (TRAPA37, 37);
default_interrupt (TRAPA38, 38);
default_interrupt (TRAPA39, 39);
default_interrupt (TRAPA40, 40);
default_interrupt (TRAPA41, 41);
default_interrupt (TRAPA42, 42);
default_interrupt (TRAPA43, 43);
default_interrupt (TRAPA44, 44);
default_interrupt (TRAPA45, 45);
default_interrupt (TRAPA46, 46);
default_interrupt (TRAPA47, 47);
default_interrupt (TRAPA48, 48);
default_interrupt (TRAPA49, 49);
default_interrupt (TRAPA50, 50);
default_interrupt (TRAPA51, 51);
default_interrupt (TRAPA52, 52);
default_interrupt (TRAPA53, 53);
default_interrupt (TRAPA54, 54);
default_interrupt (TRAPA55, 55);
default_interrupt (TRAPA56, 56);
default_interrupt (TRAPA57, 57);
default_interrupt (TRAPA58, 58);
default_interrupt (TRAPA59, 59);
default_interrupt (TRAPA60, 60);
default_interrupt (TRAPA61, 61);
default_interrupt (TRAPA62, 62);
default_interrupt (TRAPA63, 63);
default_interrupt (IRQ0, 64);
default_interrupt (IRQ1, 65);
default_interrupt (IRQ2, 66);
default_interrupt (IRQ3, 67);
default_interrupt (IRQ4, 68);
default_interrupt (IRQ5, 69);
default_interrupt (IRQ6, 70);
default_interrupt (IRQ7, 71);
default_interrupt (DEI0, 72);
reserve_interrupt ( 73);
default_interrupt (DEI1, 74);
reserve_interrupt ( 75);
default_interrupt (DEI2, 76);
reserve_interrupt ( 77);
default_interrupt (DEI3, 78);
reserve_interrupt ( 79);
default_interrupt (IMIA0, 80);
default_interrupt (IMIB0, 81);
default_interrupt (OVI0, 82);
reserve_interrupt ( 83);
default_interrupt (IMIA1, 84);
default_interrupt (IMIB1, 85);
default_interrupt (OVI1, 86);
reserve_interrupt ( 87);
default_interrupt (IMIA2, 88);
default_interrupt (IMIB2, 89);
default_interrupt (OVI2, 90);
reserve_interrupt ( 91);
default_interrupt (IMIA3, 92);
default_interrupt (IMIB3, 93);
default_interrupt (OVI3, 94);
reserve_interrupt ( 95);
default_interrupt (IMIA4, 96);
default_interrupt (IMIB4, 97);
default_interrupt (OVI4, 98);
reserve_interrupt ( 99);
default_interrupt (REI0, 100);
default_interrupt (RXI0, 101);
default_interrupt (TXI0, 102);
default_interrupt (TEI0, 103);
default_interrupt (REI1, 104);
default_interrupt (RXI1, 105);
default_interrupt (TXI1, 106);
default_interrupt (TEI1, 107);
reserve_interrupt ( 108);
default_interrupt (ADITI, 109);
/* reset vectors are handled in crt0.S */
void (*vbr[]) (void) __attribute__ ((section (".vectors"))) =
{
GII, /*** 4 General Illegal Instruction ***/
UIE5, /*** 5 Reserved ***/
ISI, /*** 6 Illegal Slot Instruction ***/
UIE7, /*** 7-8 Reserved ***/
UIE8,
CPUAE, /*** 9 CPU Address Error ***/
DMAAE, /*** 10 DMA Address Error ***/
NMI, /*** 11 NMI ***/
UB, /*** 12 User Break ***/
/* Vector table & UIE block.
* Handled in asm because gcc 4.x doesn't allow weak aliases to symbols
* defined in an asm block -- silly.
* Reset vectors (0..3) are handled in crt0.S */
/*** 13-31 Reserved ***/
UIE13,UIE14,UIE15,UIE16,UIE17,UIE18,UIE19,UIE20,
UIE21,UIE22,UIE23,UIE24,UIE25,UIE26,UIE27,UIE28,
UIE29,UIE30,UIE31,
#define RESERVE_INTERRUPT(number) "\t.long\t_UIE" #number "\n"
#define DEFAULT_INTERRUPT(name, number) "\t.weak\t_" #name \
"\n\t.set\t_" #name ",_UIE" #number \
"\n\t.long\t_" #name "\n"
/*** 32-63 TRAPA #20...#3F ***/
TRAPA32,TRAPA33,TRAPA34,TRAPA35,TRAPA36,TRAPA37,TRAPA38,TRAPA39,
TRAPA40,TRAPA41,TRAPA42,TRAPA43,TRAPA44,TRAPA45,TRAPA46,TRAPA47,
TRAPA48,TRAPA49,TRAPA50,TRAPA51,TRAPA52,TRAPA53,TRAPA54,TRAPA55,
TRAPA56,TRAPA57,TRAPA58,TRAPA59,TRAPA60,TRAPA61,TRAPA62,TRAPA63,
asm (
".section\t.vectors,\"aw\",@progbits\n"
DEFAULT_INTERRUPT (GII, 4)
RESERVE_INTERRUPT ( 5)
DEFAULT_INTERRUPT (ISI, 6)
RESERVE_INTERRUPT ( 7)
RESERVE_INTERRUPT ( 8)
DEFAULT_INTERRUPT (CPUAE, 9)
DEFAULT_INTERRUPT (DMAAE, 10)
DEFAULT_INTERRUPT (NMI, 11)
DEFAULT_INTERRUPT (UB, 12)
RESERVE_INTERRUPT ( 13)
RESERVE_INTERRUPT ( 14)
RESERVE_INTERRUPT ( 15)
RESERVE_INTERRUPT ( 16) /* TCB #0 */
RESERVE_INTERRUPT ( 17) /* TCB #1 */
RESERVE_INTERRUPT ( 18) /* TCB #2 */
RESERVE_INTERRUPT ( 19) /* TCB #3 */
RESERVE_INTERRUPT ( 20) /* TCB #4 */
RESERVE_INTERRUPT ( 21) /* TCB #5 */
RESERVE_INTERRUPT ( 22) /* TCB #6 */
RESERVE_INTERRUPT ( 23) /* TCB #7 */
RESERVE_INTERRUPT ( 24) /* TCB #8 */
RESERVE_INTERRUPT ( 25) /* TCB #9 */
RESERVE_INTERRUPT ( 26) /* TCB #10 */
RESERVE_INTERRUPT ( 27) /* TCB #11 */
RESERVE_INTERRUPT ( 28) /* TCB #12 */
RESERVE_INTERRUPT ( 29) /* TCB #13 */
RESERVE_INTERRUPT ( 30) /* TCB #14 */
RESERVE_INTERRUPT ( 31) /* TCB #15 */
DEFAULT_INTERRUPT (TRAPA32, 32)
DEFAULT_INTERRUPT (TRAPA33, 33)
DEFAULT_INTERRUPT (TRAPA34, 34)
DEFAULT_INTERRUPT (TRAPA35, 35)
DEFAULT_INTERRUPT (TRAPA36, 36)
DEFAULT_INTERRUPT (TRAPA37, 37)
DEFAULT_INTERRUPT (TRAPA38, 38)
DEFAULT_INTERRUPT (TRAPA39, 39)
DEFAULT_INTERRUPT (TRAPA40, 40)
DEFAULT_INTERRUPT (TRAPA41, 41)
DEFAULT_INTERRUPT (TRAPA42, 42)
DEFAULT_INTERRUPT (TRAPA43, 43)
DEFAULT_INTERRUPT (TRAPA44, 44)
DEFAULT_INTERRUPT (TRAPA45, 45)
DEFAULT_INTERRUPT (TRAPA46, 46)
DEFAULT_INTERRUPT (TRAPA47, 47)
DEFAULT_INTERRUPT (TRAPA48, 48)
DEFAULT_INTERRUPT (TRAPA49, 49)
DEFAULT_INTERRUPT (TRAPA50, 50)
DEFAULT_INTERRUPT (TRAPA51, 51)
DEFAULT_INTERRUPT (TRAPA52, 52)
DEFAULT_INTERRUPT (TRAPA53, 53)
DEFAULT_INTERRUPT (TRAPA54, 54)
DEFAULT_INTERRUPT (TRAPA55, 55)
DEFAULT_INTERRUPT (TRAPA56, 56)
DEFAULT_INTERRUPT (TRAPA57, 57)
DEFAULT_INTERRUPT (TRAPA58, 58)
DEFAULT_INTERRUPT (TRAPA59, 59)
DEFAULT_INTERRUPT (TRAPA60, 60)
DEFAULT_INTERRUPT (TRAPA61, 61)
DEFAULT_INTERRUPT (TRAPA62, 62)
DEFAULT_INTERRUPT (TRAPA63, 63)
DEFAULT_INTERRUPT (IRQ0, 64)
DEFAULT_INTERRUPT (IRQ1, 65)
DEFAULT_INTERRUPT (IRQ2, 66)
DEFAULT_INTERRUPT (IRQ3, 67)
DEFAULT_INTERRUPT (IRQ4, 68)
DEFAULT_INTERRUPT (IRQ5, 69)
DEFAULT_INTERRUPT (IRQ6, 70)
DEFAULT_INTERRUPT (IRQ7, 71)
DEFAULT_INTERRUPT (DEI0, 72)
RESERVE_INTERRUPT ( 73)
DEFAULT_INTERRUPT (DEI1, 74)
RESERVE_INTERRUPT ( 75)
DEFAULT_INTERRUPT (DEI2, 76)
RESERVE_INTERRUPT ( 77)
DEFAULT_INTERRUPT (DEI3, 78)
RESERVE_INTERRUPT ( 79)
DEFAULT_INTERRUPT (IMIA0, 80)
DEFAULT_INTERRUPT (IMIB0, 81)
DEFAULT_INTERRUPT (OVI0, 82)
RESERVE_INTERRUPT ( 83)
DEFAULT_INTERRUPT (IMIA1, 84)
DEFAULT_INTERRUPT (IMIB1, 85)
DEFAULT_INTERRUPT (OVI1, 86)
RESERVE_INTERRUPT ( 87)
DEFAULT_INTERRUPT (IMIA2, 88)
DEFAULT_INTERRUPT (IMIB2, 89)
DEFAULT_INTERRUPT (OVI2, 90)
RESERVE_INTERRUPT ( 91)
DEFAULT_INTERRUPT (IMIA3, 92)
DEFAULT_INTERRUPT (IMIB3, 93)
DEFAULT_INTERRUPT (OVI3, 94)
RESERVE_INTERRUPT ( 95)
DEFAULT_INTERRUPT (IMIA4, 96)
DEFAULT_INTERRUPT (IMIB4, 97)
DEFAULT_INTERRUPT (OVI4, 98)
RESERVE_INTERRUPT ( 99)
DEFAULT_INTERRUPT (REI0, 100)
DEFAULT_INTERRUPT (RXI0, 101)
DEFAULT_INTERRUPT (TXI0, 102)
DEFAULT_INTERRUPT (TEI0, 103)
DEFAULT_INTERRUPT (REI1, 104)
DEFAULT_INTERRUPT (RXI1, 105)
DEFAULT_INTERRUPT (TXI1, 106)
DEFAULT_INTERRUPT (TEI1, 107)
RESERVE_INTERRUPT ( 108)
DEFAULT_INTERRUPT (ADITI, 109)
/*** 64-71 IRQ0-7 ***/
IRQ0,IRQ1,IRQ2,IRQ3,IRQ4,IRQ5,IRQ6,IRQ7,
DEI0, /*** 72 DMAC0 ***/
UIE73, /*** 73 Reserved ***/
DEI1, /*** 74 DMAC1 ***/
UIE75, /*** 75 Reserved ***/
DEI2, /*** 76 DMAC2 ***/
UIE77, /*** 77 Reserved ***/
DEI3, /*** 78 DMAC3 ***/
UIE79, /*** 79 Reserved ***/
IMIA0, /*** 80-82 ITU0 ***/
IMIB0,
OVI0,
UIE83, /*** 83 Reserved ***/
IMIA1, /*** 84-86 ITU1 ***/
IMIB1,
OVI1,
UIE87, /*** 87 Reserved ***/
IMIA2, /*** 88-90 ITU2 ***/
IMIB2,
OVI2,
UIE91, /*** 91 Reserved ***/
IMIA3, /*** 92-94 ITU3 ***/
IMIB3,
OVI3,
UIE95, /*** 95 Reserved ***/
IMIA4, /*** 96-98 ITU4 ***/
IMIB4,
OVI4,
UIE99, /*** 99 Reserved ***/
/*** 100-103 SCI0 ***/
REI0,RXI0,TXI0,TEI0,
/*** 104-107 SCI1 ***/
REI1,RXI1,TXI1,TEI1,
UIE108, /*** 108 Parity Control Unit ***/
ADITI /*** 109 AD Converter ***/
};
"\t.text\n"
"_UIE0:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\n"
"_UIE1:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\n"
"_UIE2:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\n"
"_UIE3:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\n"
"_UIE4:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\n"
"_UIE5:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\n"
"_UIE6:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\n"
"_UIE7:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\n"
"_UIE8:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\n"
"_UIE9:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\n"
"_UIE10:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\n"
"_UIE11:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\n"
"_UIE12:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\n"
"_UIE13:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\n"
"_UIE14:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\n"
"_UIE15:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\n"
"_UIE16:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\n"
"_UIE17:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\n"
"_UIE18:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\n"
"_UIE19:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\n"
"_UIE20:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\n"
"_UIE21:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\n"
"_UIE22:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\n"
"_UIE23:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\n"
"_UIE24:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\n"
"_UIE25:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\n"
"_UIE26:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\n"
"_UIE27:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\n"
"_UIE28:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\n"
"_UIE29:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\n"
"_UIE30:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\n"
"_UIE31:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\n"
"_UIE32:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\n"
"_UIE33:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\n"
"_UIE34:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\n"
"_UIE35:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\n"
"_UIE36:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\n"
"_UIE37:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\n"
"_UIE38:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\n"
"_UIE39:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\n"
"_UIE40:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\n"
"_UIE41:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\n"
"_UIE42:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\n"
"_UIE43:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\n"
"_UIE44:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\n"
"_UIE45:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\n"
"_UIE46:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\n"
"_UIE47:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\n"
"_UIE48:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\n"
"_UIE49:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\n"
"_UIE50:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\n"
"_UIE51:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\n"
"_UIE52:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\n"
"_UIE53:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\n"
"_UIE54:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\n"
"_UIE55:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\n"
"_UIE56:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\n"
"_UIE57:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\n"
"_UIE58:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\n"
"_UIE59:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\n"
"_UIE60:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\n"
"_UIE61:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\n"
"_UIE62:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\n"
"_UIE63:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\n"
"_UIE64:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\n"
"_UIE65:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\n"
"_UIE66:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\n"
"_UIE67:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\n"
"_UIE68:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\n"
"_UIE69:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\n"
"_UIE70:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\n"
"_UIE71:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\n"
"_UIE72:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\n"
"_UIE73:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\n"
"_UIE74:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\n"
"_UIE75:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\n"
"_UIE76:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\n"
"_UIE77:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\n"
"_UIE78:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\n"
"_UIE79:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\n"
"_UIE80:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\n"
"_UIE81:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\n"
"_UIE82:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\n"
"_UIE83:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\n"
"_UIE84:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\n"
"_UIE85:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\n"
"_UIE86:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\n"
"_UIE87:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\n"
"_UIE88:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\n"
"_UIE89:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\n"
"_UIE90:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\n"
"_UIE91:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\n"
"_UIE92:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\n"
"_UIE93:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\n"
"_UIE94:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\n"
"_UIE95:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\n"
"_UIE96:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\n"
"_UIE97:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\n"
"_UIE98:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\n"
"_UIE99:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\n"
"_UIE100:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\n"
"_UIE101:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\n"
"_UIE102:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\n"
"_UIE103:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\n"
"_UIE104:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\n"
"_UIE105:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\n"
"_UIE106:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\n"
"_UIE107:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\n"
"_UIE108:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\n"
"_UIE109:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\n"
);
extern void UIE0(void); /* needed for calculating the UIE number */
void UIE (unsigned int pc) /* Unexpected Interrupt or Exception */
{
@ -922,118 +974,6 @@ void UIE (unsigned int pc) /* Unexpected Interrupt or Exception */
}
}
asm (
"_UIE0:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
"_UIE1:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
"_UIE2:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
"_UIE3:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
"_UIE4:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
"_UIE5:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
"_UIE6:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
"_UIE7:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
"_UIE8:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
"_UIE9:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
"_UIE10:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
"_UIE11:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
"_UIE12:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
"_UIE13:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
"_UIE14:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
"_UIE15:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
"_UIE16:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
"_UIE17:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
"_UIE18:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
"_UIE19:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
"_UIE20:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
"_UIE21:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
"_UIE22:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
"_UIE23:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
"_UIE24:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
"_UIE25:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
"_UIE26:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
"_UIE27:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
"_UIE28:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
"_UIE29:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
"_UIE30:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
"_UIE31:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
"_UIE32:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
"_UIE33:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
"_UIE34:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
"_UIE35:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
"_UIE36:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
"_UIE37:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
"_UIE38:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
"_UIE39:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
"_UIE40:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
"_UIE41:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
"_UIE42:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
"_UIE43:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
"_UIE44:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
"_UIE45:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
"_UIE46:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
"_UIE47:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
"_UIE48:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
"_UIE49:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
"_UIE50:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
"_UIE51:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
"_UIE52:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
"_UIE53:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
"_UIE54:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
"_UIE55:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
"_UIE56:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
"_UIE57:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
"_UIE58:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
"_UIE59:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
"_UIE60:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
"_UIE61:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
"_UIE62:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
"_UIE63:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
"_UIE64:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
"_UIE65:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
"_UIE66:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
"_UIE67:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
"_UIE68:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
"_UIE69:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
"_UIE70:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
"_UIE71:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
"_UIE72:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
"_UIE73:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
"_UIE74:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
"_UIE75:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
"_UIE76:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
"_UIE77:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
"_UIE78:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
"_UIE79:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
"_UIE80:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
"_UIE81:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
"_UIE82:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
"_UIE83:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
"_UIE84:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
"_UIE85:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
"_UIE86:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
"_UIE87:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
"_UIE88:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
"_UIE89:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
"_UIE90:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
"_UIE91:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
"_UIE92:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
"_UIE93:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
"_UIE94:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
"_UIE95:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
"_UIE96:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
"_UIE97:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
"_UIE98:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
"_UIE99:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
"_UIE100:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
"_UIE101:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
"_UIE102:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
"_UIE103:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
"_UIE104:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
"_UIE105:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
"_UIE106:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
"_UIE107:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
"_UIE108:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
"_UIE109:\tbsr\t_UIE\n\tmov.l\t@r15+,r4");
void system_init(void)
{
/* Disable all interrupts */