2003-12-12 13:29:34 +00:00
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#include "config.h"
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2002-05-02 14:05:51 +00:00
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ENTRY(start)
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2005-07-18 12:40:29 +00:00
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#ifdef CPU_COLDFIRE
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2004-10-06 13:30:44 +00:00
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OUTPUT_FORMAT(elf32-m68k)
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2006-08-31 19:45:05 +00:00
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INPUT(target/coldfire/crt0.o)
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2006-01-12 00:35:50 +00:00
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#elif defined(CPU_ARM)
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2005-11-07 23:07:19 +00:00
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OUTPUT_FORMAT(elf32-littlearm)
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OUTPUT_ARCH(arm)
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2006-08-31 19:45:05 +00:00
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#ifdef CPU_PP
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INPUT(target/arm/crt0-pp.o)
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2007-11-11 17:58:13 +00:00
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#elif CONFIG_CPU==DM320
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2007-09-30 16:29:21 +00:00
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INPUT(target/arm/tms320dm320/crt0.o)
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2007-11-11 17:58:13 +00:00
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#elif CONFIG_CPU==S3C2440
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INPUT(target/arm/s3c2440/crt0.o)
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2007-03-24 19:26:13 +00:00
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#elif CONFIG_CPU == PNX0101
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2007-04-19 10:14:55 +00:00
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INPUT(target/arm/pnx0101/crt0-pnx0101.o)
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2006-08-31 19:45:05 +00:00
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#elif defined(CPU_ARM)
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INPUT(target/arm/crt0.o)
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#endif
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2004-10-06 13:30:44 +00:00
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#else
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2002-03-28 15:09:10 +00:00
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OUTPUT_FORMAT(elf32-sh)
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2006-08-31 19:45:05 +00:00
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INPUT(target/sh/crt0.o)
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2005-11-07 23:07:19 +00:00
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#endif
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2002-08-01 08:12:17 +00:00
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2005-06-27 21:23:03 +00:00
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#define PLUGINSIZE PLUGIN_BUFFER_SIZE
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#define CODECSIZE CODEC_SIZE
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2003-06-29 16:33:04 +00:00
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2003-02-26 16:05:30 +00:00
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#ifdef DEBUG
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2004-10-06 13:30:44 +00:00
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#define STUBOFFSET 0x10000
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2003-02-26 16:05:30 +00:00
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#else
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2004-10-06 13:30:44 +00:00
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#define STUBOFFSET 0
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2003-02-26 16:05:30 +00:00
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#endif
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2004-10-06 13:30:44 +00:00
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2007-11-11 20:50:44 +00:00
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#if CONFIG_CPU==S3C2440
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#include "s3c2440.h"
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#define DRAMSIZE (MEMORYSIZE * 0x100000) - 0x100 - PLUGINSIZE - STUBOFFSET - CODECSIZE - LCD_BUFFER_SIZE - TTB_SIZE
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#elif CONFIG_CPU==DM320
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#include "dm320.h"
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#define DRAMSIZE (MEMORYSIZE * 0x100000) - PLUGINSIZE - STUBOFFSET - CODECSIZE - LCD_BUFFER_SIZE - TTB_SIZE
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#else
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#define DRAMSIZE (MEMORYSIZE * 0x100000) - PLUGINSIZE - STUBOFFSET - CODECSIZE
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#endif
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2005-07-09 07:46:42 +00:00
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#if defined(IRIVER_H100_SERIES) || defined(IRIVER_H300)
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2005-07-08 15:08:59 +00:00
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#define DRAMORIG 0x31000000 + STUBOFFSET
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2005-07-09 07:46:42 +00:00
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#define IRAMORIG 0x10000000
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2005-09-01 20:57:33 +00:00
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#define IRAMSIZE 0xc000
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2007-03-04 14:09:21 +00:00
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#elif defined(IAUDIO_X5) || defined(IAUDIO_M5)
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2006-03-18 23:06:45 +00:00
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#define DRAMORIG 0x31000000 + STUBOFFSET
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#define IRAMORIG 0x10000000
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2006-11-09 21:15:49 +00:00
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#define IRAMSIZE 0x10000
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2006-11-22 00:41:30 +00:00
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#elif defined(CPU_PP)
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2005-12-12 13:21:08 +00:00
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#define DRAMORIG 0x00000000 + STUBOFFSET
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2005-11-12 15:29:43 +00:00
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#define IRAMORIG 0x40000000
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#define IRAMSIZE 0xc000
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2006-01-12 00:35:50 +00:00
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#elif CONFIG_CPU==PNX0101
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2006-02-12 23:16:05 +00:00
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#define DRAMORIG 0xc00000 + STUBOFFSET
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2007-11-02 05:21:34 +00:00
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#define IRAM0ORIG 0x000000
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#define IRAM0SIZE 0x7000
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2006-01-24 23:32:53 +00:00
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#define IRAMORIG 0x400000
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2006-08-12 22:43:44 +00:00
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#define IRAMSIZE 0x7000
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2006-02-24 15:42:52 +00:00
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#elif CONFIG_CPU==S3C2440
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2007-09-20 04:46:41 +00:00
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#define DRAMORIG 0x00000100 + STUBOFFSET
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2007-11-11 20:50:44 +00:00
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#define IRAMORIG DRAMORIG
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#define IRAM DRAM
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2007-11-11 17:58:13 +00:00
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#define IRAMSIZE 0x1000
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2007-09-20 04:46:41 +00:00
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#elif CONFIG_CPU==DM320
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#define DRAMORIG 0x00900000 + STUBOFFSET
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2007-09-30 20:52:39 +00:00
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#define IRAMORIG 0x00000000
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#define IRAMSIZE 0x4000
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2007-09-21 15:51:53 +00:00
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#elif CONFIG_CPU==IMX31L
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2007-11-27 15:40:29 +00:00
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#define DRAMORIG (0x88000000 + STUBOFFSET)
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2007-09-21 15:51:53 +00:00
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#define IRAMORIG 0x1FFFC000
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#define IRAMSIZE 0x4000
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2004-10-06 13:30:44 +00:00
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#else
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#define DRAMORIG 0x09000000 + STUBOFFSET
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#define IRAMORIG 0x0f000000
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#define IRAMSIZE 0x1000
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#endif
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2005-06-22 02:47:54 +00:00
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/* End of the audio buffer, where the codec buffer starts */
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#define ENDAUDIOADDR (DRAMORIG + DRAMSIZE)
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/* Where the codec buffer ends, and the plugin buffer starts */
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#define ENDADDR (ENDAUDIOADDR + CODECSIZE)
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2004-10-06 13:48:25 +00:00
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2002-08-01 08:12:17 +00:00
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MEMORY
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{
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2007-11-02 05:21:34 +00:00
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DRAM : ORIGIN = DRAMORIG, LENGTH = DRAMSIZE
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2007-11-11 20:50:44 +00:00
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#if CONFIG_CPU != S3C2440
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2007-11-02 05:21:34 +00:00
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IRAM : ORIGIN = IRAMORIG, LENGTH = IRAMSIZE
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2007-11-11 20:50:44 +00:00
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#endif
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2006-08-12 21:03:23 +00:00
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#if CONFIG_CPU==PNX0101
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2007-11-02 05:21:34 +00:00
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IRAM0 : ORIGIN = IRAM0ORIG, LENGTH = IRAM0SIZE
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2006-08-12 21:03:23 +00:00
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#endif
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2002-08-01 08:12:17 +00:00
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}
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2002-03-28 15:09:10 +00:00
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SECTIONS
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{
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2007-11-02 05:21:34 +00:00
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#if (CONFIG_CPU==DM320)
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.text :
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{
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loadaddress = .;
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_loadaddress = .;
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. = ALIGN(0x200);
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*(.init.text)
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*(.text*)
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*(.glue_7)
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*(.glue_7t)
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. = ALIGN(0x4);
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} > DRAM
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.rodata :
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{
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*(.rodata) /* problems without this, dunno why */
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*(.rodata*)
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*(.rodata.str1.1)
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*(.rodata.str1.4)
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. = ALIGN(0x4);
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/* Pseudo-allocate the copies of the data sections */
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_datacopy = .;
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} > DRAM
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/* TRICK ALERT! For RAM execution, we put the .data section at the
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same load address as the copy. Thus, we don't waste extra RAM
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when we don't actually need the copy. */
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.data : AT ( _datacopy )
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{
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_datastart = .;
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*(.data*)
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. = ALIGN(0x4);
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_dataend = .;
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} > DRAM
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/DISCARD/ :
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{
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*(.eh_frame)
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}
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.vectors IRAMORIG :
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{
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_vectorsstart = .;
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*(.vectors);
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_vectorsend = .;
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} > IRAM AT> DRAM
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_vectorscopy = LOADADDR(.vectors);
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.iram :
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{
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_iramstart = .;
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*(.icode)
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*(.irodata)
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*(.idata)
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_iramend = .;
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} > IRAM AT> DRAM
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_iramcopy = LOADADDR(.iram);
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.ibss (NOLOAD) :
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{
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_iedata = .;
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*(.ibss)
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. = ALIGN(0x4);
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_iend = .;
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} > IRAM
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.stack :
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{
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*(.stack)
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stackbegin = .;
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. += 0x2000;
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stackend = .;
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} > IRAM
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.bss ADDR(.data) + SIZEOF(.data) + SIZEOF(.iram) + SIZEOF(.vectors):
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{
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_edata = .;
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*(.bss*)
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*(COMMON)
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. = ALIGN(0x4);
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_end = .;
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} > DRAM
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2007-11-11 17:58:13 +00:00
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#elif CONFIG_CPU==S3C2440
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.text :
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{
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loadaddress = .;
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_loadaddress = .;
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. = ALIGN(0x200);
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*(.init.text)
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*(.text*)
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*(.glue_7)
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*(.glue_7t)
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. = ALIGN(0x4);
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} > DRAM
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.rodata :
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{
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*(.rodata) /* problems without this, dunno why */
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*(.rodata*)
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*(.rodata.str1.1)
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*(.rodata.str1.4)
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. = ALIGN(0x4);
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/* Pseudo-allocate the copies of the data sections */
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_datacopy = .;
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} > DRAM
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/* TRICK ALERT! For RAM execution, we put the .data section at the
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same load address as the copy. Thus, we don't waste extra RAM
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when we don't actually need the copy. */
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.data : AT ( _datacopy )
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{
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_datastart = .;
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*(.data*)
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. = ALIGN(0x4);
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_dataend = .;
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} > DRAM
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/DISCARD/ :
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{
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*(.eh_frame)
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}
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.vectors 0x0 :
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{
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_vectorsstart = .;
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*(.vectors);
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_vectorsend = .;
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} AT> DRAM
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_vectorscopy = LOADADDR(.vectors);
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2007-11-11 20:50:44 +00:00
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.iram :
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2007-11-11 17:58:13 +00:00
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{
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_iramstart = .;
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*(.icode)
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*(.irodata)
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*(.idata)
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_iramend = .;
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2007-11-11 20:50:44 +00:00
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} > DRAM
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2007-11-11 17:58:13 +00:00
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_iramcopy = LOADADDR(.iram);
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.ibss (NOLOAD) :
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{
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_iedata = .;
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*(.ibss)
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. = ALIGN(0x4);
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_iend = .;
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} > DRAM
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2007-11-11 20:50:44 +00:00
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.stack :
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2007-11-11 17:58:13 +00:00
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{
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*(.stack)
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stackbegin = .;
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. += 0x2000;
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stackend = .;
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} > DRAM
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.bss :
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{
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_edata = .;
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*(.bss*)
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*(COMMON)
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. = ALIGN(0x4);
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_end = .;
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} > DRAM
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#else /* End CONFIG_CPU */
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2007-09-20 04:46:41 +00:00
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#if !defined(CPU_ARM)
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2002-08-01 08:12:17 +00:00
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.vectors :
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2002-03-28 15:09:10 +00:00
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{
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2005-03-31 08:47:02 +00:00
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loadaddress = .;
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_loadaddress = .;
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2005-06-21 00:01:28 +00:00
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KEEP(*(.resetvectors));
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2002-05-29 09:12:34 +00:00
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*(.resetvectors);
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2005-06-21 00:01:28 +00:00
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KEEP(*(.vectors));
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2002-03-28 15:09:10 +00:00
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*(.vectors);
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2002-08-01 08:12:17 +00:00
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} > DRAM
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2002-05-02 14:05:51 +00:00
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.text :
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{
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2006-01-24 23:32:53 +00:00
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#else
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.text :
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{
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loadaddress = .;
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_loadaddress = .;
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#endif
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2004-07-24 17:56:38 +00:00
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. = ALIGN(0x200);
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*(.init.text)
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2005-06-21 00:01:28 +00:00
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*(.text*)
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2006-01-12 00:35:50 +00:00
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#ifdef CPU_ARM
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2005-11-12 15:29:43 +00:00
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*(.glue_7)
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*(.glue_7t)
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#endif
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2003-04-24 20:25:10 +00:00
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. = ALIGN(0x4);
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2002-08-01 08:12:17 +00:00
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} > DRAM
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2002-03-28 15:09:10 +00:00
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2004-07-24 17:56:38 +00:00
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.rodata :
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2002-05-02 14:05:51 +00:00
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{
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2005-06-21 00:01:28 +00:00
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*(.rodata) /* problems without this, dunno why */
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*(.rodata*)
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2004-10-07 08:37:25 +00:00
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*(.rodata.str1.1)
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2004-07-24 17:56:38 +00:00
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*(.rodata.str1.4)
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2004-01-28 20:43:31 +00:00
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. = ALIGN(0x4);
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2004-07-24 17:56:38 +00:00
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/* Pseudo-allocate the copies of the data sections */
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_datacopy = .;
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2002-08-01 08:12:17 +00:00
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} > DRAM
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2002-05-02 14:05:51 +00:00
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2004-07-24 17:56:38 +00:00
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/* TRICK ALERT! For RAM execution, we put the .data section at the
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same load address as the copy. Thus, we don't waste extra RAM
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when we don't actually need the copy. */
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.data : AT ( _datacopy )
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2002-05-02 14:05:51 +00:00
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{
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2004-07-24 17:56:38 +00:00
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_datastart = .;
|
2005-06-21 00:01:28 +00:00
|
|
|
*(.data*)
|
2003-04-24 20:25:10 +00:00
|
|
|
. = ALIGN(0x4);
|
2004-07-24 17:56:38 +00:00
|
|
|
_dataend = .;
|
2002-08-01 08:12:17 +00:00
|
|
|
} > DRAM
|
2002-05-24 15:37:26 +00:00
|
|
|
|
2007-01-13 02:24:15 +00:00
|
|
|
/DISCARD/ :
|
2005-07-24 15:32:28 +00:00
|
|
|
{
|
|
|
|
*(.eh_frame)
|
|
|
|
}
|
|
|
|
|
2007-09-20 04:46:41 +00:00
|
|
|
#if defined(CPU_ARM)
|
2006-01-24 23:32:53 +00:00
|
|
|
.vectors 0x0 :
|
|
|
|
{
|
|
|
|
_vectorsstart = .;
|
|
|
|
*(.vectors);
|
|
|
|
_vectorsend = .;
|
2006-08-12 21:03:23 +00:00
|
|
|
#if CONFIG_CPU==PNX0101
|
|
|
|
*(.dmabuf)
|
|
|
|
} >IRAM0 AT> DRAM
|
|
|
|
#else
|
2006-01-24 23:32:53 +00:00
|
|
|
} AT> DRAM
|
2006-08-12 21:03:23 +00:00
|
|
|
#endif
|
2006-01-24 23:32:53 +00:00
|
|
|
|
|
|
|
_vectorscopy = LOADADDR(.vectors);
|
|
|
|
#endif
|
|
|
|
|
|
|
|
#if CONFIG_CPU==PNX0101
|
|
|
|
.iram IRAMORIG + SIZEOF(.vectors) :
|
|
|
|
#else
|
|
|
|
.iram IRAMORIG :
|
|
|
|
#endif
|
2004-07-24 17:56:38 +00:00
|
|
|
{
|
|
|
|
_iramstart = .;
|
|
|
|
*(.icode)
|
2005-10-19 19:35:24 +00:00
|
|
|
*(.irodata)
|
2004-07-24 17:56:38 +00:00
|
|
|
*(.idata)
|
|
|
|
_iramend = .;
|
2006-01-24 23:32:53 +00:00
|
|
|
} > IRAM AT> DRAM
|
|
|
|
|
|
|
|
_iramcopy = LOADADDR(.iram);
|
2007-01-13 02:24:15 +00:00
|
|
|
|
2005-10-19 19:35:24 +00:00
|
|
|
.ibss (NOLOAD) :
|
|
|
|
{
|
|
|
|
_iedata = .;
|
|
|
|
*(.ibss)
|
|
|
|
. = ALIGN(0x4);
|
|
|
|
_iend = .;
|
|
|
|
} > IRAM
|
2004-07-24 17:56:38 +00:00
|
|
|
|
2006-01-12 00:35:50 +00:00
|
|
|
#if defined(CPU_COLDFIRE) || defined(CPU_ARM)
|
2006-08-03 16:44:45 +00:00
|
|
|
#ifdef CPU_PP
|
2007-09-28 10:20:02 +00:00
|
|
|
.idle_stacks :
|
|
|
|
{
|
|
|
|
*(.idle_stacks)
|
2007-09-29 07:32:41 +00:00
|
|
|
#if NUM_CORES > 1
|
2007-09-28 10:20:02 +00:00
|
|
|
cpu_idlestackbegin = .;
|
2007-09-29 06:17:33 +00:00
|
|
|
. += IDLE_STACK_SIZE;
|
2007-09-28 10:20:02 +00:00
|
|
|
cpu_idlestackend = .;
|
2007-09-29 06:17:33 +00:00
|
|
|
#endif
|
2007-09-28 10:20:02 +00:00
|
|
|
cop_idlestackbegin = .;
|
2007-09-29 06:17:33 +00:00
|
|
|
. += IDLE_STACK_SIZE;
|
2007-09-28 10:20:02 +00:00
|
|
|
cop_idlestackend = .;
|
|
|
|
} > IRAM
|
|
|
|
#endif
|
2006-08-03 16:29:42 +00:00
|
|
|
|
2007-11-27 01:20:26 +00:00
|
|
|
.stack :
|
|
|
|
{
|
|
|
|
*(.stack)
|
|
|
|
stackbegin = .;
|
|
|
|
. += 0x2000;
|
|
|
|
stackend = .;
|
|
|
|
} > IRAM
|
|
|
|
|
2005-03-01 12:25:30 +00:00
|
|
|
#else
|
2004-07-24 17:56:38 +00:00
|
|
|
/* TRICK ALERT! We want 0x2000 bytes of stack, but we set the section
|
|
|
|
size smaller, and allow the stack to grow into the .iram copy */
|
2004-08-09 21:35:57 +00:00
|
|
|
.stack ADDR(.data) + SIZEOF(.data) + SIZEOF(.iram):
|
2002-05-24 15:37:26 +00:00
|
|
|
{
|
|
|
|
*(.stack)
|
2004-08-09 21:35:57 +00:00
|
|
|
_stackbegin = . - SIZEOF(.iram);
|
|
|
|
. += 0x2000 - SIZEOF(.iram);
|
2002-07-15 22:15:00 +00:00
|
|
|
_stackend = .;
|
2002-08-01 08:12:17 +00:00
|
|
|
} > DRAM
|
2005-03-01 12:25:30 +00:00
|
|
|
#endif
|
2002-05-24 15:37:26 +00:00
|
|
|
|
2006-01-24 23:32:53 +00:00
|
|
|
#if defined(CPU_COLDFIRE)
|
2005-03-01 12:25:30 +00:00
|
|
|
.bss ADDR(.data) + SIZEOF(.data) + SIZEOF(.iram):
|
2007-11-11 17:58:13 +00:00
|
|
|
#elif defined(CPU_ARM)
|
2006-01-24 23:32:53 +00:00
|
|
|
.bss ADDR(.data) + SIZEOF(.data) + SIZEOF(.iram) + SIZEOF(.vectors):
|
2005-03-01 12:25:30 +00:00
|
|
|
#else
|
2002-08-01 08:58:17 +00:00
|
|
|
.bss :
|
2005-03-01 12:25:30 +00:00
|
|
|
#endif
|
2002-08-01 08:58:17 +00:00
|
|
|
{
|
|
|
|
_edata = .;
|
2005-06-21 00:01:28 +00:00
|
|
|
*(.bss*)
|
2002-08-01 08:58:17 +00:00
|
|
|
*(COMMON)
|
2005-03-18 07:53:52 +00:00
|
|
|
. = ALIGN(0x4);
|
2002-08-01 08:58:17 +00:00
|
|
|
_end = .;
|
|
|
|
} > DRAM
|
2007-11-02 05:21:34 +00:00
|
|
|
|
|
|
|
#endif
|
2002-08-01 08:58:17 +00:00
|
|
|
|
2005-04-05 11:33:58 +00:00
|
|
|
.audiobuf ALIGN(4) :
|
2002-05-24 15:37:26 +00:00
|
|
|
{
|
2005-04-05 11:33:58 +00:00
|
|
|
_audiobuffer = .;
|
|
|
|
audiobuffer = .;
|
2002-08-01 08:12:17 +00:00
|
|
|
} > DRAM
|
2002-05-24 15:37:26 +00:00
|
|
|
|
2005-06-22 02:47:54 +00:00
|
|
|
.audiobufend ENDAUDIOADDR:
|
2002-05-24 15:37:26 +00:00
|
|
|
{
|
2005-04-05 11:33:58 +00:00
|
|
|
audiobufend = .;
|
|
|
|
_audiobufend = .;
|
2002-08-01 08:12:17 +00:00
|
|
|
} > DRAM
|
2002-03-28 15:09:10 +00:00
|
|
|
|
2005-06-22 02:47:54 +00:00
|
|
|
.codec ENDAUDIOADDR:
|
|
|
|
{
|
|
|
|
codecbuf = .;
|
|
|
|
_codecbuf = .;
|
|
|
|
}
|
|
|
|
|
2003-06-29 16:33:04 +00:00
|
|
|
.plugin ENDADDR:
|
|
|
|
{
|
|
|
|
_pluginbuf = .;
|
2005-02-03 08:36:18 +00:00
|
|
|
pluginbuf = .;
|
2003-06-29 16:33:04 +00:00
|
|
|
}
|
2002-05-24 15:37:26 +00:00
|
|
|
}
|
2005-02-10 22:37:09 +00:00
|
|
|
|