4221a7f22f
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@22865 a1c6a512-1295-4272-9138-f99709370657
184 lines
5.7 KiB
C
184 lines
5.7 KiB
C
/***************************************************************************
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* __________ __ ___.
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* Open \______ \ ____ ____ | | _\_ |__ _______ ___
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* Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
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* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
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* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
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* \/ \/ \/ \/ \/
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* $Id$
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*
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* Copyright (C) 2002 by Linus Nielsen Feltzing
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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*
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* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
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* KIND, either express or implied.
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*
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****************************************************************************/
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#ifndef _MAS_H_
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#define _MAS_H_
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#define MAS_BANK_D0 0
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#define MAS_BANK_D1 1
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#define MAX_PEAK 0x8000
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/*
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MAS I2C defs
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*/
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#if (CONFIG_CODEC == MAS3587F) || (CONFIG_CODEC == MAS3539F)
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#define MAS_ADR 0x3c
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#define MAS_DEV_WRITE (MAS_ADR | 0x00)
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#define MAS_DEV_READ (MAS_ADR | 0x01)
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#elif CONFIG_CODEC == MAS3507D
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#define MAS_ADR 0x3a
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#define MAS_DEV_WRITE (MAS_ADR | 0x00)
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#define MAS_DEV_READ (MAS_ADR | 0x01)
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#endif
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/* registers..*/
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#if (CONFIG_CODEC == MAS3587F) || (CONFIG_CODEC == MAS3539F)
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#define MAS_DATA_WRITE 0x68
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#define MAS_DATA_READ 0x69
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#define MAS_CODEC_WRITE 0x6c
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#define MAS_CODEC_READ 0x6d
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#define MAS_CONTROL 0x6a
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#define MAS_DCCF 0x76
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#define MAS_DCFR 0x77
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#elif CONFIG_CODEC == MAS3507D
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#define MAS_DATA_WRITE 0x68
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#define MAS_DATA_READ 0x69
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#define MAS_CONTROL 0x6a
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#endif
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/*
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* MAS register
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*/
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#define MAS_REG_DCCF 0x8e
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#define MAS_REG_MUTE 0xaa
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#define MAS_REG_PIODATA 0xc8
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#define MAS_REG_StartUpConfig 0xe6
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#define MAS_REG_KPRESCALE 0xe7
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#if (CONFIG_CODEC == MAS3587F) || (CONFIG_CODEC == MAS3539F)
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#define MAS_REG_KMDB_SWITCH 0x21
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#define MAS_REG_KMDB_STR 0x22
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#define MAS_REG_KMDB_HAR 0x23
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#define MAS_REG_KMDB_FC 0x24
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#define MAS_REG_KLOUDNESS 0x1e
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#define MAS_REG_QPEAK_L 0x0a
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#define MAS_REG_QPEAK_R 0x0b
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#define MAS_REG_DQPEAK_L 0x0c
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#define MAS_REG_DQPEAK_R 0x0d
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#define MAS_REG_VOLUME_CONTROL 0x10
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#define MAS_REG_BALANCE 0x11
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#define MAS_REG_KAVC 0x12
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#define MAS_REG_KBASS 0x14
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#define MAS_REG_KTREBLE 0x15
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#elif CONFIG_CODEC == MAS3507D
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#define MAS_REG_KBASS 0x6b
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#define MAS_REG_KTREBLE 0x6f
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#endif
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/*
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* MAS commands
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*/
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#if (CONFIG_CODEC == MAS3587F) || (CONFIG_CODEC == MAS3539F)
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#define MAS_CMD_READ_ANCILLARY 0x50
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#define MAS_CMD_FAST_PRG_DL 0x60
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#define MAS_CMD_READ_IC_VER 0x70
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#define MAS_CMD_READ_REG 0xa0
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#define MAS_CMD_WRITE_REG 0xb0
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#define MAS_CMD_READ_D0_MEM 0xc0
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#define MAS_CMD_READ_D1_MEM 0xd0
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#define MAS_CMD_WRITE_D0_MEM 0xe0
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#define MAS_CMD_WRITE_D1_MEM 0xf0
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#elif CONFIG_CODEC == MAS3507D
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#define MAS_CMD_READ_ANCILLARY 0x30
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#define MAS_CMD_WRITE_REG 0x90
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#define MAS_CMD_WRITE_D0_MEM 0xa0
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#define MAS_CMD_WRITE_D1_MEM 0xb0
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#define MAS_CMD_READ_REG 0xd0
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#define MAS_CMD_READ_D0_MEM 0xe0
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#define MAS_CMD_READ_D1_MEM 0xf0
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#endif
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/*
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* MAS D0 memory cells (MAS3587F / MAS3539F)
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*/
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#if CONFIG_CODEC == MAS3587F
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#define MAS_D0_APP_SELECT 0x7f6
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#define MAS_D0_APP_RUNNING 0x7f7
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#define MAS_D0_ENCODER_CONTROL 0x7f0
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#define MAS_D0_IO_CONTROL_MAIN 0x7f1
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#define MAS_D0_INTERFACE_CONTROL 0x7f2
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#define MAS_D0_OFREQ_CONTROL 0x7f3
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#define MAS_D0_OUT_CLK_CONFIG 0x7f4
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#define MAS_D0_SPD_OUT_BITS 0x7f8
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#define MAS_D0_SOFT_MUTE 0x7f9
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#define MAS_D0_OUT_LL 0x7fc
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#define MAS_D0_OUT_LR 0x7fd
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#define MAS_D0_OUT_RL 0x7fe
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#define MAS_D0_OUT_RR 0x7ff
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#define MAS_D0_MPEG_FRAME_COUNT 0xfd0
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#define MAS_D0_MPEG_STATUS_1 0xfd1
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#define MAS_D0_MPEG_STATUS_2 0xfd2
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#define MAS_D0_CRC_ERROR_COUNT 0xfd3
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#elif CONFIG_CODEC == MAS3539F
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#define MAS_D0_APP_SELECT 0x34b
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#define MAS_D0_APP_RUNNING 0x34c
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/* no encoder :( */
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#define MAS_D0_IO_CONTROL_MAIN 0x346
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#define MAS_D0_INTERFACE_CONTROL 0x347
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#define MAS_D0_OFREQ_CONTROL 0x348
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#define MAS_D0_OUT_CLK_CONFIG 0x349
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#define MAS_D0_SPD_OUT_BITS 0x351
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#define MAS_D0_SOFT_MUTE 0x350
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#define MAS_D0_OUT_LL 0x354
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#define MAS_D0_OUT_LR 0x355
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#define MAS_D0_OUT_RL 0x356
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#define MAS_D0_OUT_RR 0x357
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#define MAS_D0_MPEG_FRAME_COUNT 0xfd0
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#define MAS_D0_MPEG_STATUS_1 0xfd1
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#define MAS_D0_MPEG_STATUS_2 0xfd2
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#define MAS_D0_CRC_ERROR_COUNT 0xfd3
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#elif CONFIG_CODEC == MAS3507D
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#define MAS_D0_MPEG_FRAME_COUNT 0x300
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#define MAS_D0_MPEG_STATUS_1 0x301
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#define MAS_D0_MPEG_STATUS_2 0x302
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#define MAS_D0_CRC_ERROR_COUNT 0x303
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#define MAS_D0_OUT_LL 0x7f8
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#define MAS_D0_OUT_LR 0x7f9
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#define MAS_D0_OUT_RL 0x7fa
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#define MAS_D0_OUT_RR 0x7fb
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#endif
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int mas_default_read(unsigned short *buf);
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int mas_run(unsigned short address);
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int mas_readmem(int bank, int addr, unsigned long* dest, int len);
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int mas_writemem(int bank, int addr, const unsigned long* src, int len);
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int mas_readreg(int reg);
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int mas_writereg(int reg, unsigned int val);
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void mas_reset(void);
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int mas_direct_config_read(unsigned char reg);
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int mas_direct_config_write(unsigned char reg, unsigned int val);
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int mas_codec_writereg(int reg, unsigned int val);
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int mas_codec_readreg(int reg);
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unsigned long mas_readver(void);
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#endif
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#if CONFIG_TUNER & S1A0903X01
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void mas_store_pllfreq(int freq);
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int mas_get_pllfreq(void);
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#endif
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