49ec9ea190
(patch by Denes Balatoni, FS#9499) git-svn-id: svn://svn.rockbox.org/rockbox/trunk@18827 a1c6a512-1295-4272-9138-f99709370657
108 lines
2.4 KiB
C
108 lines
2.4 KiB
C
/***************************************************************************
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* __________ __ ___.
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* Open \______ \ ____ ____ | | _\_ |__ _______ ___
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* Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
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* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
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* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
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* \/ \/ \/ \/ \/
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* $Id$
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*
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* Copyright (C) 2008 by Frank Gevaerts
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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*
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* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
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* KIND, either express or implied.
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*
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****************************************************************************/
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#include "qt1106.h"
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#include "cpu.h"
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#include "system.h"
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#define SPIDELAY(_x) void(_x);
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#define SETMOSI() (PDAT1 |= (1 << 6))
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#define CLRMOSI() (PDAT1 &= ~(1 << 6))
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#define MISO ((PDAT0 >> 3) & 1)
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#define RDY (PDAT1 & (1 << 5))
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#define SETCLK() (PDAT0 |= (1 << 1))
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#define CLRCLK() (PDAT0 &= ~(1 << 1))
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#define SETSS() (PDAT0 |= (1 << 0))
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#define CLRSS() (PDAT0 &= ~(1 << 0))
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#define CHANGE (PDAT0 & (1 << 4))
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void init_qt1106(void)
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{
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int oldval;
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oldval = PCON0;
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//Set P0.0 and P0.1 to output, set P0.3 and P0.4 to input
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PCON0 = ((oldval & ~(3 << 0 | 3 << 2 | 3 << 6 | 3 << 8)) | (1 << 0 | 1 << 2));
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oldval = PCON1;
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//Set P1.5 to input, set P1.6 to output
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PCON1 = ((oldval & ~(0xf << 20 | 0xf << 24)) | (1 << 24));
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SETSS();
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SETCLK();
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}
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static inline void delay(int duration)
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{
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volatile int i;
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for(i=0;i<duration;i++);
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}
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void qt1106_wait(void)
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{
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while(!(PDAT0 & (1 << 4))) {}
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}
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unsigned int qt1106_io(unsigned int output)
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{
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unsigned int input = 0;
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int i;
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while(!RDY) {}
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delay(10*100); // < 470 us
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CLRSS();
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delay(13*100); // > 22 us
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for (i = 0; i < 24; i++) {
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CLRCLK();
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if (output & (1 << 23))
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SETMOSI();
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else
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CLRMOSI();
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output <<= 1;
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delay(20*100); // >> 6.7 us
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SETCLK();
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input <<= 1;
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input |= MISO;
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delay(20*100); // >> 6.7 us
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}
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SETSS();
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return (input);
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}
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