fe2d52cc7d
Nothing in the core has used it for some time. It's exported to the plugin API but the last plugins to use it were switched to the mixer API back in 2011. This allows us to get rid of pcm_play_dma_pause() from all audio drivers Change-Id: Ic3fa02592316f84963e41d792d1cabb436d1ff6b
275 lines
7.2 KiB
C
275 lines
7.2 KiB
C
/***************************************************************************
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* __________ __ ___.
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* Open \______ \ ____ ____ | | _\_ |__ _______ ___
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* Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
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* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
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* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
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* \/ \/ \/ \/ \/
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* $Id$
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*
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* Copyright (C) 2006 by Michael Sevakis
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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*
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* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
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* KIND, either express or implied.
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*
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****************************************************************************/
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#include <stdlib.h>
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#include "config.h"
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#include "system.h"
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#include "kernel.h"
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#include "logf.h"
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#include "audio.h"
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#include "sound.h"
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#include "file.h"
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#include "pcm-internal.h"
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/* PCM interrupt routine lockout */
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static struct
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{
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int locked;
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unsigned long state;
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} dma_play_lock =
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{
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.locked = 0,
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.state = 0,
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};
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#define FIFO_COUNT ((IISFCON >> 6) & 0x3F)
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/* Setup for the DMA controller */
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#define DMA_CONTROL_SETUP ((1<<31) | (1<<29) | (1<<23) | (1<<22) | (1<<20))
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#ifdef HAVE_UDA1341
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/* for PCLK = 50 MHz, frame size = 32 */
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/* [prescaler, master clock rate] */
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static const unsigned char pcm_freq_parms[HW_NUM_FREQ][2] =
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{
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[HW_FREQ_44] = { 2, IISMOD_MASTER_CLOCK_384FS },
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[HW_FREQ_22] = { 8, IISMOD_MASTER_CLOCK_256FS },
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[HW_FREQ_11] = { 17, IISMOD_MASTER_CLOCK_256FS },
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};
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#endif
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/* DMA count has hit zero - no more data */
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/* Get more data from the callback and top off the FIFO */
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void fiq_handler(void) __attribute__((interrupt ("FIQ")));
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/* Mask the DMA interrupt */
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void pcm_play_lock(void)
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{
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if (++dma_play_lock.locked == 1)
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bitset32(&INTMSK, DMA2_MASK);
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}
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/* Unmask the DMA interrupt if enabled */
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void pcm_play_unlock(void)
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{
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if (--dma_play_lock.locked == 0)
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bitclr32(&INTMSK, dma_play_lock.state);
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}
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void pcm_play_dma_init(void)
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{
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/* There seem to be problems when changing the IIS interface configuration
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* when a clock is not present.
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*/
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bitset32(&CLKCON, 1<<17);
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#ifdef HAVE_UDA1341
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/* master, transmit mode, 16 bit samples, BCLK 32fs, PCLK */
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IISMOD = IISMOD_MASTER_CLOCK_PCLK | IISMOD_MASTER_MODE | IISMOD_TRANSMIT_MODE
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| IISMOD_16_BIT | IISMOD_MASTER_CLOCK_256FS | IISMOD_BIT_CLOCK_32FS;
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/* TX idle, enable prescaler */
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IISCON |= IISCON_TX_IDLE | IISCON_IIS_PRESCALER_ENABLE;
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#else
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/* slave, transmit mode, 16 bit samples - MCLK 384fs - use 16.9344Mhz -
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BCLK 32fs */
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IISMOD = (1<<9) | (1<<8) | (2<<6) | (1<<3) | (1<<2) | (1<<0);
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/* RX,TX off,on */
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IISCON |= (1<<3) | (1<<2);
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#endif
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bitclr32(&CLKCON, 1<<17);
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audiohw_init();
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/* init GPIO */
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#ifdef GIGABEAT_F
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/* GPCCON = (GPCCON & ~(3<<14)) | (1<<14); */
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S3C244_GPIO_CONFIG (GPCCON, 7, GPIO_OUTPUT);
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GPCDAT |= (1<<7);
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#endif
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/* GPE4=I2SDO, GPE3=I2SDI, GPE2=CDCLK, GPE1=I2SSCLK, GPE0=I2SLRCK */
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GPECON = (GPECON & ~0x3ff) | 0x2aa;
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/* Do not service DMA requests, yet */
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/* clear any pending int and mask it */
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bitset32(&INTMSK, DMA2_MASK);
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SRCPND = DMA2_MASK;
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/* connect to FIQ */
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bitset32(&INTMOD, DMA2_MASK);
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}
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void pcm_play_dma_postinit(void)
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{
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audiohw_postinit();
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}
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void pcm_dma_apply_settings(void)
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{
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#ifdef HAVE_UDA1341
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unsigned int reg_val;
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/* set prescaler and master clock rate according to freq */
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reg_val = (pcm_freq_parms [pcm_fsel][0] << 5) | pcm_freq_parms [pcm_fsel][0];
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IISMOD = (IISMOD & ~IISMOD_MASTER_CLOCK_384FS) | pcm_freq_parms [pcm_fsel][1] ;
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IISPSR = reg_val;
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#endif
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audiohw_set_frequency(pcm_fsel);
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}
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/* Connect the DMA and start filling the FIFO */
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static void play_start_pcm(void)
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{
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/* clear pending DMA interrupt */
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SRCPND = DMA2_MASK;
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/* Flush any pending writes */
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commit_dcache_range((char*)DISRC2-0x30000000, (DCON2 & 0xFFFFF) * 2);
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/* unmask DMA interrupt when unlocking */
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dma_play_lock.state = DMA2_MASK;
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/* turn on the request */
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IISCON |= (1<<5);
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/* Activate the channel */
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DMASKTRIG2 = 0x2;
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/* turn off the idle */
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IISCON &= ~(1<<3);
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#ifdef HAVE_UDA1341
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IISMOD = (IISMOD & ~IISMOD_MASTER_CLOCK_384FS) | pcm_freq_parms [pcm_fsel][1] ;
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IISPSR = (pcm_freq_parms [pcm_fsel][0] << 5) | pcm_freq_parms [pcm_fsel][0];
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#endif
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/* start the IIS */
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IISCON |= (1<<0);
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}
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/* Disconnect the DMA and wait for the FIFO to clear */
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static void play_stop_pcm(void)
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{
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/* Mask DMA interrupt */
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bitset32(&INTMSK, DMA2_MASK);
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/* De-Activate the DMA channel */
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DMASKTRIG2 = 0x4;
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/* are we playing? wait for the chunk to finish */
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if (dma_play_lock.state != 0)
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{
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/* wait for the FIFO to empty and DMA to stop */
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while ((IISCON & (1<<7)) || (DMASKTRIG2 & 0x2));
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}
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/* Keep interrupt masked when unlocking */
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dma_play_lock.state = 0;
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/* turn off the request */
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IISCON &= ~(1<<5);
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/* turn on the idle */
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IISCON |= (1<<3);
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/* stop the IIS */
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IISCON &= ~(1<<0);
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}
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void pcm_play_dma_start(const void *addr, size_t size)
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{
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/* Enable the IIS clock */
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bitset32(&CLKCON, 1<<17);
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/* stop any DMA in progress - idle IIS */
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play_stop_pcm();
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/* connect DMA to the FIFO and enable the FIFO */
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IISFCON = (1<<15) | (1<<13);
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/* set DMA dest */
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DIDST2 = (unsigned int)&IISFIFO;
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/* IIS is on the APB bus, INT when TC reaches 0, fixed dest addr */
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DIDSTC2 = 0x03;
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/* set DMA source and options */
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DISRC2 = (unsigned int)addr + 0x30000000;
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/* How many transfers to make - we transfer half-word at a time = 2 bytes */
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/* DMA control: CURR_TC int, single service mode, I2SSDO int, HW trig */
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/* no auto-reload, half-word (16bit) */
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DCON2 = DMA_CONTROL_SETUP | (size / 2);
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DISRCC2 = 0x00; /* memory is on AHB bus, increment addresses */
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play_start_pcm();
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}
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/* Promptly stop DMA transfers and stop IIS */
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void pcm_play_dma_stop(void)
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{
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play_stop_pcm();
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/* Disconnect the IIS clock */
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bitclr32(&CLKCON, 1<<17);
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}
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void fiq_handler(void)
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{
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static const void *start;
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static size_t size;
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/* clear any pending interrupt */
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SRCPND = DMA2_MASK;
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/* Buffer empty. Try to get more. */
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if (!pcm_play_dma_complete_callback(PCM_DMAST_OK, &start, &size))
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return;
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/* Flush any pending cache writes */
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commit_dcache_range(start, size);
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/* set the new DMA values */
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DCON2 = DMA_CONTROL_SETUP | (size >> 1);
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DISRC2 = (unsigned int)start + 0x30000000;
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/* Re-Activate the channel */
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DMASKTRIG2 = 0x2;
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pcm_play_dma_status_callback(PCM_DMAST_STARTED);
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}
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size_t pcm_get_bytes_waiting(void)
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{
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/* lie a little and only return full pairs */
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return (DSTAT2 & 0xFFFFE) * 2;
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}
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const void * pcm_play_dma_get_peak_buffer(int *count)
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{
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unsigned long addr = DCSRC2;
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int cnt = DSTAT2;
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*count = (cnt & 0xFFFFF) >> 1;
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return (void *)((addr + 2) & ~3);
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}
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