8768ee82cc
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@13647 a1c6a512-1295-4272-9138-f99709370657
300 lines
8.2 KiB
C
300 lines
8.2 KiB
C
/***************************************************************************
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* __________ __ ___.
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* Open \______ \ ____ ____ | | _\_ |__ _______ ___
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* Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
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* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
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* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
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* \/ \/ \/ \/ \/
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* $Id$
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*
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* Copyright (C) 2002 by Alan Korr
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*
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* All files in this archive are subject to the GNU General Public License.
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* See the file COPYING in the source tree root for full license agreement.
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*
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* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
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* KIND, either express or implied.
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*
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****************************************************************************/
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#include "system.h"
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#include "thread.h"
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unsigned int ipod_hw_rev;
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#if NUM_CORES > 1
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struct mutex boostctrl_mtx NOCACHEBSS_ATTR;
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#endif
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#ifndef BOOTLOADER
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extern void TIMER1(void);
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extern void TIMER2(void);
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#if defined(IPOD_MINI) /* mini 1 only, mini 2G uses iPod 4G code */
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extern void ipod_mini_button_int(void);
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void irq(void)
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{
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if(CURRENT_CORE == CPU)
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{
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if (CPU_INT_STAT & TIMER1_MASK)
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TIMER1();
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else if (CPU_INT_STAT & TIMER2_MASK)
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TIMER2();
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else if (CPU_HI_INT_STAT & GPIO_MASK)
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ipod_mini_button_int();
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} else {
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if (COP_INT_STAT & TIMER1_MASK)
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TIMER1();
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else if (COP_INT_STAT & TIMER2_MASK)
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TIMER2();
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else if (COP_HI_INT_STAT & GPIO_MASK)
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ipod_mini_button_int();
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}
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}
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#elif (defined IRIVER_H10) || (defined IRIVER_H10_5GB) || defined(ELIO_TPJ1022) \
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|| (defined SANSA_E200)
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/* TODO: this should really be in the target tree, but moving it there caused
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crt0.S not to find it while linking */
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/* TODO: Even if it isn't in the target tree, this should be the default case */
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extern void button_int(void);
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extern void clickwheel_int(void);
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void irq(void)
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{
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if(CURRENT_CORE == CPU) {
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if (CPU_INT_STAT & TIMER1_MASK) {
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TIMER1();
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}
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else if (CPU_INT_STAT & TIMER2_MASK)
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TIMER2();
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#ifdef SANSA_E200
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else if (CPU_HI_INT_STAT & GPIO1_MASK)
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{
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if (GPIOF_INT_STAT & 0xff)
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button_int();
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if (GPIOH_INT_STAT & 0xc0)
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clickwheel_int();
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}
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#endif
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} else {
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if (COP_INT_STAT & TIMER1_MASK)
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TIMER1();
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else if (COP_INT_STAT & TIMER2_MASK)
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TIMER2();
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}
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}
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#else
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extern void ipod_4g_button_int(void);
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void irq(void)
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{
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if(CURRENT_CORE == CPU)
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{
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if (CPU_INT_STAT & TIMER1_MASK)
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TIMER1();
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else if (CPU_INT_STAT & TIMER2_MASK)
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TIMER2();
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else if (CPU_HI_INT_STAT & I2C_MASK)
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ipod_4g_button_int();
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} else {
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if (COP_INT_STAT & TIMER1_MASK)
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TIMER1();
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else if (COP_INT_STAT & TIMER2_MASK)
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TIMER2();
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else if (COP_HI_INT_STAT & I2C_MASK)
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ipod_4g_button_int();
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}
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}
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#endif
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#endif /* BOOTLOADER */
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/* TODO: The following two function have been lifted straight from IPL, and
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hence have a lot of numeric addresses used straight. I'd like to use
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#defines for these, but don't know what most of them are for or even what
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they should be named. Because of this I also have no way of knowing how
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to extend the funtions to do alternate cache configurations and/or
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some other CPU frequency scaling. */
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#ifndef BOOTLOADER
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static void ipod_init_cache(void)
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{
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/* Initialising the cache in the iPod bootloader prevents Rockbox from starting */
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unsigned i;
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/* cache init mode? */
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CACHE_CTL = CACHE_INIT;
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/* PP5002 has 8KB cache */
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for (i = 0xf0004000; i < 0xf0006000; i += 16) {
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outl(0x0, i);
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}
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outl(0x0, 0xf000f040);
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outl(0x3fc0, 0xf000f044);
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/* enable cache */
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CACHE_CTL = CACHE_ENABLE;
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for (i = 0x10000000; i < 0x10002000; i += 16)
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inb(i);
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}
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#endif
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/* Not all iPod targets support CPU freq. boosting yet */
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#ifdef HAVE_ADJUSTABLE_CPU_FREQ
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void set_cpu_frequency(long frequency)
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{
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unsigned long postmult;
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# if NUM_CORES > 1
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/* Using mutex or spinlock isn't safe here. */
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while (test_and_set(&boostctrl_mtx.locked, 1)) ;
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# endif
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if (frequency == CPUFREQ_NORMAL)
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postmult = CPUFREQ_NORMAL_MULT;
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else if (frequency == CPUFREQ_MAX)
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postmult = CPUFREQ_MAX_MULT;
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else
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postmult = CPUFREQ_DEFAULT_MULT;
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cpu_frequency = frequency;
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/* Enable PLL? */
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outl(inl(0x70000020) | (1<<30), 0x70000020);
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/* Select 24MHz crystal as clock source? */
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outl((inl(0x60006020) & 0x0fffff0f) | 0x20000020, 0x60006020);
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/* Clock frequency = (24/8)*postmult */
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outl(0xaa020000 | 8 | (postmult << 8), 0x60006034);
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/* Wait for PLL relock? */
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udelay(2000);
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/* Select PLL as clock source? */
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outl((inl(0x60006020) & 0x0fffff0f) | 0x20000070, 0x60006020);
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# if defined(IPOD_COLOR) || defined(IPOD_4G) || defined(IPOD_MINI) || defined(IRIVER_H10) || defined(IRIVER_H10_5GB)
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/* We don't know why the timer interrupt gets disabled on the PP5020
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based ipods, but without the following line, the 4Gs will freeze
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when CPU frequency changing is enabled.
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Note also that a simple "CPU_INT_EN = TIMER1_MASK;" (as used
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elsewhere to enable interrupts) doesn't work, we need "|=".
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It's not needed on the PP5021 and PP5022 ipods.
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*/
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/* unmask interrupt source */
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CPU_INT_EN |= TIMER1_MASK;
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COP_INT_EN |= TIMER1_MASK;
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# endif
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# if NUM_CORES > 1
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boostctrl_mtx.locked = 0;
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# endif
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}
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#elif !defined(BOOTLOADER)
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void ipod_set_cpu_frequency(void)
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{
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/* For e200, just use clocking set up by OF loader for now */
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#ifndef SANSA_E200
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/* Enable PLL? */
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outl(inl(0x70000020) | (1<<30), 0x70000020);
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/* Select 24MHz crystal as clock source? */
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outl((inl(0x60006020) & 0x0fffff0f) | 0x20000020, 0x60006020);
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/* Clock frequency = (24/8)*25 = 75MHz */
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outl(0xaa020000 | 8 | (25 << 8), 0x60006034);
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/* Wait for PLL relock? */
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udelay(2000);
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/* Select PLL as clock source? */
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outl((inl(0x60006020) & 0x0fffff0f) | 0x20000070, 0x60006020);
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#endif /* SANSA_E200 */
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}
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#endif
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void system_init(void)
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{
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#ifndef BOOTLOADER
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if (CURRENT_CORE == CPU)
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{
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#ifdef SANSA_E200
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/* Reset all devices */
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DEV_RS = 0x3bfffef8;
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outl(0xffffffff, 0x60006008);
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DEV_RS = 0;
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outl(0x00000000, 0x60006008);
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#endif
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/* Remap the flash ROM from 0x00000000 to 0x20000000. */
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MMAP3_LOGICAL = 0x20000000 | 0x3a00;
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MMAP3_PHYSICAL = 0x00000000 | 0x3f84;
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/* The hw revision is written to the last 4 bytes of SDRAM by the
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bootloader - we save it before Rockbox overwrites it. */
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ipod_hw_rev = (*((volatile unsigned long*)(0x01fffffc)));
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/* disable all irqs */
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COP_HI_INT_CLR = -1;
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CPU_HI_INT_CLR = -1;
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HI_INT_FORCED_CLR = -1;
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COP_INT_CLR = -1;
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CPU_INT_CLR = -1;
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INT_FORCED_CLR = -1;
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GPIOA_INT_EN = 0;
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GPIOB_INT_EN = 0;
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GPIOC_INT_EN = 0;
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GPIOD_INT_EN = 0;
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GPIOE_INT_EN = 0;
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GPIOF_INT_EN = 0;
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GPIOG_INT_EN = 0;
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GPIOH_INT_EN = 0;
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GPIOI_INT_EN = 0;
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GPIOJ_INT_EN = 0;
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GPIOK_INT_EN = 0;
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GPIOL_INT_EN = 0;
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#ifdef SANSA_E200
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/* outl(0x00000000, 0x6000b000); */
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outl(inl(0x6000a000) | 0x80000000, 0x6000a000); /* Init DMA controller? */
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}
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ipod_init_cache();
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#else /* !sansa E200 */
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# if NUM_CORES > 1 && defined(HAVE_ADJUSTABLE_CPU_FREQ)
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spinlock_init(&boostctrl_mtx);
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# endif
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#if (!defined HAVE_ADJUSTABLE_CPU_FREQ) && (NUM_CORES == 1)
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ipod_set_cpu_frequency();
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#endif
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}
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#if (!defined HAVE_ADJUSTABLE_CPU_FREQ) && (NUM_CORES > 1)
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else
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{
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ipod_set_cpu_frequency();
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}
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#endif
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ipod_init_cache();
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#endif /* SANSA_E200 */
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#endif /* BOOTLOADER */
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}
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void system_reboot(void)
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{
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/* Reboot */
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DEV_RS |= DEV_SYSTEM;
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}
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int system_memory_guard(int newmode)
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{
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(void)newmode;
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return 0;
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}
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