691 lines
18 KiB
C
691 lines
18 KiB
C
/***************************************************************************
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* __________ __ ___.
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* Open \______ \ ____ ____ | | _\_ |__ _______ ___
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* Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
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* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
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* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
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* \/ \/ \/ \/ \/
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* $Id$
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*
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* Copyright (C) 2016 by Roman Stolyarov
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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*
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* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
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* KIND, either express or implied.
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*
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****************************************************************************/
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#include "config.h"
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#include "cpu.h"
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#include "nand.h"
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#include "nand_id.h"
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#include "system.h"
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#include "panic.h"
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#include "kernel.h"
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#include "storage.h"
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#include "string.h"
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/*#define LOGF_ENABLE*/
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#include "logf.h"
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//#define USE_DMA
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//#define USE_ECC
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/*
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* Standard NAND flash commands
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*/
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#define NAND_CMD_READ0 0
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#define NAND_CMD_READ1 1
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#define NAND_CMD_RNDOUT 5
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#define NAND_CMD_PAGEPROG 0x10
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#define NAND_CMD_READOOB 0x50
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#define NAND_CMD_ERASE1 0x60
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#define NAND_CMD_STATUS 0x70
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#define NAND_CMD_STATUS_MULTI 0x71
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#define NAND_CMD_SEQIN 0x80
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#define NAND_CMD_RNDIN 0x85
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#define NAND_CMD_READID 0x90
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#define NAND_CMD_ERASE2 0xd0
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#define NAND_CMD_RESET 0xff
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/* Extended commands for large page devices */
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#define NAND_CMD_READSTART 0x30
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#define NAND_CMD_RNDOUTSTART 0xE0
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#define NAND_CMD_CACHEDPROG 0x15
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/* Status bits */
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#define NAND_STATUS_FAIL 0x01
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#define NAND_STATUS_FAIL_N1 0x02
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#define NAND_STATUS_TRUE_READY 0x20
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#define NAND_STATUS_READY 0x40
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#define NAND_STATUS_WP 0x80
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/*
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* NAND parameter struct
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*/
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struct nand_param {
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unsigned int bus_width; /* data bus width: 8-bit/16-bit */
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unsigned int row_cycle; /* row address cycles: 2/3 */
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unsigned int page_size; /* page size in bytes: 512/2048/4096 */
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unsigned int oob_size; /* oob size in bytes: 16/64/128 */
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unsigned int page_per_block; /* pages per block: 32/64/128 */
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unsigned int bad_block_pos; /* bad block pos in oob: 0/5 */
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};
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/*
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* jz4760_nand.c
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*
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* NAND read routine for JZ4760
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*
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* Copyright (c) 2005-2008 Ingenic Semiconductor Inc.
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*
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*/
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#define CFG_NAND_BASE 0xBA000000
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#define NAND_ADDR_OFFSET 0x00800000
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#define NAND_CMD_OFFSET 0x00400000
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#define CFG_NAND_SMCR1 0x0d444400
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#define NAND_DATAPORT CFG_NAND_BASE
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#define NAND_ADDRPORT (CFG_NAND_BASE | NAND_ADDR_OFFSET)
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#define NAND_COMMPORT (CFG_NAND_BASE | NAND_CMD_OFFSET)
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#define ECC_BLOCK 512
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#define ECC_POS 24
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#define PAR_SIZE 13
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#define __nand_cmd(n) (REG8(NAND_COMMPORT) = (n))
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#define __nand_addr(n) (REG8(NAND_ADDRPORT) = (n))
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#define __nand_data8() (REG8(NAND_DATAPORT))
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#define __nand_data16() (REG16(NAND_DATAPORT))
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#define __nand_select() (REG_NEMC_NFCSR |= NEMC_NFCSR_NFE1 | NEMC_NFCSR_NFCE1)
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#define __nand_deselect() (REG_NEMC_NFCSR &= ~(NEMC_NFCSR_NFE1 | NEMC_NFCSR_NFCE1))
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/*--------------------------------------------------------------*/
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static struct nand_info* chip_info = NULL;
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static struct nand_info* bank;
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static unsigned long nand_size;
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static struct nand_param internal_param;
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static struct mutex nand_mtx;
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#ifdef USE_DMA
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static struct mutex nand_dma_mtx;
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static struct semaphore nand_dma_complete;
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#endif
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static unsigned char temp_page[2048]; /* Max page size */
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static inline void jz_nand_wait_ready(void)
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{
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unsigned int timeout = 1000;
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while ((REG_GPIO_PXPIN(0) & 0x00100000) && timeout--);
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while (!(REG_GPIO_PXPIN(0) & 0x00100000));
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}
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#ifndef USE_DMA
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static inline void jz_nand_read_buf16(void *buf, int count)
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{
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register int i;
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register unsigned short *p = (unsigned short *)buf;
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for (i = 0; i < count; i += 2)
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*p++ = __nand_data16();
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}
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static inline void jz_nand_read_buf8(void *buf, int count)
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{
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register int i;
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register unsigned char *p = (unsigned char *)buf;
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for (i = 0; i < count; i++)
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*p++ = __nand_data8();
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}
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#else
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static void jz_nand_write_dma(void *source, unsigned int len, int bw)
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{
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mutex_lock(&nand_dma_mtx);
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if(((unsigned int)source < 0xa0000000) && len)
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dma_cache_wback_inv((unsigned long)source, len);
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dma_enable();
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REG_DMAC_DCCSR(DMA_NAND_CHANNEL) = DMAC_DCCSR_NDES;
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REG_DMAC_DSAR(DMA_NAND_CHANNEL) = PHYSADDR((unsigned long)source);
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REG_DMAC_DTAR(DMA_NAND_CHANNEL) = PHYSADDR((unsigned long)NAND_DATAPORT);
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REG_DMAC_DTCR(DMA_NAND_CHANNEL) = len / 16;
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REG_DMAC_DRSR(DMA_NAND_CHANNEL) = DMAC_DRSR_RS_AUTO;
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REG_DMAC_DCMD(DMA_NAND_CHANNEL) = (DMAC_DCMD_SAI| DMAC_DCMD_DAI | DMAC_DCMD_SWDH_32 | DMAC_DCMD_DS_16BYTE |
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(bw == 8 ? DMAC_DCMD_DWDH_8 : DMAC_DCMD_DWDH_16));
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REG_DMAC_DCCSR(DMA_NAND_CHANNEL) |= DMAC_DCCSR_EN; /* Enable DMA channel */
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#if 1
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while( REG_DMAC_DTCR(DMA_NAND_CHANNEL) )
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yield();
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#else
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REG_DMAC_DCMD(DMA_NAND_CHANNEL) |= DMAC_DCMD_TIE; /* Enable DMA interrupt */
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semaphore_wait(&nand_dma_complete, TIMEOUT_BLOCK);
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#endif
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REG_DMAC_DCCSR(DMA_NAND_CHANNEL) &= ~DMAC_DCCSR_EN; /* Disable DMA channel */
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dma_disable();
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mutex_unlock(&nand_dma_mtx);
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}
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static void jz_nand_read_dma(void *target, unsigned int len, int bw)
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{
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mutex_lock(&nand_dma_mtx);
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if(((unsigned int)target < 0xa0000000) && len)
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dma_cache_wback_inv((unsigned long)target, len);
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dma_enable();
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REG_DMAC_DCCSR(DMA_NAND_CHANNEL) = DMAC_DCCSR_NDES ;
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REG_DMAC_DSAR(DMA_NAND_CHANNEL) = PHYSADDR((unsigned long)NAND_DATAPORT);
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REG_DMAC_DTAR(DMA_NAND_CHANNEL) = PHYSADDR((unsigned long)target);
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REG_DMAC_DTCR(DMA_NAND_CHANNEL) = len / 4;
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REG_DMAC_DRSR(DMA_NAND_CHANNEL) = DMAC_DRSR_RS_AUTO;
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REG_DMAC_DCMD(DMA_NAND_CHANNEL) = (DMAC_DCMD_SAI| DMAC_DCMD_DAI | DMAC_DCMD_DWDH_32 | DMAC_DCMD_DS_32BIT |
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(bw == 8 ? DMAC_DCMD_SWDH_8 : DMAC_DCMD_SWDH_16));
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REG_DMAC_DCCSR(DMA_NAND_CHANNEL) |= DMAC_DCCSR_EN; /* Enable DMA channel */
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#if 1
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while( REG_DMAC_DTCR(DMA_NAND_CHANNEL) )
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yield();
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#else
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REG_DMAC_DCMD(DMA_NAND_CHANNEL) |= DMAC_DCMD_TIE; /* Enable DMA interrupt */
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semaphore_wait(&nand_dma_complete, TIMEOUT_BLOCK);
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#endif
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//REG_DMAC_DCCSR(DMA_NAND_CHANNEL) &= ~DMAC_DCCSR_EN; /* Disable DMA channel */
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dma_disable();
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mutex_unlock(&nand_dma_mtx);
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}
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void DMA_CALLBACK(DMA_NAND_CHANNEL)(void)
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{
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if (REG_DMAC_DCCSR(DMA_NAND_CHANNEL) & DMAC_DCCSR_HLT)
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REG_DMAC_DCCSR(DMA_NAND_CHANNEL) &= ~DMAC_DCCSR_HLT;
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if (REG_DMAC_DCCSR(DMA_NAND_CHANNEL) & DMAC_DCCSR_AR)
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REG_DMAC_DCCSR(DMA_NAND_CHANNEL) &= ~DMAC_DCCSR_AR;
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if (REG_DMAC_DCCSR(DMA_NAND_CHANNEL) & DMAC_DCCSR_CT)
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REG_DMAC_DCCSR(DMA_NAND_CHANNEL) &= ~DMAC_DCCSR_CT;
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if (REG_DMAC_DCCSR(DMA_NAND_CHANNEL) & DMAC_DCCSR_TT)
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REG_DMAC_DCCSR(DMA_NAND_CHANNEL) &= ~DMAC_DCCSR_TT;
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semaphore_release(&nand_dma_complete);
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}
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#endif /* USE_DMA */
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static inline void jz_nand_read_buf(void *buf, int count, int bw)
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{
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#ifdef USE_DMA
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if (bw == 8)
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jz_nand_read_dma(buf, count, 8);
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else
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jz_nand_read_dma(buf, count, 16);
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#else
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if (bw == 8)
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jz_nand_read_buf8(buf, count);
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else
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jz_nand_read_buf16(buf, count);
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#endif
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}
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#ifdef USE_ECC
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/*
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* Correct 1~9-bit errors in 512-bytes data
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*/
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static void jz_rs_correct(unsigned char *dat, int idx, int mask)
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{
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int i, j;
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unsigned short d, d1, dm;
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i = (idx * 9) >> 3;
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j = (idx * 9) & 0x7;
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i = (j == 0) ? (i - 1) : i;
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j = (j == 0) ? 7 : (j - 1);
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if (i > 512)
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return;
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if (i == 512)
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d = dat[i - 1];
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else
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d = (dat[i] << 8) | dat[i - 1];
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d1 = (d >> j) & 0x1ff;
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d1 ^= mask;
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dm = ~(0x1ff << j);
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d = (d & dm) | (d1 << j);
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dat[i - 1] = d & 0xff;
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if (i < 512)
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dat[i] = (d >> 8) & 0xff;
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}
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#endif
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/*
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* Read oob
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*/
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static int jz_nand_read_oob(unsigned long page_addr, unsigned char *buf, int size)
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{
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struct nand_param *nandp = &internal_param;
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int page_size, row_cycle, bus_width;
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int col_addr;
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page_size = nandp->page_size;
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row_cycle = nandp->row_cycle;
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bus_width = nandp->bus_width;
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if (page_size >= 2048)
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col_addr = page_size;
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else
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col_addr = 0;
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if (page_size >= 2048)
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/* Send READ0 command */
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__nand_cmd(NAND_CMD_READ0);
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else
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/* Send READOOB command */
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__nand_cmd(NAND_CMD_READOOB);
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/* Send column address */
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__nand_addr(col_addr & 0xff);
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if (page_size >= 2048)
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__nand_addr((col_addr >> 8) & 0xff);
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/* Send page address */
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__nand_addr(page_addr & 0xff);
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__nand_addr((page_addr >> 8) & 0xff);
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if (row_cycle == 3)
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__nand_addr((page_addr >> 16) & 0xff);
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/* Send READSTART command for 2048 ps NAND */
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if (page_size >= 2048)
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__nand_cmd(NAND_CMD_READSTART);
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/* Wait for device ready */
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jz_nand_wait_ready();
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/* Read oob data */
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jz_nand_read_buf(buf, size, bus_width);
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return 0;
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}
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/*
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* nand_read_page()
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*
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* Input:
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*
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* block - block number: 0, 1, 2, ...
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* page - page number within a block: 0, 1, 2, ...
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* dst - pointer to target buffer
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*/
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static int jz_nand_read_page(unsigned long page_addr, unsigned char *dst)
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{
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struct nand_param *nandp = &internal_param;
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int page_size, oob_size;
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int row_cycle, bus_width, ecc_count;
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int i;
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#ifdef USE_ECC
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int j;
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#endif
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unsigned char *data_buf;
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unsigned char oob_buf[nandp->oob_size];
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page_size = nandp->page_size;
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oob_size = nandp->oob_size;
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row_cycle = nandp->row_cycle;
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bus_width = nandp->bus_width;
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/*
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* Read oob data
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*/
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jz_nand_read_oob(page_addr, oob_buf, oob_size);
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/*
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* Read page data
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*/
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/* Send READ0 command */
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__nand_cmd(NAND_CMD_READ0);
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/* Send column address */
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__nand_addr(0);
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if (page_size >= 2048)
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__nand_addr(0);
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/* Send page address */
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__nand_addr(page_addr & 0xff);
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__nand_addr((page_addr >> 8) & 0xff);
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if (row_cycle >= 3)
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__nand_addr((page_addr >> 16) & 0xff);
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/* Send READSTART command for 2048 ps NAND */
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if (page_size >= 2048)
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__nand_cmd(NAND_CMD_READSTART);
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/* Wait for device ready */
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jz_nand_wait_ready();
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/* Read page data */
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data_buf = dst;
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ecc_count = page_size / ECC_BLOCK;
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for (i = 0; i < ecc_count; i++)
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{
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#ifdef USE_ECC
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volatile unsigned char *paraddr = (volatile unsigned char *)EMC_NFPAR0;
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unsigned int stat;
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/* Enable RS decoding */
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REG_EMC_NFINTS = 0x0;
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__ecc_decoding_4bit();
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#endif
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/* Read data */
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jz_nand_read_buf((void *)data_buf, ECC_BLOCK, bus_width);
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#ifdef USE_ECC
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/* Set PAR values */
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for (j = 0; j < PAR_SIZE; j++)
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*paraddr++ = oob_buf[ECC_POS + i*PAR_SIZE + j];
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/* Set PRDY */
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REG_EMC_NFECR |= EMC_NFECR_PRDY;
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/* Wait for completion */
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__ecc_decode_sync();
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/* Disable decoding */
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__ecc_disable();
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/* Check result of decoding */
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stat = REG_EMC_NFINTS;
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if (stat & EMC_NFINTS_ERR)
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{
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/* Error occurred */
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if (stat & EMC_NFINTS_UNCOR)
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{
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/* Uncorrectable error occurred */
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logf("Uncorrectable ECC error at NAND page address 0x%lx", page_addr);
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return -1;
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}
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else
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{
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unsigned int errcnt, index, mask;
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errcnt = (stat & EMC_NFINTS_ERRCNT_MASK) >> EMC_NFINTS_ERRCNT_BIT;
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switch (errcnt)
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{
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case 4:
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index = (REG_EMC_NFERR3 & EMC_NFERR_INDEX_MASK) >> EMC_NFERR_INDEX_BIT;
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mask = (REG_EMC_NFERR3 & EMC_NFERR_MASK_MASK) >> EMC_NFERR_MASK_BIT;
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jz_rs_correct(data_buf, index, mask);
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case 3:
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index = (REG_EMC_NFERR2 & EMC_NFERR_INDEX_MASK) >> EMC_NFERR_INDEX_BIT;
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mask = (REG_EMC_NFERR2 & EMC_NFERR_MASK_MASK) >> EMC_NFERR_MASK_BIT;
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jz_rs_correct(data_buf, index, mask);
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case 2:
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index = (REG_EMC_NFERR1 & EMC_NFERR_INDEX_MASK) >> EMC_NFERR_INDEX_BIT;
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mask = (REG_EMC_NFERR1 & EMC_NFERR_MASK_MASK) >> EMC_NFERR_MASK_BIT;
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jz_rs_correct(data_buf, index, mask);
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case 1:
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index = (REG_EMC_NFERR0 & EMC_NFERR_INDEX_MASK) >> EMC_NFERR_INDEX_BIT;
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mask = (REG_EMC_NFERR0 & EMC_NFERR_MASK_MASK) >> EMC_NFERR_MASK_BIT;
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jz_rs_correct(data_buf, index, mask);
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break;
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default:
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break;
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}
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}
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}
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#endif
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data_buf += ECC_BLOCK;
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}
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return 0;
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}
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static int jz_nand_init(void)
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{
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unsigned char cData[5];
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__gpio_as_nand_16bit(1);
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REG_NEMC_SMCR1 = CFG_NAND_SMCR1 | 0x40;
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__nand_select();
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__nand_cmd(NAND_CMD_READID);
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__nand_addr(NAND_CMD_READ0);
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cData[0] = __nand_data8();
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cData[1] = __nand_data8();
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cData[2] = __nand_data8();
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cData[3] = __nand_data8();
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cData[4] = __nand_data8();
|
|
|
|
__nand_deselect();
|
|
|
|
logf("NAND chip %d: 0x%x 0x%x 0x%x 0x%x 0x%x", i+1, cData[0], cData[1],
|
|
cData[2], cData[3], cData[4]);
|
|
|
|
bank = nand_identify(cData);
|
|
|
|
if(bank == NULL)
|
|
{
|
|
panicf("Unknown NAND flash chip: 0x%x 0x%x 0x%x 0x%x 0x%x", cData[0],
|
|
cData[1], cData[2], cData[3], cData[4]);
|
|
return -1; /* panicf() doesn't return though */
|
|
}
|
|
|
|
chip_info = bank;
|
|
|
|
internal_param.bus_width = 16;
|
|
internal_param.row_cycle = chip_info->row_cycles;
|
|
internal_param.page_size = chip_info->page_size;
|
|
internal_param.oob_size = chip_info->spare_size;
|
|
internal_param.page_per_block = chip_info->pages_per_block;
|
|
internal_param.bad_block_pos = 0;
|
|
|
|
nand_size = ((chip_info->page_size * chip_info->blocks_per_bank * chip_info->pages_per_block) - 0x200000) / 512;
|
|
|
|
return 0;
|
|
}
|
|
|
|
int nand_init(void)
|
|
{
|
|
int res = 0;
|
|
static bool inited = false;
|
|
|
|
if(!inited)
|
|
{
|
|
res = jz_nand_init();
|
|
mutex_init(&nand_mtx);
|
|
#ifdef USE_DMA
|
|
mutex_init(&nand_dma_mtx);
|
|
semaphore_init(&nand_dma_complete, 1, 0);
|
|
system_enable_irq(DMA_IRQ(DMA_NAND_CHANNEL));
|
|
#endif
|
|
|
|
inited = true;
|
|
}
|
|
|
|
return res;
|
|
}
|
|
|
|
static inline int read_sector(unsigned long start, unsigned int count,
|
|
void* buf, unsigned int chip_size)
|
|
{
|
|
register int ret;
|
|
|
|
if(UNLIKELY(start % chip_size == 0 && count == chip_size))
|
|
ret = jz_nand_read_page(start / chip_size, buf);
|
|
else
|
|
{
|
|
ret = jz_nand_read_page(start / chip_size, temp_page);
|
|
memcpy(buf, temp_page + (start % chip_size), count);
|
|
}
|
|
|
|
return ret;
|
|
}
|
|
|
|
static inline int write_sector(unsigned long start, unsigned int count,
|
|
const void* buf, unsigned int chip_size)
|
|
{
|
|
int ret = 0;
|
|
|
|
(void)start;
|
|
(void)count;
|
|
(void)buf;
|
|
(void)chip_size;
|
|
|
|
/* TODO */
|
|
|
|
return ret;
|
|
}
|
|
|
|
int nand_read_sectors(IF_MV(int drive,) unsigned long start, int count, void* buf)
|
|
{
|
|
#ifdef HAVE_MULTIVOLUME
|
|
(void)drive;
|
|
#endif
|
|
int ret = 0;
|
|
unsigned int _count, chip_size = chip_info->page_size;
|
|
unsigned long _start;
|
|
|
|
logf("start");
|
|
mutex_lock(&nand_mtx);
|
|
|
|
_start = start << 9;
|
|
_start += 0x200000; /* skip BL */
|
|
_count = count << 9;
|
|
|
|
__nand_select();
|
|
ret = read_sector(_start, _count, buf, chip_size);
|
|
__nand_deselect();
|
|
|
|
mutex_unlock(&nand_mtx);
|
|
|
|
logf("nand_read_sectors(%ld, %d, 0x%x): %d", start, count, (int)buf, ret);
|
|
|
|
return ret;
|
|
}
|
|
|
|
int nand_write_sectors(IF_MV(int drive,) unsigned long start, int count, const void* buf)
|
|
{
|
|
#ifdef HAVE_MULTIVOLUME
|
|
(void)drive;
|
|
#endif
|
|
int ret = 0;
|
|
unsigned int _count, chip_size = chip_info->page_size;
|
|
unsigned long _start;
|
|
|
|
logf("start");
|
|
mutex_lock(&nand_mtx);
|
|
|
|
_start = start << 9;
|
|
_start += chip_info->page_size * chip_info->pages_per_block; /* skip BL */
|
|
_count = count << 9;
|
|
|
|
__nand_select();
|
|
ret = write_sector(_start, _count, buf, chip_size);
|
|
__nand_deselect();
|
|
|
|
mutex_unlock(&nand_mtx);
|
|
|
|
logf("nand_write_sectors(%ld, %d, 0x%x): %d", start, count, (int)buf, ret);
|
|
|
|
return ret;
|
|
}
|
|
|
|
#ifdef HAVE_STORAGE_FLUSH
|
|
int nand_flush(void)
|
|
{
|
|
return 0;
|
|
}
|
|
#endif
|
|
|
|
void nand_spindown(int seconds)
|
|
{
|
|
/* null */
|
|
(void)seconds;
|
|
}
|
|
|
|
void nand_sleep(void)
|
|
{
|
|
/* null */
|
|
}
|
|
|
|
void nand_spin(void)
|
|
{
|
|
/* null */
|
|
}
|
|
|
|
void nand_enable(bool on)
|
|
{
|
|
/* null - flash controller is enabled/disabled as needed. */
|
|
(void)on;
|
|
}
|
|
|
|
/* TODO */
|
|
long nand_last_disk_activity(void)
|
|
{
|
|
return 0;
|
|
}
|
|
|
|
int nand_spinup_time(void)
|
|
{
|
|
return 0;
|
|
}
|
|
|
|
void nand_sleepnow(void)
|
|
{
|
|
}
|
|
|
|
#ifdef STORAGE_GET_INFO
|
|
void nand_get_info(IF_MV(int drive,) struct storage_info *info)
|
|
{
|
|
#ifdef HAVE_MULTIVOLUME
|
|
(void)drive;
|
|
#endif
|
|
|
|
/* firmware version */
|
|
info->revision="0.00";
|
|
|
|
info->vendor="Rockbox";
|
|
info->product="NAND Storage";
|
|
|
|
/* blocks count */
|
|
info->num_sectors = nand_size;
|
|
info->sector_size = 512;
|
|
}
|
|
#endif
|
|
|
|
#ifdef CONFIG_STORAGE_MULTI
|
|
int nand_num_drives(int first_drive)
|
|
{
|
|
/* We don't care which logical drive number(s) we have been assigned */
|
|
(void)first_drive;
|
|
|
|
return 1;
|
|
}
|
|
#endif
|