eac1ca22bd
NOTE: this commit does not introduce any change, ideally even the binary should
be almost the same. I checked the disassembly by hand and there are only a few
differences here and there, mostly the compiler decides to compile very close
expressions slightly differently. I tried to run the new code on several targets
to make sure and saw no difference.
The major syntax changes of the new headers are as follows:
- BF_{WR,SET,CLR} are now superpowerful and allows to set several fileds at once:
BF_WR(reg, field1(value1), field2(value2), ...)
- BF_CS (use like BF_WR) does a write to reg_CLR and then reg_SET instead of RMW
- there is no more need for macros like BF_{WR_,SET,CLR}_V, since one can simply
BF_WR with field_V(name)
- the old BF_SETV macro has no trivial equivalent and is replaced with its
its equivalent for BF_WR(reg_SET, ...)
I also rename the register headers: "regs/regs-x.h" -> "regs/x.h" to avoid the
redundant "regs".
Final note: the registers were generated using the following command:
./headergen_v2 -g imx -o ../../firmware/target/arm/imx233/regs/ desc/regs-stmp3{600,700,780}.xml
Change-Id: I7485e8b4315a0929a8edb63e7fa1edcaa54b1edc
231 lines
7.9 KiB
C
231 lines
7.9 KiB
C
/***************************************************************************
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* __________ __ ___.
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* Open \______ \ ____ ____ | | _\_ |__ _______ ___
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* Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
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* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
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* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
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* \/ \/ \/ \/ \/
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* This file was automatically generated by headergen, DO NOT EDIT it.
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* headergen version: 3.0.0
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* stmp3600 version: 2.4.0
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* stmp3600 authors: Amaury Pouly
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*
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* Copyright (C) 2015 by the authors
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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*
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* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
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* KIND, either express or implied.
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*
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****************************************************************************/
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#ifndef __HEADERGEN_STMP3600_ARC_H__
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#define __HEADERGEN_STMP3600_ARC_H__
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#define HW_ARC_BASE HW(ARC_BASE)
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#define HWA_ARC_BASE (0x80080000 + 0x0)
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#define HWT_ARC_BASE HWIO_32_RW
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#define HWN_ARC_BASE ARC_BASE
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#define HWI_ARC_BASE
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#define HW_ARC_ID HW(ARC_ID)
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#define HWA_ARC_ID (0x80080000 + 0x0)
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#define HWT_ARC_ID HWIO_32_RW
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#define HWN_ARC_ID ARC_ID
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#define HWI_ARC_ID
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#define HW_ARC_HCSPARAMS HW(ARC_HCSPARAMS)
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#define HWA_ARC_HCSPARAMS (0x80080000 + 0x104)
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#define HWT_ARC_HCSPARAMS HWIO_32_RW
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#define HWN_ARC_HCSPARAMS ARC_HCSPARAMS
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#define HWI_ARC_HCSPARAMS
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#define HW_ARC_USBCMD HW(ARC_USBCMD)
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#define HWA_ARC_USBCMD (0x80080000 + 0x140)
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#define HWT_ARC_USBCMD HWIO_32_RW
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#define HWN_ARC_USBCMD ARC_USBCMD
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#define HWI_ARC_USBCMD
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#define HW_ARC_USBSTS HW(ARC_USBSTS)
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#define HWA_ARC_USBSTS (0x80080000 + 0x144)
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#define HWT_ARC_USBSTS HWIO_32_RW
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#define HWN_ARC_USBSTS ARC_USBSTS
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#define HWI_ARC_USBSTS
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#define HW_ARC_USBINTR HW(ARC_USBINTR)
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#define HWA_ARC_USBINTR (0x80080000 + 0x148)
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#define HWT_ARC_USBINTR HWIO_32_RW
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#define HWN_ARC_USBINTR ARC_USBINTR
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#define HWI_ARC_USBINTR
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#define HW_ARC_FRINDEX HW(ARC_FRINDEX)
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#define HWA_ARC_FRINDEX (0x80080000 + 0x14c)
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#define HWT_ARC_FRINDEX HWIO_32_RW
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#define HWN_ARC_FRINDEX ARC_FRINDEX
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#define HWI_ARC_FRINDEX
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#define HW_ARC_DEVADDR HW(ARC_DEVADDR)
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#define HWA_ARC_DEVADDR (0x80080000 + 0x154)
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#define HWT_ARC_DEVADDR HWIO_32_RW
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#define HWN_ARC_DEVADDR ARC_DEVADDR
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#define HWI_ARC_DEVADDR
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#define HW_ARC_ENDPTLISTADDR HW(ARC_ENDPTLISTADDR)
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#define HWA_ARC_ENDPTLISTADDR (0x80080000 + 0x158)
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#define HWT_ARC_ENDPTLISTADDR HWIO_32_RW
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#define HWN_ARC_ENDPTLISTADDR ARC_ENDPTLISTADDR
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#define HWI_ARC_ENDPTLISTADDR
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#define HW_ARC_PORTSC1 HW(ARC_PORTSC1)
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#define HWA_ARC_PORTSC1 (0x80080000 + 0x184)
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#define HWT_ARC_PORTSC1 HWIO_32_RW
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#define HWN_ARC_PORTSC1 ARC_PORTSC1
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#define HWI_ARC_PORTSC1
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#define HW_ARC_OTGSC HW(ARC_OTGSC)
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#define HWA_ARC_OTGSC (0x80080000 + 0x1a4)
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#define HWT_ARC_OTGSC HWIO_32_RW
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#define HWN_ARC_OTGSC ARC_OTGSC
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#define HWI_ARC_OTGSC
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#define HW_ARC_USBMODE HW(ARC_USBMODE)
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#define HWA_ARC_USBMODE (0x80080000 + 0x1a8)
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#define HWT_ARC_USBMODE HWIO_32_RW
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#define HWN_ARC_USBMODE ARC_USBMODE
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#define HWI_ARC_USBMODE
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#define HW_ARC_ENDPTSETUPSTAT HW(ARC_ENDPTSETUPSTAT)
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#define HWA_ARC_ENDPTSETUPSTAT (0x80080000 + 0x1ac)
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#define HWT_ARC_ENDPTSETUPSTAT HWIO_32_RW
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#define HWN_ARC_ENDPTSETUPSTAT ARC_ENDPTSETUPSTAT
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#define HWI_ARC_ENDPTSETUPSTAT
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#define HW_ARC_ENDPTPRIME HW(ARC_ENDPTPRIME)
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#define HWA_ARC_ENDPTPRIME (0x80080000 + 0x1b0)
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#define HWT_ARC_ENDPTPRIME HWIO_32_RW
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#define HWN_ARC_ENDPTPRIME ARC_ENDPTPRIME
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#define HWI_ARC_ENDPTPRIME
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#define HW_ARC_ENDPTFLUSH HW(ARC_ENDPTFLUSH)
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#define HWA_ARC_ENDPTFLUSH (0x80080000 + 0x1b4)
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#define HWT_ARC_ENDPTFLUSH HWIO_32_RW
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#define HWN_ARC_ENDPTFLUSH ARC_ENDPTFLUSH
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#define HWI_ARC_ENDPTFLUSH
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#define HW_ARC_ENDPTSTATUS HW(ARC_ENDPTSTATUS)
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#define HWA_ARC_ENDPTSTATUS (0x80080000 + 0x1b8)
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#define HWT_ARC_ENDPTSTATUS HWIO_32_RW
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#define HWN_ARC_ENDPTSTATUS ARC_ENDPTSTATUS
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#define HWI_ARC_ENDPTSTATUS
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#define HW_ARC_ENDPTCOMPLETE HW(ARC_ENDPTCOMPLETE)
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#define HWA_ARC_ENDPTCOMPLETE (0x80080000 + 0x1bc)
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#define HWT_ARC_ENDPTCOMPLETE HWIO_32_RW
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#define HWN_ARC_ENDPTCOMPLETE ARC_ENDPTCOMPLETE
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#define HWI_ARC_ENDPTCOMPLETE
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#define HW_ARC_ENDPTCTRL0 HW(ARC_ENDPTCTRL0)
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#define HWA_ARC_ENDPTCTRL0 (0x80080000 + 0x1c0)
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#define HWT_ARC_ENDPTCTRL0 HWIO_32_RW
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#define HWN_ARC_ENDPTCTRL0 ARC_ENDPTCTRL0
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#define HWI_ARC_ENDPTCTRL0
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#define HW_ARC_ENDPTCTRL1 HW(ARC_ENDPTCTRL1)
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#define HWA_ARC_ENDPTCTRL1 (0x80080000 + 0x1c4)
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#define HWT_ARC_ENDPTCTRL1 HWIO_32_RW
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#define HWN_ARC_ENDPTCTRL1 ARC_ENDPTCTRL1
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#define HWI_ARC_ENDPTCTRL1
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#define HW_ARC_ENDPTCTRL2 HW(ARC_ENDPTCTRL2)
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#define HWA_ARC_ENDPTCTRL2 (0x80080000 + 0x1c8)
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#define HWT_ARC_ENDPTCTRL2 HWIO_32_RW
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#define HWN_ARC_ENDPTCTRL2 ARC_ENDPTCTRL2
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#define HWI_ARC_ENDPTCTRL2
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#define HW_ARC_ENDPTCTRL3 HW(ARC_ENDPTCTRL3)
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#define HWA_ARC_ENDPTCTRL3 (0x80080000 + 0x1cc)
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#define HWT_ARC_ENDPTCTRL3 HWIO_32_RW
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#define HWN_ARC_ENDPTCTRL3 ARC_ENDPTCTRL3
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#define HWI_ARC_ENDPTCTRL3
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#define HW_ARC_ENDPTCTRL4 HW(ARC_ENDPTCTRL4)
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#define HWA_ARC_ENDPTCTRL4 (0x80080000 + 0x1d0)
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#define HWT_ARC_ENDPTCTRL4 HWIO_32_RW
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#define HWN_ARC_ENDPTCTRL4 ARC_ENDPTCTRL4
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#define HWI_ARC_ENDPTCTRL4
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#define HW_ARC_ENDPTCTRL5 HW(ARC_ENDPTCTRL5)
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#define HWA_ARC_ENDPTCTRL5 (0x80080000 + 0x1d4)
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#define HWT_ARC_ENDPTCTRL5 HWIO_32_RW
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#define HWN_ARC_ENDPTCTRL5 ARC_ENDPTCTRL5
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#define HWI_ARC_ENDPTCTRL5
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#define HW_ARC_ENDPTCTRL6 HW(ARC_ENDPTCTRL6)
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#define HWA_ARC_ENDPTCTRL6 (0x80080000 + 0x1d8)
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#define HWT_ARC_ENDPTCTRL6 HWIO_32_RW
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#define HWN_ARC_ENDPTCTRL6 ARC_ENDPTCTRL6
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#define HWI_ARC_ENDPTCTRL6
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#define HW_ARC_ENDPTCTRL7 HW(ARC_ENDPTCTRL7)
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#define HWA_ARC_ENDPTCTRL7 (0x80080000 + 0x1dc)
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#define HWT_ARC_ENDPTCTRL7 HWIO_32_RW
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#define HWN_ARC_ENDPTCTRL7 ARC_ENDPTCTRL7
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#define HWI_ARC_ENDPTCTRL7
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#define HW_ARC_ENDPTCTRL8 HW(ARC_ENDPTCTRL8)
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#define HWA_ARC_ENDPTCTRL8 (0x80080000 + 0x1e0)
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#define HWT_ARC_ENDPTCTRL8 HWIO_32_RW
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#define HWN_ARC_ENDPTCTRL8 ARC_ENDPTCTRL8
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#define HWI_ARC_ENDPTCTRL8
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#define HW_ARC_ENDPTCTRL9 HW(ARC_ENDPTCTRL9)
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#define HWA_ARC_ENDPTCTRL9 (0x80080000 + 0x1e4)
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#define HWT_ARC_ENDPTCTRL9 HWIO_32_RW
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#define HWN_ARC_ENDPTCTRL9 ARC_ENDPTCTRL9
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#define HWI_ARC_ENDPTCTRL9
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#define HW_ARC_ENDPTCTRL10 HW(ARC_ENDPTCTRL10)
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#define HWA_ARC_ENDPTCTRL10 (0x80080000 + 0x1e8)
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#define HWT_ARC_ENDPTCTRL10 HWIO_32_RW
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#define HWN_ARC_ENDPTCTRL10 ARC_ENDPTCTRL10
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#define HWI_ARC_ENDPTCTRL10
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#define HW_ARC_ENDPTCTRL11 HW(ARC_ENDPTCTRL11)
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#define HWA_ARC_ENDPTCTRL11 (0x80080000 + 0x1ec)
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#define HWT_ARC_ENDPTCTRL11 HWIO_32_RW
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#define HWN_ARC_ENDPTCTRL11 ARC_ENDPTCTRL11
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#define HWI_ARC_ENDPTCTRL11
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#define HW_ARC_ENDPTCTRL12 HW(ARC_ENDPTCTRL12)
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#define HWA_ARC_ENDPTCTRL12 (0x80080000 + 0x1f0)
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#define HWT_ARC_ENDPTCTRL12 HWIO_32_RW
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#define HWN_ARC_ENDPTCTRL12 ARC_ENDPTCTRL12
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#define HWI_ARC_ENDPTCTRL12
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#define HW_ARC_ENDPTCTRL13 HW(ARC_ENDPTCTRL13)
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#define HWA_ARC_ENDPTCTRL13 (0x80080000 + 0x1f4)
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#define HWT_ARC_ENDPTCTRL13 HWIO_32_RW
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#define HWN_ARC_ENDPTCTRL13 ARC_ENDPTCTRL13
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#define HWI_ARC_ENDPTCTRL13
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#define HW_ARC_ENDPTCTRL14 HW(ARC_ENDPTCTRL14)
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#define HWA_ARC_ENDPTCTRL14 (0x80080000 + 0x1f8)
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#define HWT_ARC_ENDPTCTRL14 HWIO_32_RW
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#define HWN_ARC_ENDPTCTRL14 ARC_ENDPTCTRL14
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#define HWI_ARC_ENDPTCTRL14
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#define HW_ARC_ENDPTCTRL15 HW(ARC_ENDPTCTRL15)
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#define HWA_ARC_ENDPTCTRL15 (0x80080000 + 0x1fc)
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#define HWT_ARC_ENDPTCTRL15 HWIO_32_RW
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#define HWN_ARC_ENDPTCTRL15 ARC_ENDPTCTRL15
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#define HWI_ARC_ENDPTCTRL15
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#define HW_ARC_ENDPTCTRLn(_n1) HW(ARC_ENDPTCTRLn(_n1))
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#define HWA_ARC_ENDPTCTRLn(_n1) (0x80080000 + 0x1c0 + (_n1) * 0x4)
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#define HWT_ARC_ENDPTCTRLn(_n1) HWIO_32_RW
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#define HWN_ARC_ENDPTCTRLn(_n1) ARC_ENDPTCTRLn
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#define HWI_ARC_ENDPTCTRLn(_n1) (_n1)
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#endif /* __HEADERGEN_STMP3600_ARC_H__*/
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