fbac4f8444
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@11572 a1c6a512-1295-4272-9138-f99709370657
716 lines
19 KiB
C
716 lines
19 KiB
C
/***************************************************************************
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* __________ __ ___.
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* Open \______ \ ____ ____ | | _\_ |__ _______ ___
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* Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
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* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
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* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
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* \/ \/ \/ \/ \/
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* $Id$
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*
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* Copyright (C) 2006 by Michael Sevakis
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*
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* All files in this archive are subject to the GNU General Public License.
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* See the file COPYING in the source tree root for full license agreement.
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*
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* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
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* KIND, either express or implied.
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*
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****************************************************************************/
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#include <stdlib.h>
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#include "system.h"
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#include "kernel.h"
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#include "logf.h"
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#include "audio.h"
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#if defined(HAVE_UDA1380)
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#include "uda1380.h"
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#elif defined(HAVE_TLV320)
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#include "tlv320.h"
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#endif
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#if defined(HAVE_SPDIF_IN) || defined(HAVE_SPDIF_OUT)
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#include "spdif.h"
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#endif
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/* Avoid further #ifdef's for some codec functions */
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#if defined(HAVE_UDA1380)
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#define ac_init uda1380_init
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#define ac_mute uda1380_mute
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#define ac_set_frequency uda1380_set_frequency
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#elif defined(HAVE_TLV320)
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#define ac_init tlv320_init
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#define ac_mute tlv320_mute
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#define ac_set_frequency tlv320_set_frequency
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#endif
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/** Semi-private shared symbols **/
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/* the registered callback function to ask for more pcm data */
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extern volatile pcm_more_callback_type pcm_callback_for_more;
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extern volatile bool pcm_playing;
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extern volatile bool pcm_paused;
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/* the registered callback function for when more data is available */
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extern volatile pcm_more_callback_type pcm_callback_more_ready;
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extern volatile bool pcm_recording;
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/* peaks */
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static int play_peak_left, play_peak_right;
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static unsigned long *rec_peak_addr;
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static int rec_peak_left, rec_peak_right;
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#define IIS_DEFPARM ( (freq_ent[FPARM_CLOCKSEL] << 12) | \
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(pcm_txsrc_select[pcm_monitor+1] << 8) | \
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(4 << 2) ) /* 64 bit clocks / word clock */
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#define IIS_RESET 0x800
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#ifdef IAUDIO_X5
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#define SET_IIS_CONFIG(x) IIS1CONFIG = (x);
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#define IIS_CONFIG IIS1CONFIG
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#define PLLCR_SET_AUDIO_BITS_DEFPARM \
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((freq_ent[FPARM_CLSEL] << 28) | (1 << 22))
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#else
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#define SET_IIS_CONFIG(x) IIS2CONFIG = (x);
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#define IIS_CONFIG IIS2CONFIG
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#define PLLCR_SET_AUDIO_BITS_DEFPARM \
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((freq_ent[FPARM_CLSEL] << 28) | (3 << 22))
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#endif
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/** Sample rates **/
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#define FPARM_CLOCKSEL 0
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#define FPARM_CLSEL 1
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#define FPARM_FSEL 2
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#if CONFIG_CPU == MCF5249 && defined(HAVE_UDA1380)
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static const unsigned char pcm_freq_parms[HW_NUM_FREQ][3] =
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{
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[HW_FREQ_88] = { 0x0c, 0x01, 0x03 },
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[HW_FREQ_44] = { 0x06, 0x01, 0x02 },
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[HW_FREQ_22] = { 0x04, 0x02, 0x01 },
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[HW_FREQ_11] = { 0x02, 0x02, 0x00 },
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};
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#endif
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#if CONFIG_CPU == MCF5250 && defined(HAVE_TLV320)
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static const unsigned char pcm_freq_parms[HW_NUM_FREQ][3] =
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{
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[HW_FREQ_88] = { 0x0c, 0x01, 0x02 },
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[HW_FREQ_44] = { 0x06, 0x01, 0x01 },
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[HW_FREQ_22] = { 0x04, 0x01, 0x00 },
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[HW_FREQ_11] = { 0x02, 0x02, 0x00 },
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};
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#endif
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static int pcm_freq = HW_SAMPR_DEFAULT; /* 44.1 is default */
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static const unsigned char *freq_ent = pcm_freq_parms[HW_FREQ_DEFAULT];
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/* set frequency used by the audio hardware */
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void pcm_set_frequency(unsigned int frequency)
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{
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int index;
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switch(frequency)
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{
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case SAMPR_11:
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index = HW_FREQ_11;
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break;
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case SAMPR_22:
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index = HW_FREQ_22;
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break;
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default:
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case SAMPR_44:
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index = HW_FREQ_44;
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break;
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case SAMPR_88:
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index = HW_FREQ_88;
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break;
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}
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/* remember table entry and rate */
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freq_ent = pcm_freq_parms[index];
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pcm_freq = hw_freq_sampr[index];
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} /* pcm_set_frequency */
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/** monitoring/source selection **/
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static int pcm_monitor = AUDIO_SRC_PLAYBACK;
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static const unsigned char pcm_txsrc_select[AUDIO_NUM_SOURCES+1] =
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{
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[AUDIO_SRC_PLAYBACK+1] = 3, /* PDOR3 */
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[AUDIO_SRC_MIC+1] = 4, /* IIS1 RcvData */
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[AUDIO_SRC_LINEIN+1] = 4, /* IIS1 RcvData */
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#ifdef HAVE_FMRADIO_IN
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[AUDIO_SRC_FMRADIO+1] = 4, /* IIS1 RcvData */
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#endif
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#ifdef HAVE_SPDIF_IN
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[AUDIO_SRC_SPDIF+1] = 7, /* EBU1 RcvData */
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#endif
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};
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static const unsigned short pcm_dataincontrol[AUDIO_NUM_SOURCES+1] =
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{
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[AUDIO_SRC_PLAYBACK+1] = 0x0200, /* Reset PDIR2 data flow */
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[AUDIO_SRC_MIC+1] = 0xc020, /* Int. when 6 samples in FIFO,
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PDIR2 src = ebu1RcvData */
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[AUDIO_SRC_LINEIN+1] = 0xc020, /* Int. when 6 samples in FIFO,
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PDIR2 src = ebu1RcvData */
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#ifdef HAVE_FMRADIO_IN
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[AUDIO_SRC_FMRADIO+1] = 0xc020, /* Int. when 6 samples in FIFO,
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PDIR2 src = ebu1RcvData */
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#endif
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#ifdef HAVE_SPDIF_IN
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[AUDIO_SRC_SPDIF+1] = 0xc038, /* Int. when 6 samples in FIFO,
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PDIR2 src = ebu1RcvData */
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#endif
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};
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static int pcm_rec_src = AUDIO_SRC_PLAYBACK;
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void pcm_set_monitor(int monitor)
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{
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if ((unsigned)monitor >= AUDIO_NUM_SOURCES)
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monitor = AUDIO_SRC_PLAYBACK;
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pcm_monitor = monitor;
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} /* pcm_set_monitor */
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void pcm_set_rec_source(int source)
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{
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if ((unsigned)source >= AUDIO_NUM_SOURCES)
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source = AUDIO_SRC_PLAYBACK;
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pcm_rec_src = source;
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} /* pcm_set_rec_source */
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/* apply audio settings */
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void pcm_apply_settings(bool reset)
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{
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static int last_pcm_freq = HW_SAMPR_DEFAULT;
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#if 0
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static int last_pcm_monitor = AUDIO_SRC_PLAYBACK;
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#endif
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static int last_pcm_rec_src = AUDIO_SRC_PLAYBACK;
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/* Playback must prevent pops and record monitoring won't work at all
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adding IIS_RESET when setting IIS_CONFIG. Use a different method for
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each. */
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if (reset && (pcm_monitor != AUDIO_SRC_PLAYBACK))
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{
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/* Not playback - reset first */
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SET_IIS_CONFIG(IIS_RESET);
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reset = false;
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}
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if (pcm_rec_src != last_pcm_rec_src)
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{
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last_pcm_rec_src = pcm_rec_src;
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DATAINCONTROL = pcm_dataincontrol[pcm_rec_src+1];
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}
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if (pcm_freq != last_pcm_freq)
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{
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last_pcm_freq = pcm_freq;
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ac_set_frequency(freq_ent[FPARM_FSEL]);
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coldfire_set_pllcr_audio_bits(PLLCR_SET_AUDIO_BITS_DEFPARM);
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}
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SET_IIS_CONFIG(IIS_DEFPARM | (reset ? IIS_RESET : 0));
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} /* pcm_apply_settings */
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/** DMA **/
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/****************************************************************************
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** Playback DMA transfer
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**/
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/* Set up the DMA transfer that kicks in when the audio FIFO gets empty */
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void pcm_play_dma_start(const void *addr, size_t size)
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{
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logf("pcm_play_dma_start");
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addr = (void *)((unsigned long)addr & ~3); /* Align data */
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size &= ~3; /* Size must be multiple of 4 */
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pcm_playing = true;
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/* Set up DMA transfer */
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SAR0 = (unsigned long)addr; /* Source address */
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DAR0 = (unsigned long)&PDOR3; /* Destination address */
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BCR0 = size; /* Bytes to transfer */
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/* Enable the FIFO and force one write to it */
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pcm_apply_settings(false);
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DCR0 = DMA_INT | DMA_EEXT | DMA_CS | DMA_AA |
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DMA_SINC | DMA_SSIZE(3) | DMA_START;
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} /* pcm_play_dma_start */
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/* Stops the DMA transfer and interrupt */
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void pcm_play_dma_stop(void)
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{
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logf("pcm_play_dma_stop");
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pcm_playing = false;
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DCR0 = 0;
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DSR0 = 1;
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/* Reset the FIFO */
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pcm_apply_settings(false);
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} /* pcm_play_dma_stop */
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void pcm_init(void)
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{
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logf("pcm_init");
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pcm_playing = false;
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pcm_paused = false;
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pcm_callback_for_more = NULL;
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MPARK = 0x81; /* PARK[1,0]=10 + BCR24BIT */
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DIVR0 = 54; /* DMA0 is mapped into vector 54 in system.c */
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DMAROUTE = (DMAROUTE & 0xffffff00) | DMA0_REQ_AUDIO_1;
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DMACONFIG = 1; /* DMA0Req = PDOR3, DMA1Req = PDIR2 */
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/* Reset the audio FIFO */
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SET_IIS_CONFIG(IIS_RESET);
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pcm_set_frequency(-1);
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pcm_set_monitor(-1);
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/* Prevent pops (resets DAC to zero point) */
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SET_IIS_CONFIG(IIS_DEFPARM | IIS_RESET);
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#if defined(HAVE_SPDIF_IN) || defined(HAVE_SPDIF_OUT)
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spdif_init();
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#endif
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/* Initialize default register values. */
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ac_init();
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#if defined(HAVE_UDA1380)
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/* Sleep a while so the power can stabilize (especially a long
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delay is needed for the line out connector). */
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sleep(HZ);
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/* Power on FSDAC and HP amp. */
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uda1380_enable_output(true);
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#elif defined(HAVE_TLV320)
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sleep(HZ/4);
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#endif
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/* UDA1380: Unmute the master channel
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(DAC should be at zero point now). */
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ac_mute(false);
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/* Call pcm_play_dma_stop to initialize everything. */
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pcm_play_dma_stop();
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/* Enable interrupt at level 7, priority 0 */
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ICR6 = (7 << 2);
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IMR &= ~(1 << 14); /* bit 14 is DMA0 */
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} /* pcm_init */
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size_t pcm_get_bytes_waiting(void)
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{
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return BCR0 & 0xffffff;
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} /* pcm_get_bytes_waiting */
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/* DMA0 Interrupt is called when the DMA has finished transfering a chunk
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from the caller's buffer */
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void DMA0(void) __attribute__ ((interrupt_handler, section(".icode")));
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void DMA0(void)
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{
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int res = DSR0;
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DSR0 = 1; /* Clear interrupt */
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DCR0 &= ~DMA_EEXT;
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/* Stop on error */
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if ((res & 0x70) == 0)
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{
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pcm_more_callback_type get_more = pcm_callback_for_more;
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unsigned char *next_start;
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size_t next_size = 0;
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if (get_more)
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get_more(&next_start, &next_size);
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if (next_size > 0)
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{
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SAR0 = (unsigned long)next_start; /* Source address */
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BCR0 = next_size; /* Bytes to transfer */
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DCR0 |= DMA_EEXT;
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return;
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}
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else
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{
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/* Finished playing */
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#if 0
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/* int. logfs can trash the display */
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logf("DMA0 No Data:0x%04x", res);
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#endif
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}
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}
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else
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{
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logf("DMA Error:0x%04x", res);
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}
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pcm_play_dma_stop();
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} /* DMA0 */
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/****************************************************************************
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** Recording DMA transfer
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**/
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void pcm_rec_dma_start(const void *addr, size_t size)
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{
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logf("pcm_rec_dma_start");
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addr = (void *)((unsigned long)addr & ~3); /* Align data */
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size &= ~3; /* Size must be multiple of 4 */
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pcm_recording = true;
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DAR1 = (unsigned long)addr; /* Destination address */
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SAR1 = (unsigned long)&PDIR2; /* Source address */
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BCR1 = size; /* Bytes to transfer */
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rec_peak_addr = (unsigned long *)addr;
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pcm_apply_settings(false);
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/* Start the DMA transfer.. */
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#ifdef HAVE_SPDIF_IN
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INTERRUPTCLEAR = 0x03c00000;
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#endif
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DCR1 = DMA_INT | DMA_EEXT | DMA_CS | DMA_AA | DMA_DINC |
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DMA_DSIZE(3) | DMA_START;
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} /* pcm_dma_start */
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void pcm_rec_dma_stop(void)
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{
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logf("pcm_rec_dma_stop");
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pcm_recording = false;
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DCR1 = 0;
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DSR1 = 1; /* Clear interrupt */
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} /* pcm_dma_stop */
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void pcm_init_recording(void)
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{
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logf("pcm_init_recording");
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pcm_recording = false;
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pcm_callback_more_ready = NULL;
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AUDIOGLOB |= 0x180; /* IIS1 fifo auto sync = on, PDIR2 auto sync = on */
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DIVR1 = 55; /* DMA1 is mapped into vector 55 in system.c */
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DMACONFIG = 1; /* DMA0Req = PDOR3, DMA1Req = PDIR2 */
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DMAROUTE = (DMAROUTE & 0xffff00ff) | DMA1_REQ_AUDIO_2;
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pcm_rec_dma_stop();
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ICR7 = (7 << 2); /* Enable interrupt at level 7, priority 0 */
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IMR &= ~(1 << 15); /* bit 15 is DMA1 */
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} /* pcm_init_recording */
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void pcm_close_recording(void)
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{
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logf("pcm_close_recording");
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pcm_rec_dma_stop();
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DMAROUTE &= 0xffff00ff;
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ICR7 = 0x00; /* Disable interrupt */
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IMR |= (1 << 15); /* bit 15 is DMA1 */
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} /* pcm_close_recording */
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/* DMA1 Interrupt is called when the DMA has finished transfering a chunk
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into the caller's buffer */
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void DMA1(void) __attribute__ ((interrupt_handler, section(".icode")));
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void DMA1(void)
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{
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int res = DSR1;
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pcm_more_callback_type more_ready;
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unsigned char *next_start;
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ssize_t next_size = 0; /* passing <> 0 is indicates
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an error condition */
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DSR1 = 1; /* Clear interrupt */
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DCR1 &= ~DMA_EEXT;
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if (res & 0x70)
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{
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next_size = DMA_REC_ERROR_DMA;
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logf("DMA1 err: 0x%x", res);
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}
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#ifdef HAVE_SPDIF_IN
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else if (pcm_rec_src == AUDIO_SRC_SPDIF &&
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(INTERRUPTSTAT & 0x01c00000)) /* valnogood, symbolerr, parityerr */
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{
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INTERRUPTCLEAR = 0x03c00000;
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next_size = DMA_REC_ERROR_SPDIF;
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logf("spdif err");
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}
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#endif
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more_ready = pcm_callback_more_ready;
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if (more_ready)
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more_ready(&next_start, &next_size);
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if (next_size > 0)
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{
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/* Start peaking at dest */
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rec_peak_addr = (unsigned long *)next_start;
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DAR1 = (unsigned long)next_start; /* Destination address */
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BCR1 = (unsigned long)next_size; /* Bytes to transfer */
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DCR1 |= DMA_EEXT;
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return;
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}
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else
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{
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#if 0
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/* int. logfs can trash the display */
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logf("DMA1 No Data:0x%04x", res);
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#endif
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}
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/* Finished recording */
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pcm_rec_dma_stop();
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} /* DMA1 */
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void pcm_mute(bool mute)
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{
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ac_mute(mute);
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if (mute)
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sleep(HZ/16);
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} /* pcm_mute */
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void pcm_play_pause_pause(void)
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{
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/* Disable DMA peripheral request. */
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DCR0 &= ~DMA_EEXT;
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pcm_apply_settings(true);
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} /* pcm_play_pause_pause */
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void pcm_play_pause_unpause(void)
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{
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/* Enable the FIFO and force one write to it */
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pcm_apply_settings(false);
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DCR0 |= DMA_EEXT | DMA_START;
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} /* pcm_play_pause_unpause */
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/**
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* Return playback peaks - Peaks ahead in the DMA buffer based upon the
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* calling period to attempt to compensate for
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* delay.
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*/
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void pcm_calculate_peaks(int *left, int *right)
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{
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unsigned long samples;
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|
unsigned long *addr, *end;
|
|
long peak_p, peak_n;
|
|
int level;
|
|
|
|
static unsigned long last_peak_tick = 0;
|
|
static unsigned long frame_period = 0;
|
|
|
|
/* Throttled peak ahead based on calling period */
|
|
unsigned long period = current_tick - last_peak_tick;
|
|
|
|
/* Keep reasonable limits on period */
|
|
if (period < 1)
|
|
period = 1;
|
|
else if (period > HZ/5)
|
|
period = HZ/5;
|
|
|
|
frame_period = (3*frame_period + period) >> 2;
|
|
|
|
last_peak_tick = current_tick;
|
|
|
|
if (!pcm_playing || pcm_paused)
|
|
{
|
|
play_peak_left = play_peak_right = 0;
|
|
goto peak_done;
|
|
}
|
|
|
|
/* prevent interrupt from setting up next transfer and
|
|
be sure SAR0 and BCR0 refer to current transfer */
|
|
level = set_irq_level(HIGHEST_IRQ_LEVEL);
|
|
|
|
addr = (long *)(SAR0 & ~3);
|
|
samples = (BCR0 & 0xffffff) >> 2;
|
|
|
|
set_irq_level(level);
|
|
|
|
samples = MIN(frame_period*pcm_freq/HZ, samples);
|
|
end = addr + samples;
|
|
peak_p = peak_n = 0;
|
|
|
|
if (left && right)
|
|
{
|
|
if (samples > 0)
|
|
{
|
|
long peak_rp = 0, peak_rn = 0;
|
|
|
|
do
|
|
{
|
|
long value = *addr;
|
|
long ch;
|
|
|
|
ch = value >> 16;
|
|
if (ch > peak_p) peak_p = ch;
|
|
else if (ch < peak_n) peak_n = ch;
|
|
|
|
ch = (short)value;
|
|
if (ch > peak_rp) peak_rp = ch;
|
|
else if (ch < peak_rn) peak_rn = ch;
|
|
|
|
addr += 4;
|
|
}
|
|
while (addr < end);
|
|
|
|
play_peak_left = MAX(peak_p, -peak_n);
|
|
play_peak_right = MAX(peak_rp, -peak_rn);
|
|
}
|
|
}
|
|
else if (left || right)
|
|
{
|
|
if (samples > 0)
|
|
{
|
|
if (left)
|
|
{
|
|
/* Put left channel in low word */
|
|
addr = (long *)((short *)addr - 1);
|
|
end = (long *)((short *)end - 1);
|
|
}
|
|
|
|
do
|
|
{
|
|
long value = *(short *)addr;
|
|
|
|
if (value > peak_p) peak_p = value;
|
|
else if (value < peak_n) peak_n = value;
|
|
|
|
addr += 4;
|
|
}
|
|
while (addr < end);
|
|
|
|
if (left)
|
|
play_peak_left = MAX(peak_p, -peak_n);
|
|
else
|
|
play_peak_right = MAX(peak_p, -peak_n);
|
|
}
|
|
}
|
|
|
|
peak_done:
|
|
if (left)
|
|
*left = play_peak_left;
|
|
|
|
if (right)
|
|
*right = play_peak_right;
|
|
} /* pcm_calculate_peaks */
|
|
|
|
/**
|
|
* Return recording peaks - Looks at every 4th sample from last peak up to
|
|
* current write position.
|
|
*/
|
|
void pcm_calculate_rec_peaks(int *left, int *right)
|
|
{
|
|
unsigned long *pkaddr, *addr, *end;
|
|
long peak_lp, peak_ln; /* L +,- */
|
|
long peak_rp, peak_rn; /* R +,- */
|
|
int level;
|
|
|
|
if (!pcm_recording)
|
|
{
|
|
rec_peak_left = rec_peak_right = 0;
|
|
goto peak_done;
|
|
}
|
|
|
|
/* read these atomically or each value may not refer to the
|
|
same data transfer */
|
|
level = set_irq_level(HIGHEST_IRQ_LEVEL);
|
|
|
|
pkaddr = rec_peak_addr;
|
|
addr = pkaddr;
|
|
end = (unsigned long *)(DAR1 & ~3);
|
|
|
|
set_irq_level(level);
|
|
|
|
if (addr < end)
|
|
{
|
|
peak_lp = peak_ln =
|
|
peak_rp = peak_rn = 0;
|
|
|
|
/* peak one sample per line */
|
|
do
|
|
{
|
|
long value = *addr;
|
|
long ch;
|
|
|
|
ch = value >> 16;
|
|
if (ch < peak_ln)
|
|
peak_ln = ch;
|
|
else if (ch > peak_lp)
|
|
peak_lp = ch;
|
|
|
|
ch = (short)value;
|
|
if (ch > peak_rp)
|
|
peak_rp = ch;
|
|
else if (ch < peak_rn)
|
|
peak_rn = ch;
|
|
|
|
addr += 4;
|
|
}
|
|
while (addr < end);
|
|
|
|
/* only update rec_peak_addr if a DMA interrupt hasn't already
|
|
done so */
|
|
level = set_irq_level(HIGHEST_IRQ_LEVEL);
|
|
|
|
if (pkaddr == rec_peak_addr)
|
|
rec_peak_addr = end;
|
|
|
|
set_irq_level(level);
|
|
|
|
/* save peaks */
|
|
rec_peak_left = MAX(peak_lp, -peak_ln);
|
|
rec_peak_right = MAX(peak_rp, -peak_rn);
|
|
}
|
|
|
|
peak_done:
|
|
if (left)
|
|
*left = rec_peak_left;
|
|
|
|
if (right)
|
|
*right = rec_peak_right;
|
|
} /* pcm_calculate_rec_peaks */
|
|
|
|
/**
|
|
* Select VINL & VINR source: 0=Line-in, 1=FM Radio
|
|
*/
|
|
/* All use GPIO */
|
|
#if defined(IAUDIO_X5)
|
|
#define REC_MUX_BIT (1 << 29)
|
|
#define REC_MUX_SET_LINE() or_l(REC_MUX_BIT, &GPIO_OUT)
|
|
#define REC_MUX_SET_FM() and_l(~REC_MUX_BIT, &GPIO_OUT)
|
|
#else
|
|
#if defined(IRIVER_H100_SERIES)
|
|
#define REC_MUX_BIT (1 << 23)
|
|
#elif defined(IRIVER_H300_SERIES)
|
|
#define REC_MUX_BIT (1 << 30)
|
|
#endif
|
|
#define REC_MUX_SET_LINE() and_l(~REC_MUX_BIT, &GPIO_OUT)
|
|
#define REC_MUX_SET_FM() or_l(REC_MUX_BIT, &GPIO_OUT)
|
|
#endif
|
|
|
|
void pcm_rec_mux(int source)
|
|
{
|
|
if (source == 0)
|
|
REC_MUX_SET_LINE(); /* Line In */
|
|
else
|
|
REC_MUX_SET_FM(); /* FM radio */
|
|
|
|
or_l(REC_MUX_BIT, &GPIO_ENABLE);
|
|
or_l(REC_MUX_BIT, &GPIO_FUNCTION);
|
|
} /* pcm_rec_mux */
|