6f44a25efa
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@7491 a1c6a512-1295-4272-9138-f99709370657
341 lines
8.3 KiB
C
341 lines
8.3 KiB
C
/***************************************************************************
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* __________ __ ___.
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* Open \______ \ ____ ____ | | _\_ |__ _______ ___
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* Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
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* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
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* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
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* \/ \/ \/ \/ \/
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* $Id$
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*
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* Copyright (C) 2002 by Alan Korr
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*
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* All files in this archive are subject to the GNU General Public License.
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* See the file COPYING in the source tree root for full license agreement.
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*
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* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
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* KIND, either express or implied.
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*
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****************************************************************************/
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#ifndef __SYSTEM_H__
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#define __SYSTEM_H__
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#include "cpu.h"
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#include "config.h"
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#include "stdbool.h"
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extern void system_reboot (void);
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extern void system_init(void);
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extern long cpu_frequency;
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#ifdef HAVE_ADJUSTABLE_CPU_FREQ
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#define FREQ cpu_frequency
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void set_cpu_frequency(long frequency);
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void cpu_boost(bool on_off);
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void cpu_idle_mode(bool on_off);
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#else
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#define FREQ CPU_FREQ
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#define cpu_boost(on_off)
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#define cpu_idle_mode(on_off)
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#endif
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#define BAUDRATE 9600
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#ifndef NULL
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#define NULL ((void*)0)
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#endif
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#ifndef MIN
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#define MIN(a, b) (((a)<(b))?(a):(b))
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#endif
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#ifndef MAX
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#define MAX(a, b) (((a)>(b))?(a):(b))
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#endif
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#ifdef ROCKBOX_LITTLE_ENDIAN
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#define SWAB16(x) (x)
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#define SWAB32(x) (x)
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#endif
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#define nop \
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asm volatile ("nop")
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/* gcc 3.4 changed the format of the constraints */
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#if (__GNUC__ >= 3) && (__GNUC_MINOR__ > 3) || (__GNUC__ >= 4)
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#define I_CONSTRAINT "I08"
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#else
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#define I_CONSTRAINT "I"
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#endif
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/* Utilize the user break controller to catch invalid memory accesses. */
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int system_memory_guard(int newmode);
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enum {
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MEMGUARD_KEEP = -1, /* don't change the mode; for reading */
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MEMGUARD_NONE = 0, /* catch nothing */
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MEMGUARD_FLASH_WRITES, /* catch writes to area 02 (flash ROM) */
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MEMGUARD_ZERO_AREA, /* catch all accesses to areas 00 and 01 */
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MAXMEMGUARD
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};
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#if CONFIG_CPU == SH7034
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#define or_b(mask, address) \
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asm \
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("or.b %0,@(r0,gbr)" \
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: \
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: /* %0 */ I_CONSTRAINT((char)(mask)), \
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/* %1 */ "z"(address-GBR))
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#define and_b(mask, address) \
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asm \
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("and.b %0,@(r0,gbr)" \
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: \
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: /* %0 */ I_CONSTRAINT((char)(mask)), \
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/* %1 */ "z"(address-GBR))
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#define xor_b(mask, address) \
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asm \
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("xor.b %0,@(r0,gbr)" \
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: \
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: /* %0 */ I_CONSTRAINT((char)(mask)), \
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/* %1 */ "z"(address-GBR))
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#elif defined(CPU_COLDFIRE)
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#define or_l(mask, address) \
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asm \
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("or.l %0,(%1)" \
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: \
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: /* %0 */ "d"(mask), \
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/* %1 */ "a"(address))
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#define and_l(mask, address) \
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asm \
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("and.l %0,(%1)" \
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: \
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: /* %0 */ "d"(mask), \
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/* %1 */ "a"(address))
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#define eor_l(mask, address) \
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asm \
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("eor.l %0,(%1)" \
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: \
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: /* %0 */ "d"(mask), \
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/* %1 */ "a"(address))
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#define EMAC_ROUND 0x10
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#define EMAC_FRACTIONAL 0x20
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#define EMAC_SATURATE 0x80
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static inline void coldfire_set_macsr(unsigned long flags)
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{
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asm volatile ("move.l %0, %%macsr" : : "i,r" (flags));
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}
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static inline unsigned long coldfire_get_macsr(void)
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{
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unsigned long m;
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asm volatile ("move.l %%macsr, %0" : "=r" (m));
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return m;
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}
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#endif
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#ifndef SIMULATOR
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/****************************************************************************
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* Interrupt level setting
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* The level is left shifted 4 bits
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****************************************************************************/
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#if CONFIG_CPU == SH7034
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#define HIGHEST_IRQ_LEVEL (15<<4)
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static inline int set_irq_level(int level)
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{
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int i;
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/* Read the old level and set the new one */
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asm volatile ("stc sr, %0" : "=r" (i));
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asm volatile ("ldc %0, sr" : : "r" (level));
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return i;
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}
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static inline unsigned short SWAB16(unsigned short value)
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/*
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result[15..8] = value[ 7..0];
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result[ 7..0] = value[15..8];
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*/
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{
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unsigned short result;
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asm volatile ("swap.b\t%1,%0" : "=r"(result) : "r"(value));
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return result;
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}
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static inline unsigned long SWAW32(unsigned long value)
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/*
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result[31..16] = value[15.. 0];
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result[15.. 0] = value[31..16];
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*/
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{
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unsigned long result;
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asm volatile ("swap.w\t%1,%0" : "=r"(result) : "r"(value));
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return result;
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}
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static inline unsigned long SWAB32(unsigned long value)
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/*
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result[31..24] = value[ 7.. 0];
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result[23..16] = value[15.. 8];
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result[15.. 8] = value[23..16];
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result[ 7.. 0] = value[31..24];
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*/
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{
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asm volatile ("swap.b\t%0,%0\n"
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"swap.w\t%0,%0\n"
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"swap.b\t%0,%0\n" : "+r"(value));
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return value;
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}
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#define invalidate_icache()
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#elif defined(CPU_COLDFIRE)
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#define HIGHEST_IRQ_LEVEL (7<<8)
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static inline int set_irq_level(int level)
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{
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int oldlevel;
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/* Read the old level and set the new one */
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asm volatile ("move.w %%sr,%0\n"
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"or.l #0x2000,%1\n"
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"move.w %1,%%sr\n" : "=r" (oldlevel), "+r" (level) : );
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return oldlevel;
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}
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static inline unsigned short SWAB16(unsigned short value)
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/*
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result[15..8] = value[ 7..0];
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result[ 7..0] = value[15..8];
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*/
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{
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return (value >> 8) | (value << 8);
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}
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static inline unsigned long SWAW32(unsigned long value)
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/*
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result[31..16] = value[15.. 0];
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result[15.. 0] = value[31..16];
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*/
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{
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asm ("swap %%0" : "+r"(value));
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return value;
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}
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static inline unsigned long SWAB32(unsigned long value)
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/*
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result[31..24] = value[ 7.. 0];
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result[23..16] = value[15.. 8];
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result[15.. 8] = value[23..16];
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result[ 7.. 0] = value[31..24];
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*/
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{
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unsigned long mask = 0x00FF00FF;
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asm ( /* val = ABCD */
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"and.l %[val],%[mask] \n" /* mask = .B.D */
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"eor.l %[mask],%[val] \n" /* val = A.C. */
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"lsl.l #8,%[mask] \n" /* mask = B.D. */
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"lsr.l #8,%[val] \n" /* val = .A.C */
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"or.l %[mask],%[val] \n" /* val = BADC */
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"swap %[val] \n" /* val = DCBA */
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: /* outputs */
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[val] "+d"(value),
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[mask]"+d"(mask)
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);
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return value;
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}
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static inline void invalidate_icache(void)
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{
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asm volatile ("move.l #0x01000000,%d0\n"
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"movec.l %d0,%cacr\n"
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"move.l #0x80000000,%d0\n"
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"movec.l %d0,%cacr");
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}
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#define CPUFREQ_DEFAULT CPU_FREQ
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#define CPUFREQ_NORMAL 47980800
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#define CPUFREQ_MAX 119952000
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#elif CONFIG_CPU == TCC730
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extern int smsc_version(void);
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extern void smsc_delay(void);
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extern void set_pll_freq(int pll_index, long freq_out);
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extern void* volatile interrupt_vector[16] __attribute__ ((section(".idata")));
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extern void ddma_transfer(int dir, int mem, void* intAddr, long extAddr,
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int num);
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#define HIGHEST_IRQ_LEVEL (1)
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static inline int set_irq_level(int level)
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{
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int result;
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__asm__ ("ld %0, 0\n\t"
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"tstsr ie\n\t"
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"incc %0" : "=r"(result));
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if (level > 0)
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__asm__ volatile ("clrsr ie");
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else
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__asm__ volatile ("setsr ie");
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return result;
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}
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static inline unsigned short SWAB16(unsigned short value)
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/*
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result[15..8] = value[ 7..0];
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result[ 7..0] = value[15..8];
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*/
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{
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return (value >> 8) | (value << 8);
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}
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static inline unsigned long SWAB32(unsigned long value)
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/*
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result[31..24] = value[ 7.. 0];
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result[23..16] = value[15.. 8];
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result[15.. 8] = value[23..16];
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result[ 7.. 0] = value[31..24];
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*/
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{
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unsigned long hi = SWAB16(value >> 16);
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unsigned long lo = SWAB16(value & 0xffff);
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return (lo << 16) | hi;
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}
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/* Archos uses:
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22MHz: busy wait on dma
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32MHz: normal
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80Mhz: heavy load
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*/
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#define CPUFREQ_DEFAULT CPU_FREQ
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#define CPUFREQ_NORMAL (32000000)
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#define CPUFREQ_MAX (80000000)
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#define invalidate_icache()
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#endif
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#else
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#define invalidate_icache()
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#endif
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#endif
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