Dana Conrad b31127db7d [bugfix] x1000: Wait for FIFO to be empty rather than flushing ... When data is not in packed-16-bit mode, flushing the fifo may result in swapping left and right channels if there happens to be an odd number of entries in the FIFO. This is especially likely when switching sample frequencies for some reason. When stopping PCM DMA, disable DMA and Underrun Interrupts and then wait for FIFO to be empty before stopping AIC's playback. Change-Id: I45b6b022c9e3889627842663cd9b7d2e0affb7c6		2023-04-02 11:34:39 -04:00
..
ingenic_jz47xx	fix red from #641e91aa2f	2023-01-13 17:02:23 -05:00
ingenic_x1000	[bugfix] x1000: Wait for FIFO to be empty rather than flushing	2023-04-02 11:34:39 -04:00
exception-mips.S	mips: consolidate exception handling, add exception backtraces	2022-10-17 09:04:18 -04:00
mipsr2-endian.h	MIPS: add another mipsr2 endian function	2021-05-29 15:35:50 +00:00
mmu-mips.c	New port: FiiO M3K on bare metal	2021-03-28 00:01:37 +00:00
mmu-mips.h	mips: Work around an issue with GCC 8.	2022-10-10 08:24:33 -04:00
system-mips.c	mips: consolidate exception handling, add exception backtraces	2022-10-17 09:04:18 -04:00
system-mips.h	mips: consolidate exception handling, add exception backtraces	2022-10-17 09:04:18 -04:00