9bb6050d40
Since we can catch exceptions like data aborts on read/write, it takes very
little to also catch exceptions in calls. When extending this with the catching
of illegal instructions, the call instruction now becomes much more robust and
also for address and instruction probing. Since we can catch several types of
exception, rename set_data_abort_jmp to set_exception_jmp. At the same time,
simplify the logic in read/write request handlers. Also fix a bug in ARM
jump code: it was using
stmia r1, {..., pc}
as if pc would get current pc + 8 but this is actually implementation defined
on older ARMs (typically pc + 12) and deprecated on newer ARMs, so rewrite the
code avoid that. The set_exception_jmp() function now also reports the exception
type.
Change-Id: Icd0dd52d2456b361b27c4776be09c3d13528ed93
295 lines
6.3 KiB
ArmAsm
295 lines
6.3 KiB
ArmAsm
#include "mips.h"
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#include "system.h"
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.extern main
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.global start
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.set mips32r2
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.set noreorder
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.set noat
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.section .init.text,"ax",%progbits
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start:
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di # disable interrupts
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bltzal zero, load_addr # ra = PC + 8, branch not taken
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nop
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load_addr:
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addiu v0, ra, -12 # calc real load address
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# account for branch delay slot
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# and very first 'di' instruction
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core_clk_setup:
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la t0, 0xb0010000 # CMU base
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li t1, 0x440 # HOSC enable, bypass
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sw t1, 0(t0) # CMU_COREPLL
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li t1, 0x350 # CORECLKS 24M, CCLKDIV = 1, SCLKDIV = 2,
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# PCLKDIV = 4
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sw t1, 0x0c(t0) # CMU_BUSCLK
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li t1, 0xc6 # HOSC enable, PLL enable, 6*6M = 36M
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sw t1, 0(t0) # CMU_COREPLL
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nop
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nop
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nop
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nop
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nop
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nop
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nop
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nop # arbitrary 300ns delay as there is no
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# PLL lock feedback
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li t1, 0x390 # CORECLKS COREPLL, CCLKDIV = 1, SCLKDIV = 2,
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# PCLKDIV = 4
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sw t1, 0x0c(t0) # CMU_BUSCLK
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cache_setup:
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la t0, 0x80000000 # an idx op should use an unmappable address
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ori t1, t0, 0x4000 # 16kB cache
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mtc0 zero, C0_TAGLO
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mtc0 zero, C0_TAGHI
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cache_init_loop:
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cache ICIndexStTag, 0(t0) # index store icache tag
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cache DCIndexStTag, 0(t0) # index store dcache tag
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bne t0, t1, cache_init_loop
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addiu t0, t0, 0x10
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li t0, 3 # enable cache for kseg0 accesses
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mtc0 t0, C0_CONFIG
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ehb
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la t0, relocstart
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la t1, relocend
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beq t0, v0, entry_point # no relocation needed
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nop
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reloc_loop:
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lw s0, 0(v0) # src
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lw s1, 4(v0)
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lw s2, 8(v0)
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lw s3, 12(v0)
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sw s0, 0(t0) # dst
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sw s1, 4(t0)
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sw s2, 8(t0)
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sw s3, 12(t0)
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synci 0(t0) # dcache writeback invalidate
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# icache invalidate
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addiu t0, t0, 16 # inc dst addr
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slt t2, t0, t1
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bnez t2, reloc_loop
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addiu v0, v0, 16 # inc src addr
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entry_point_jump:
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la t0, entry_point
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sync
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jr.hb t0
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nop
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entry_point:
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intc_setup:
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li t0, 0xb0020000 # INTC base
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lw zero, 4(t0) # INTC_MSK mask all interrupt sources
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core_irq_setup:
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li t0, 0x00404000 # BEV=1 for C0_EBASE setup, IM6=1, IE=0
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mtc0 t0, C0_STATUS
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la t0, _irqbase # vectors base address must be 4k aligned
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mtc0 t0, C0_EBASE
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li t0, 0x00004000
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mtc0 t0, C0_STATUS # BEV=0, IM6=1, IE=0
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li t1, 0x08800000
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mtc0 t1, C0_CAUSE # DC=1, IV=1
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mtc0 zero,C0_INTCTL # VS = 0
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clear_bss:
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la t0, bssbegin
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la t1, bssend
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beq t0, t1, stack_setup
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nop
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clear_bss_loop:
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sw zero, 0(t0)
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bne t0, t1, clear_bss_loop
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addiu t0, 4
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stack_setup:
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la k0, irqstackend
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la sp, stackend
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la t0, stackbegin
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li t1, 0xdeadbeef
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stack_munge_loop:
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sw t1, 0(t0)
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bne t0, sp, stack_munge_loop
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addiu t0, 4
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# jump to C code with enabled interrupts
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la t0, main
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jr.hb t0
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ei
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.extern exception_jmp_ctx_ptr
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.global tlb_refill_handler
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.section .exception.tlb_refill,"ax",%progbits
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tlb_refill_handler:
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la k1, exception_jmp_ctx_ptr
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lw s0, 0(k1)
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lw s1, 4(k1)
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lw s2, 8(k1)
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lw s3, 12(k1)
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lw s4, 16(k1)
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lw s5, 20(k1)
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lw s6, 24(k1)
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lw s7, 28(k1)
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lw sp, 32(k1)
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lw s8, 36(k1)
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lw k1, 40(k1)
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mtc0 k1, C0_EPC
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ehb
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li v0, EXCEPTION_ADDR
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eret
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nop
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.global cache_error_handler
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.section .exception.cache_error,"ax",%progbits
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cache_error_handler:
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la k1, exception_jmp_ctx_ptr
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lw s0, 0(k1)
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lw s1, 4(k1)
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lw s2, 8(k1)
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lw s3, 12(k1)
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lw s4, 16(k1)
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lw s5, 20(k1)
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lw s6, 24(k1)
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lw s7, 28(k1)
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lw sp, 32(k1)
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lw s8, 36(k1)
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lw k1, 40(k1)
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mtc0 k1, C0_EPC
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ehb
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li v0, EXCEPTION_ADDR
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eret
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nop
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.global general_exception_handler
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.section .exception.general_exception,"ax",%progbits
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general_exception_handler:
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la k1, exception_jmp_ctx_ptr
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lw s0, 0(k1)
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lw s1, 4(k1)
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lw s2, 8(k1)
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lw s3, 12(k1)
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lw s4, 16(k1)
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lw s5, 20(k1)
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lw s6, 24(k1)
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lw s7, 28(k1)
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lw sp, 32(k1)
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lw s8, 36(k1)
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lw k1, 40(k1)
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mtc0 k1, C0_EPC
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ehb
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li v0, EXCEPTION_UNSP
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eret
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nop
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/* s0-s7 not saved as this are callee saved registers
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* CO_STATUS is not saved as nested interrupts are not supported
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*
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* Separate irqstack is used for context save and irq processing
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* k0 holds the address of the top of this stack and k1 is used
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* to hold original sp value. Since we do not support nesting
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* there is nothing to worry about
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*/
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.extern INT_UDC
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.global irq_handler
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.section .exception.irq,"ax",%progbits
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irq_handler:
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move k1, sp
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move sp, k0
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addiu sp, sp, -84
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/* context save */
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sw AT, 0(sp)
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sw v0, 4(sp)
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sw v1, 8(sp)
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sw a0, 12(sp)
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sw a1, 16(sp)
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sw a2, 20(sp)
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sw a3, 24(sp)
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sw t0, 28(sp)
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sw t1, 32(sp)
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sw t2, 36(sp)
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sw t3, 40(sp)
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sw t4, 44(sp)
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sw t5, 48(sp)
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sw t6, 52(sp)
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sw t7, 56(sp)
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sw t8, 60(sp)
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sw t9, 64(sp)
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sw fp, 68(sp)
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sw ra, 72(sp)
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mfhi t0
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mflo t1
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sw t0, 76(sp)
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sw t1, 80(sp)
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/* handle interrupt */
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lui t0, 0xb002 /* INTC base */
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lw a0, 0(t0) /* INTC_PD */
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lw a1, 4(t0) /* INTC_MSK */
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and a0, a0, a1 /* mask */
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andi a0, a0, 0x10 /* UDC flag */
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beq a0, zero, restore
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nop
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/* irq dispatch */
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la a0, INT_UDC
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jalr a0
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nop
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restore:
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/* context restore */
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lw t0, 76(sp)
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lw t1, 80(sp)
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mthi t0
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mtlo t1
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lw AT, 0(sp)
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lw v0, 4(sp)
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lw v1, 8(sp)
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lw a0, 12(sp)
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lw a1, 16(sp)
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lw a2, 20(sp)
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lw a3, 24(sp)
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lw t0, 28(sp)
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lw t1, 32(sp)
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lw t2, 36(sp)
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lw t3, 40(sp)
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lw t4, 44(sp)
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lw t5, 48(sp)
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lw t6, 52(sp)
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lw t7, 56(sp)
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lw t8, 60(sp)
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lw t9, 64(sp)
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lw fp, 68(sp)
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lw ra, 72(sp)
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addiu sp, sp, 84
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move sp, k1
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eret
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nop
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.set reorder
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.set at
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