2d48d0ffa6
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@13599 a1c6a512-1295-4272-9138-f99709370657
658 lines
18 KiB
C
658 lines
18 KiB
C
/***************************************************************************
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* __________ __ ___.
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* Open \______ \ ____ ____ | | _\_ |__ _______ ___
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* Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
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* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
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* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
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* \/ \/ \/ \/ \/
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* $Id$
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*
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* Copyright (C) 2006 by Michael Sevakis
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*
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* All files in this archive are subject to the GNU General Public License.
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* See the file COPYING in the source tree root for full license agreement.
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*
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* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
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* KIND, either express or implied.
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*
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****************************************************************************/
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#include <stdlib.h>
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#include "system.h"
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#include "kernel.h"
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#include "logf.h"
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#include "audio.h"
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#include "sound.h"
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#if defined(HAVE_SPDIF_REC) || defined(HAVE_SPDIF_OUT)
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#include "spdif.h"
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#endif
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/* peaks */
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static unsigned long *rec_peak_addr;
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enum
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{
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PLAY_PEAK_LEFT = 0,
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PLAY_PEAK_RIGHT,
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REC_PEAK_LEFT,
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REC_PEAK_RIGHT
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};
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static int peaks[4]; /* p-l, p-r, r-l, r-r */
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#define IIS_PLAY_DEFPARM ( (freq_ent[FPARM_CLOCKSEL] << 12) | \
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(IIS_PLAY & (7 << 8)) | \
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(4 << 2) ) /* 64 bit clocks / word clock */
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#define IIS_FIFO_RESET (1 << 11)
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#define PDIR2_FIFO_RESET (1 << 9)
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#if defined(IAUDIO_X5) || defined(IAUDIO_M5)
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#define SET_IIS_PLAY(x) IIS1CONFIG = (x)
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#define IIS_PLAY IIS1CONFIG
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#else
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#define SET_IIS_PLAY(x) IIS2CONFIG = (x)
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#define IIS_PLAY IIS2CONFIG
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#endif
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static bool is_playback_monitoring(void)
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{
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return (IIS_PLAY & (7 << 8)) == (3 << 8);
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}
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static void iis_play_reset_if_playback(bool if_playback)
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{
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bool is_playback = is_playback_monitoring();
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if (is_playback != if_playback)
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return;
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or_l(IIS_FIFO_RESET, &IIS_PLAY);
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}
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#define PLLCR_SET_AUDIO_BITS_DEFPARM \
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((freq_ent[FPARM_CLSEL] << 28) | (1 << 22))
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/** Sample rates **/
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#define FPARM_CLOCKSEL 0
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#define FPARM_CLSEL 1
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#define FPARM_FSEL 2
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#if CONFIG_CPU == MCF5249 && defined(HAVE_UDA1380)
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static const unsigned char pcm_freq_parms[HW_NUM_FREQ][3] =
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{
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[HW_FREQ_88] = { 0x0c, 0x01, 0x03 },
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[HW_FREQ_44] = { 0x06, 0x01, 0x02 },
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[HW_FREQ_22] = { 0x04, 0x02, 0x01 },
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[HW_FREQ_11] = { 0x02, 0x02, 0x00 },
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};
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#endif
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#if CONFIG_CPU == MCF5250 && defined(HAVE_TLV320)
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static const unsigned char pcm_freq_parms[HW_NUM_FREQ][3] =
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{
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[HW_FREQ_88] = { 0x0c, 0x01, 0x02 },
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[HW_FREQ_44] = { 0x06, 0x01, 0x01 },
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[HW_FREQ_22] = { 0x04, 0x01, 0x00 },
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[HW_FREQ_11] = { 0x02, 0x02, 0x00 },
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};
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#endif
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static int pcm_freq = HW_SAMPR_DEFAULT; /* 44.1 is default */
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static const unsigned char *freq_ent = pcm_freq_parms[HW_FREQ_DEFAULT];
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/* set frequency used by the audio hardware */
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void pcm_set_frequency(unsigned int frequency)
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{
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int index;
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switch(frequency)
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{
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case SAMPR_11:
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index = HW_FREQ_11;
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break;
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case SAMPR_22:
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index = HW_FREQ_22;
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break;
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default:
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case SAMPR_44:
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index = HW_FREQ_44;
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break;
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case SAMPR_88:
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index = HW_FREQ_88;
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break;
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}
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/* remember table entry and rate */
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freq_ent = pcm_freq_parms[index];
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pcm_freq = hw_freq_sampr[index];
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} /* pcm_set_frequency */
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/* apply audio settings */
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bool _pcm_apply_settings(bool clear_reset)
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{
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static int last_pcm_freq = 0;
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bool did_reset = false;
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unsigned long iis_play_defparm = IIS_PLAY_DEFPARM;
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if (pcm_freq != last_pcm_freq)
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{
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last_pcm_freq = pcm_freq;
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/* Reprogramming bits 15-12 requires FIFO to be in a reset
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condition - Users Manual 17-8, Note 11 */
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or_l(IIS_FIFO_RESET, &IIS_PLAY);
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/* Important for TLV320 - this must happen in the correct order
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or starting recording will sound absolutely awful once in
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awhile - audiohw_set_frequency then coldfire_set_pllcr_audio_bits
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*/
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SET_IIS_PLAY(iis_play_defparm | IIS_FIFO_RESET);
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audiohw_set_frequency(freq_ent[FPARM_FSEL]);
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coldfire_set_pllcr_audio_bits(PLLCR_SET_AUDIO_BITS_DEFPARM);
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did_reset = true;
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}
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/* If a reset was done because of a sample rate change, IIS_PLAY will have
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been set already, so only needs to be set again if the reset flag must
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be cleared. If the frequency didn't change, it was never altered and
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the reset flag can just be removed or no action taken. */
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if (clear_reset)
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SET_IIS_PLAY(iis_play_defparm & ~IIS_FIFO_RESET);
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#if 0
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logf("IISPLAY: %08X", IIS_PLAY);
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#endif
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return did_reset;
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} /* _pcm_apply_settings */
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/* This clears the reset bit to enable monitoring immediately if monitoring
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recording sources or always if playback is in progress - we might be
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switching samplerates on the fly */
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void pcm_apply_settings(void)
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{
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int level = set_irq_level(DMA_IRQ_LEVEL);
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bool pbm = is_playback_monitoring();
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bool kick = (DCR0 & DMA_EEXT) != 0 && pbm;
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/* Clear reset if not playback monitoring or peripheral request is
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active and playback monitoring */
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if (_pcm_apply_settings(!pbm || kick) && kick)
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PDOR3 = 0; /* Kick FIFO out of reset by writing to it */
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set_irq_level(level);
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} /* pcm_apply_settings */
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/** DMA **/
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/****************************************************************************
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** Playback DMA transfer
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**/
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/* Set up the DMA transfer that kicks in when the audio FIFO gets empty */
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void pcm_play_dma_start(const void *addr, size_t size)
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{
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int level;
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logf("pcm_play_dma_start");
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addr = (void *)((unsigned long)addr & ~3); /* Align data */
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size &= ~3; /* Size must be multiple of 4 */
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/* If a tranfer is going, prevent an interrupt while setting up
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a new one */
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level = set_irq_level(DMA_IRQ_LEVEL);
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pcm_playing = true;
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/* Set up DMA transfer */
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SAR0 = (unsigned long)addr; /* Source address */
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DAR0 = (unsigned long)&PDOR3; /* Destination address */
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BCR0 = (unsigned long)size; /* Bytes to transfer */
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/* Enable the FIFO and force one write to it */
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_pcm_apply_settings(is_playback_monitoring());
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DCR0 = DMA_INT | DMA_EEXT | DMA_CS | DMA_AA |
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DMA_SINC | DMA_SSIZE(DMA_SIZE_LINE) | DMA_START;
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set_irq_level(level);
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} /* pcm_play_dma_start */
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/* Stops the DMA transfer and interrupt */
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static void pcm_play_dma_stop_irq(void)
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{
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pcm_playing = false;
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pcm_paused = false;
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DSR0 = 1;
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DCR0 = 0;
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/* Place TX FIFO in reset condition if playback monitoring is on.
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Recording monitoring something else should not be stopped. */
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iis_play_reset_if_playback(true);
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} /* pcm_play_dma_stop_irq */
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void pcm_play_dma_stop(void)
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{
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int level = set_irq_level(DMA_IRQ_LEVEL);
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logf("pcm_play_dma_stop");
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pcm_play_dma_stop_irq();
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set_irq_level(level);
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} /* pcm_play_dma_stop */
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void pcm_init(void)
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{
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logf("pcm_init");
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pcm_playing = false;
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pcm_paused = false;
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pcm_callback_for_more = NULL;
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AUDIOGLOB = (1 << 8) /* IIS1 fifo auto sync */
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| (1 << 7) /* PDIR2 fifo auto sync */
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#ifdef HAVE_SPDIF_OUT
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| (1 << 10) /* EBU TX auto sync */
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#endif
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;
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DIVR0 = 54; /* DMA0 is mapped into vector 54 in system.c */
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and_l(0xffffff00, &DMAROUTE);
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or_l(DMA0_REQ_AUDIO_1, &DMAROUTE);
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DMACONFIG = 1; /* DMA0Req = PDOR3, DMA1Req = PDIR2 */
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/* Call pcm_play_dma_stop to initialize everything. */
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pcm_play_dma_stop();
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/* Call pcm_close_recording to put in closed state */
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pcm_close_recording();
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/* Setup Coldfire I2S before initializing hardware or changing
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other settings. */
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or_l(IIS_FIFO_RESET, &IIS_PLAY);
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SET_IIS_PLAY(IIS_PLAY_DEFPARM | IIS_FIFO_RESET);
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pcm_set_frequency(HW_FREQ_DEFAULT);
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audio_set_output_source(AUDIO_SRC_PLAYBACK);
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/* Initialize default register values. */
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audiohw_init();
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audio_input_mux(AUDIO_SRC_PLAYBACK, SRCF_PLAYBACK);
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audiohw_set_frequency(freq_ent[FPARM_FSEL]);
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coldfire_set_pllcr_audio_bits(PLLCR_SET_AUDIO_BITS_DEFPARM);
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#if defined(HAVE_SPDIF_REC) || defined(HAVE_SPDIF_OUT)
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spdif_init();
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#endif
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/* Enable interrupt at level 6, priority 0 */
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ICR6 = (6 << 2);
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and_l(~(1 << 14), &IMR); /* bit 14 is DMA0 */
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} /* pcm_init */
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void pcm_postinit(void)
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{
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audiohw_postinit();
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}
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size_t pcm_get_bytes_waiting(void)
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{
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return BCR0 & 0xffffff;
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} /* pcm_get_bytes_waiting */
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/* DMA0 Interrupt is called when the DMA has finished transfering a chunk
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from the caller's buffer */
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void DMA0(void) __attribute__ ((interrupt_handler, section(".icode")));
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void DMA0(void)
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{
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int res = DSR0;
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DSR0 = 1; /* Clear interrupt */
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and_l(~DMA_EEXT, &DCR0); /* Disable peripheral request */
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/* Stop on error */
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if ((res & 0x70) == 0)
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{
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pcm_more_callback_type get_more = pcm_callback_for_more;
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unsigned char *next_start;
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size_t next_size = 0;
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if (get_more)
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get_more(&next_start, &next_size);
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if (next_size > 0)
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{
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SAR0 = (unsigned long)next_start; /* Source address */
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BCR0 = next_size; /* Bytes to transfer */
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or_l(DMA_EEXT, &DCR0); /* Enable peripheral request */
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return;
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}
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else
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{
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/* Finished playing */
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#if 0
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/* int. logfs can trash the display */
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logf("DMA0 No Data:0x%04x", res);
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#endif
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}
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}
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else
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{
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logf("DMA0 err: %02x", res);
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#if 0
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logf(" SAR0: %08x", SAR0);
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logf(" DAR0: %08x", DAR0);
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logf(" BCR0: %08x", BCR0);
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logf(" DCR0: %08x", DCR0);
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#endif
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}
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pcm_play_dma_stop_irq();
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} /* DMA0 */
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/****************************************************************************
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** Recording DMA transfer
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**/
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void pcm_rec_dma_start(void *addr, size_t size)
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{
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int level;
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logf("pcm_rec_dma_start");
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addr = (void *)((unsigned long)addr & ~3); /* Align data */
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size &= ~3; /* Size must be multiple of 4 */
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/* No DMA1 interrupts while setting up a new transfer */
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level = set_irq_level(DMA_IRQ_LEVEL);
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pcm_recording = true;
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and_l(~PDIR2_FIFO_RESET, &DATAINCONTROL);
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/* Clear TX FIFO reset bit if the source is not set to monitor playback
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otherwise maintain independence between playback and recording. */
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_pcm_apply_settings(!is_playback_monitoring());
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/* Start the DMA transfer.. */
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#ifdef HAVE_SPDIF_REC
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/* clear: ebu1cnew, valnogood, symbolerr, parityerr */
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INTERRUPTCLEAR = (1 << 25) | (1 << 24) | (1 << 23) | (1 << 22);
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#endif
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SAR1 = (unsigned long)&PDIR2; /* Source address */
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rec_peak_addr = (unsigned long *)addr; /* Start peaking at dest */
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DAR1 = (unsigned long)addr; /* Destination address */
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BCR1 = (unsigned long)size; /* Bytes to transfer */
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DCR1 = DMA_INT | DMA_EEXT | DMA_CS | DMA_AA | DMA_DINC |
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DMA_DSIZE(DMA_SIZE_LINE) /* | DMA_START */;
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set_irq_level(level);
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} /* pcm_dma_start */
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static void pcm_rec_dma_stop_irq(void)
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{
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DSR1 = 1; /* Clear interrupt */
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DCR1 = 0;
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pcm_recording = false;
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or_l(PDIR2_FIFO_RESET, &DATAINCONTROL);
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iis_play_reset_if_playback(false);
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} /* pcm_rec_dma_stop_irq */
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void pcm_rec_dma_stop(void)
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{
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int level = set_irq_level(DMA_IRQ_LEVEL);
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logf("pcm_rec_dma_stop");
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pcm_rec_dma_stop_irq();
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set_irq_level(level);
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} /* pcm_rec_dma_stop */
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void pcm_init_recording(void)
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{
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int level = set_irq_level(DMA_IRQ_LEVEL);
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logf("pcm_init_recording");
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pcm_recording = false;
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pcm_callback_more_ready = NULL;
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DIVR1 = 55; /* DMA1 is mapped into vector 55 in system.c */
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DMACONFIG = 1; /* DMA0Req = PDOR3, DMA1Req = PDIR2 */
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and_l(0xffff00ff, &DMAROUTE);
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or_l(DMA1_REQ_AUDIO_2, &DMAROUTE);
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pcm_rec_dma_stop_irq();
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ICR7 = (6 << 2) | (1 << 0); /* Enable interrupt at level 6, priority 1 */
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and_l(~(1 << 15), &IMR); /* bit 15 is DMA1 */
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set_irq_level(level);
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} /* pcm_init_recording */
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void pcm_close_recording(void)
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{
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int level = set_irq_level(DMA_IRQ_LEVEL);
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logf("pcm_close_recording");
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pcm_rec_dma_stop_irq();
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and_l(0xffff00ff, &DMAROUTE);
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ICR7 = 0x00; /* Disable interrupt */
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or_l((1 << 15), &IMR); /* bit 15 is DMA1 */
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set_irq_level(level);
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} /* pcm_close_recording */
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/* DMA1 Interrupt is called when the DMA has finished transfering a chunk
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into the caller's buffer */
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void DMA1(void) __attribute__ ((interrupt_handler, section(".icode")));
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void DMA1(void)
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{
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int res = DSR1;
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int status = 0;
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pcm_more_callback_type2 more_ready;
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DSR1 = 1; /* Clear interrupt */
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and_l(~DMA_EEXT, &DCR1); /* Disable peripheral request */
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if (res & 0x70)
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{
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status = DMA_REC_ERROR_DMA;
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logf("DMA1 err: %02x", res);
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#if 0
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logf(" SAR1: %08x", SAR1);
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logf(" DAR1: %08x", DAR1);
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logf(" BCR1: %08x", BCR1);
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logf(" DCR1: %08x", DCR1);
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#endif
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}
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#ifdef HAVE_SPDIF_REC
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else if (DATAINCONTROL == 0xc038 &&
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(INTERRUPTSTAT & ((1 << 24) | (1 << 23) | (1 << 22))))
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{
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/* reason: valnogood, symbolerr, parityerr */
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/* clear: ebu1cnew, valnogood, symbolerr, parityerr */
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INTERRUPTCLEAR = (1 << 25) | (1 << 24) | (1 << 23) | (1 << 22);
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status = DMA_REC_ERROR_SPDIF;
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logf("spdif err");
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}
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#endif
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more_ready = pcm_callback_more_ready;
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if (more_ready != NULL && more_ready(status) >= 0)
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return;
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#if 0
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/* int. logfs can trash the display */
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logf("DMA1 done:%04x %d", res, status);
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#endif
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/* Finished recording */
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pcm_rec_dma_stop_irq();
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} /* DMA1 */
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/* Continue transferring data in - call from interrupt callback */
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void pcm_record_more(void *start, size_t size)
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{
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rec_peak_addr = (unsigned long *)start; /* Start peaking at dest */
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DAR1 = (unsigned long)start; /* Destination address */
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BCR1 = (unsigned long)size; /* Bytes to transfer */
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or_l(DMA_EEXT, &DCR1); /* Enable peripheral request */
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}
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void pcm_mute(bool mute)
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{
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audiohw_mute(mute);
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if (mute)
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sleep(HZ/16);
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} /* pcm_mute */
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|
|
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void pcm_play_pause_pause(void)
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{
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/* Disable DMA peripheral request. */
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int level = set_irq_level(DMA_IRQ_LEVEL);
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and_l(~DMA_EEXT, &DCR0);
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iis_play_reset_if_playback(true);
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|
|
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set_irq_level(level);
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} /* pcm_play_pause_pause */
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|
|
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void pcm_play_pause_unpause(void)
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|
{
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int level = set_irq_level(DMA_IRQ_LEVEL);
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|
|
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/* Enable the FIFO and force one write to it */
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_pcm_apply_settings(is_playback_monitoring());
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or_l(DMA_EEXT | DMA_START, &DCR0);
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|
|
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set_irq_level(level);
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} /* pcm_play_pause_unpause */
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|
|
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/**
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* Do peak calculation using distance squared from axis and save a lot
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|
* of jumps and negation. Don't bother with the calculations of left or
|
|
* right only as it's never really used and won't save much time.
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|
*/
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static void pcm_peak_peeker(unsigned long *addr, unsigned long *end,
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int peaks[2])
|
|
{
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long peak_l = 0, peak_r = 0;
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long peaksq_l = 0, peaksq_r = 0;
|
|
|
|
do
|
|
{
|
|
long value = *addr;
|
|
long ch, chsq;
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|
|
|
ch = value >> 16;
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|
chsq = ch*ch;
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if (chsq > peaksq_l)
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|
peak_l = ch, peaksq_l = chsq;
|
|
|
|
ch = (short)value;
|
|
chsq = ch*ch;
|
|
if (chsq > peaksq_r)
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|
peak_r = ch, peaksq_r = chsq;
|
|
|
|
addr += 4;
|
|
}
|
|
while (addr < end);
|
|
|
|
peaks[0] = abs(peak_l);
|
|
peaks[1] = abs(peak_r);
|
|
} /* pcm_peak_peeker */
|
|
|
|
/**
|
|
* Return playback peaks - Peaks ahead in the DMA buffer based upon the
|
|
* calling period to attempt to compensate for
|
|
* delay.
|
|
*/
|
|
void pcm_calculate_peaks(int *left, int *right)
|
|
{
|
|
static unsigned long last_peak_tick = 0;
|
|
static unsigned long frame_period = 0;
|
|
|
|
long samples, samp_frames;
|
|
unsigned long *addr;
|
|
|
|
/* Throttled peak ahead based on calling period */
|
|
unsigned long period = current_tick - last_peak_tick;
|
|
|
|
/* Keep reasonable limits on period */
|
|
if (period < 1)
|
|
period = 1;
|
|
else if (period > HZ/5)
|
|
period = HZ/5;
|
|
|
|
frame_period = (3*frame_period + period) >> 2;
|
|
|
|
last_peak_tick = current_tick;
|
|
|
|
if (pcm_playing && !pcm_paused)
|
|
{
|
|
/* Snapshot as quickly as possible */
|
|
asm volatile (
|
|
"move.l %c[sar0], %[start] \n"
|
|
"move.l %c[bcr0], %[count] \n"
|
|
: [start]"=r"(addr), [count]"=r"(samples)
|
|
: [sar0]"p"(&SAR0), [bcr0]"p"(&BCR0)
|
|
);
|
|
|
|
samples &= 0xfffffc;
|
|
samp_frames = frame_period*pcm_freq/(HZ/4);
|
|
samples = MIN(samp_frames, samples) >> 2;
|
|
|
|
if (samples > 0)
|
|
{
|
|
addr = (long *)((long)addr & ~3);
|
|
pcm_peak_peeker(addr, addr + samples, &peaks[PLAY_PEAK_LEFT]);
|
|
}
|
|
}
|
|
else
|
|
{
|
|
peaks[PLAY_PEAK_LEFT] = peaks[PLAY_PEAK_RIGHT] = 0;
|
|
}
|
|
|
|
if (left)
|
|
*left = peaks[PLAY_PEAK_LEFT];
|
|
|
|
if (right)
|
|
*right = peaks[PLAY_PEAK_RIGHT];
|
|
} /* pcm_calculate_peaks */
|
|
|
|
/**
|
|
* Return recording peaks - From the end of the last peak up to
|
|
* current write position.
|
|
*/
|
|
void pcm_calculate_rec_peaks(int *left, int *right)
|
|
{
|
|
if (pcm_recording)
|
|
{
|
|
unsigned long *addr, *end;
|
|
|
|
/* Snapshot as quickly as possible */
|
|
asm volatile (
|
|
"move.l %c[start], %[addr] \n"
|
|
"move.l %c[dar1], %[end] \n"
|
|
"and.l %[mask], %[addr] \n"
|
|
"and.l %[mask], %[end] \n"
|
|
: [addr]"=r"(addr), [end]"=r"(end)
|
|
: [start]"p"(&rec_peak_addr), [dar1]"p"(&DAR1), [mask]"r"(~3)
|
|
);
|
|
|
|
if (addr < end)
|
|
{
|
|
pcm_peak_peeker(addr, end, &peaks[REC_PEAK_LEFT]);
|
|
|
|
if (addr == rec_peak_addr)
|
|
rec_peak_addr = end;
|
|
}
|
|
}
|
|
else
|
|
{
|
|
peaks[REC_PEAK_LEFT] = peaks[REC_PEAK_RIGHT] = 0;
|
|
}
|
|
|
|
if (left)
|
|
*left = peaks[REC_PEAK_LEFT];
|
|
|
|
if (right)
|
|
*right = peaks[REC_PEAK_RIGHT];
|
|
} /* pcm_calculate_rec_peaks */
|