4bd97c6535
Merge the x1000 and jz47xx exception handling code since they use the same exception vectors and handlers. The interrupt handler is now called from the common exception vector, but remains separate for each board since they have different IRQ layouts. The new exception handler can provide a stack traceback from the interrupted code, rather than the (uninteresting) caller traceback displayed by panicf. This allows you to see what led up to a null pointer deref or division by zero, which makes it _much_ easier to track down errors that occur in common leaf functions like strcmp. Change-Id: I59a0ebb5e40fcb36505c3bfdb47f8cac2f9936b1
154 lines
4.6 KiB
C
154 lines
4.6 KiB
C
/***************************************************************************
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* __________ __ ___.
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* Open \______ \ ____ ____ | | _\_ |__ _______ ___
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* Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
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* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
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* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
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* \/ \/ \/ \/ \/
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* $Id$
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*
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* Copyright (C) 2021 Aidan MacDonald
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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*
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* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
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* KIND, either express or implied.
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*
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****************************************************************************/
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#ifndef __SYSTEM_TARGET_H__
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#define __SYSTEM_TARGET_H__
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#ifdef DEBUG
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/* Define this to get CPU idle stats, visible in the debug menu. */
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# define X1000_CPUIDLE_STATS
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#endif
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#include "cpu.h"
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#include "mmu-mips.h"
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#include "mipsregs.h"
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#include "mipsr2-endian.h"
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#include "system-mips.h"
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#include <stdint.h>
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/* Rockbox API */
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#define enable_irq() set_c0_status(ST0_IE)
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#define disable_irq() clear_c0_status(ST0_IE)
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#define disable_irq_save() set_irq_level(0)
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#define restore_irq(arg) write_c0_status(arg)
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#define HIGHEST_IRQ_LEVEL 0
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static inline int set_irq_level(int lev)
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{
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unsigned reg, oldreg;
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reg = oldreg = read_c0_status();
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if(lev)
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reg |= ST0_IE;
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else
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reg &= ~ST0_IE;
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write_c0_status(reg);
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return oldreg;
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}
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#ifdef X1000_CPUIDLE_STATS
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/* CPU idle stats, updated each kernel tick in kernel-x1000.c */
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extern int __cpu_idle_avg;
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extern int __cpu_idle_cur;
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extern uint32_t __cpu_idle_ticks;
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extern uint32_t __cpu_idle_reftick;
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#endif
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static inline uint32_t __ost_read32(void);
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static inline void core_sleep(void)
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{
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#ifdef X1000_CPUIDLE_STATS
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uint32_t t1 = __ost_read32();
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#endif
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__asm__ __volatile__(
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".set push\n\t"
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".set mips32r2\n\t"
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"mfc0 $8, $12\n\t"
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"move $9, $8\n\t"
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"la $10, 0x8000000\n\t"
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"or $8, $10\n\t"
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"mtc0 $8, $12\n\t"
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"wait\n\t"
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"mtc0 $9, $12\n\t"
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".set pop\n\t"
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::: "t0", "t1", "t2");
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#ifdef X1000_CPUIDLE_STATS
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uint32_t t2 = __ost_read32();
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__cpu_idle_ticks += t2 - t1;
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#endif
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enable_irq();
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}
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/* IRQ control */
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typedef void(*irq_handler_t)(void);
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extern irq_handler_t system_set_irq_handler(int irq, irq_handler_t handler);
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extern void system_enable_irq(int irq);
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extern void system_disable_irq(int irq);
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/* Simple delay API */
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#define OST_FREQUENCY (X1000_EXCLK_FREQ / 4)
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#define OST_TICKS_PER_US (OST_FREQUENCY / 1000000)
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#define MAX_OST_DELAY_ARG 0x7fffffff
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#define MAX_UDELAY_ARG (MAX_OST_DELAY_ARG / OST_TICKS_PER_US)
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#define MAX_MDELAY_ARG (MAX_UDELAY_ARG / 1000)
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/* Macros adapted from include/linux/delay.h,
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* Copyright (C) 1993 Linus Torvalds
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*
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* These optimize away all calculations to compile time for the common case
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* of small constant arguments, reducing to a single __ost_delay() call.
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*/
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#define udelay(n) \
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((__builtin_constant_p(n) && (n) <= MAX_UDELAY_ARG) ? \
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__ost_delay((n) * OST_TICKS_PER_US) : __udelay((n)))
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#define mdelay(n) \
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((__builtin_constant_p(n) && (n) <= MAX_MDELAY_ARG) ? \
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__ost_delay((n) * 1000 * OST_TICKS_PER_US) : __mdelay((n)))
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/* Slow path implementations which handle their full argument range by
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* looping and calling __ost_delay() repeatedly.
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*/
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extern void __udelay(uint32_t us);
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extern void __mdelay(uint32_t ms);
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/* Read full 64-bit OST counter value; this requires disabling IRQs
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* to safely read the counter.
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*/
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extern uint64_t __ost_read64(void);
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static inline uint32_t __ost_read32(void)
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{
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/* Read OST_2CNTL using raw address to avoid exposing internal headers.
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* The 64-bit counter is read with IRQs disabled and since threads are
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* not pre-emptive in Rockbox we won't trash anybody's 64-bit read by
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* reading the low count without locking.
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*/
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return *(const volatile uint32_t*)0xb2000020;
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}
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/* NOTE: it is required that count < MAX_OST_DELAY_ARG, this is to provide
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* some slack in the 32-bit counter so we can reliably detect the timeout.
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*/
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static inline void __ost_delay(uint32_t count)
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{
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/* Add one to ensure we delay for at least the time given */
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count += 1;
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uint32_t start = __ost_read32();
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while(__ost_read32() - start < count);
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}
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#endif /* __SYSTEM_TARGET_H__ */
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