eb0a7a3318
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@16708 a1c6a512-1295-4272-9138-f99709370657
118 lines
3.5 KiB
C
118 lines
3.5 KiB
C
/***************************************************************************
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* __________ __ ___.
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* Open \______ \ ____ ____ | | _\_ |__ _______ ___
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* Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
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* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
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* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
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* \/ \/ \/ \/ \/
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* $Id$
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*
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* Copyright (C) 2008 by Jens Arnold
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*
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* All files in this archive are subject to the GNU General Public License.
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* See the file COPYING in the source tree root for full license agreement.
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*
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* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
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* KIND, either express or implied.
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*
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****************************************************************************/
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#include "config.h"
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#include "adc.h"
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#include "i2c-coldfire.h"
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#include "system.h"
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#define ADC_I2C_ADDR 0xa0
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/* The M3 ADC is hooked exclusively to the secondary I²C bus, and requires
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* very slow transfers (I²C clock <= 16kHz). So we start one 4-byte read
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* transfer each tick, and handle it via an ISR. At 11MHz, one transfer
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* takes too long to be started every tick, but it seems we have to live
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* with that. */
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static unsigned char adc_data[NUM_ADC_CHANNELS] IBSS_ATTR;
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static volatile bool data_ready = false;
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static void adc_tick(void)
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{
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if ((MBSR2 & IBB) == 0) /* Bus is free */
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{
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MBCR2 |= (MSTA|TXAK|MTX); /* Generate START and prepare for write */
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MBDR2 = ADC_I2C_ADDR|1; /* Send address */
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}
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}
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void IIC2(void) __attribute__((interrupt_handler));
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void IIC2(void)
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{
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static int bytenum = 0;
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MBSR2 &= ~IIF; /* Clear interrupt flag */
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if (MBSR2 & IAL) /* Arbitration lost - shouldn't never happen */
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{
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MBSR2 &= ~IAL; /* Clear flag */
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MBCR2 &= ~MSTA; /* STOP */
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}
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else if (MBCR2 & MTX) /* Address phase */
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{
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if (MBSR2 & RXAK) /* No ACK received */
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{
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MBCR2 &= ~MSTA; /* STOP */
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return;
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}
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MBCR2 &= ~(MTX|TXAK); /* Switch to RX mode, enable TX ack generation */
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MBDR2; /* Dummy read */
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bytenum = 0;
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}
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else
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{
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switch (bytenum)
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{
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case 2:
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MBCR2 |= TXAK; /* Don't ACK the last byte */
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break;
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case 3:
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MBCR2 &= ~MSTA; /* STOP before reading the last value */
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data_ready = true; /* Simplification - the last byte is a dummy. */
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break;
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}
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adc_data[bytenum++] = MBDR2;
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}
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}
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unsigned short adc_read(int channel)
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{
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return adc_data[channel];
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}
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void adc_init(void)
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{
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MFDR2 = 0x1f; /* I²C clock = SYSCLK / 3840 */
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MBCR2 = IEN; /* Enable interface */
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MBSR2 = 0; /* Clear flags */
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MBCR2 = (IEN|IIEN); /* Enable interrupts */
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or_l( 0x04000000, &INTPRI8); /* INT62 - Priority 4 */
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tick_add_task(adc_tick);
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while (!data_ready)
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sleep(1); /* Ensure valid readings when adc_init returns */
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}
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/* The ADC (most probably the PIC12F675) obviously has a slow and buggy I²C
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* implementation. If a transfer is stopped prematurely, it often locks up
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* and doesn't react anymore until the unit is power cycled. */
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void adc_close(void)
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{
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tick_remove_task(adc_tick);
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while (MBSR2 & IBB) /* Wait for an ongoing transfer to finish */
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sleep(1);
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}
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