a1ab7a55ff
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@19325 a1c6a512-1295-4272-9138-f99709370657
52 lines
1.7 KiB
C
52 lines
1.7 KiB
C
/***************************************************************************
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* __________ __ ___.
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* Open \______ \ ____ ____ | | _\_ |__ _______ ___
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* Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
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* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
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* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
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* \/ \/ \/ \/ \/
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* $Id$
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*
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* Copyright (C) 2007 by Greg White
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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*
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* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
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* KIND, either express or implied.
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*
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****************************************************************************/
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#ifndef SYSTEM_TARGET_H
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#define SYSTEM_TARGET_H
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#include "system-arm.h"
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#include "mmu-arm.h"
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#define CPUFREQ_DEFAULT 98784000
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#define CPUFREQ_NORMAL 98784000
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#define CPUFREQ_MAX 296352000
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/* Functions to set and clear regiser bits atomically */
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/* Set and clear register bits */
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void s3c_regmod32(volatile unsigned long *reg, unsigned long bits,
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unsigned long mask);
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/* Set register bits */
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void s3c_regset32(volatile unsigned long *reg, unsigned long bits);
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/* Clear register bits */
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void s3c_regclr32(volatile unsigned long *reg, unsigned long bits);
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#define HAVE_INVALIDATE_ICACHE
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static inline void invalidate_icache(void)
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{
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clean_dcache();
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asm volatile(
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"mov r0, #0 \n"
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"mcr p15, 0, r0, c7, c5, 0 \n"
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: : : "r0"
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);
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}
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#endif /* SYSTEM_TARGET_H */
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