2acc0ac542
later. We still need to hunt down snippets used that are not. 1324 modified files... http://www.rockbox.org/mail/archive/rockbox-dev-archive-2008-06/0060.shtml git-svn-id: svn://svn.rockbox.org/rockbox/trunk@17847 a1c6a512-1295-4272-9138-f99709370657
182 lines
4.7 KiB
C
182 lines
4.7 KiB
C
/***************************************************************************
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* __________ __ ___.
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* Open \______ \ ____ ____ | | _\_ |__ _______ ___
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* Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
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* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
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* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
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* \/ \/ \/ \/ \/
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* $Id$
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*
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* Copyright (C) 2007 by James Espinoza
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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*
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* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
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* KIND, either express or implied.
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*
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****************************************************************************/
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#include "kernel.h"
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#include "system.h"
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#include "panic.h"
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#include "avic-imx31.h"
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#include "gpio-imx31.h"
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#include "mmu-imx31.h"
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#include "system-target.h"
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#include "lcd.h"
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#include "serial-imx31.h"
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#include "debug.h"
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#include "clkctl-imx31.h"
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#include "mc13783.h"
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int system_memory_guard(int newmode)
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{
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(void)newmode;
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return 0;
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}
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void system_reboot(void)
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{
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}
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void system_init(void)
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{
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static const int disable_clocks[] =
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{
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/* CGR0 */
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CG_SD_MMC1,
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CG_SD_MMC2,
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CG_IIM,
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CG_CSPI3,
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CG_RNG,
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CG_UART1,
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CG_UART2,
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CG_SSI1,
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CG_I2C1,
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CG_I2C2,
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CG_I2C3,
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/* CGR1 */
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CG_HANTRO,
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CG_MEMSTICK1,
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CG_MEMSTICK2,
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CG_CSI,
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CG_PWM,
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CG_WDOG,
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CG_SIM,
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CG_ECT,
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CG_USBOTG,
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CG_KPP,
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CG_UART3,
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CG_UART4,
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CG_UART5,
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CG_1_WIRE,
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/* CGR2 */
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CG_SSI2,
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CG_CSPI1,
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CG_CSPI2,
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CG_GACC,
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CG_RTIC,
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CG_FIR
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};
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unsigned int i;
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/* MCR WFI enables wait mode */
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CLKCTL_CCMR &= ~(3 << 14);
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imx31_regmod32(&SDHC1_CLOCK_CONTROL, STOP_CLK, STOP_CLK);
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imx31_regmod32(&SDHC2_CLOCK_CONTROL, STOP_CLK, STOP_CLK);
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imx31_regmod32(&RNGA_CONTROL, RNGA_CONTROL_SLEEP, RNGA_CONTROL_SLEEP);
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imx31_regmod32(&UCR1_1, 0, EUARTUCR1_UARTEN);
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imx31_regmod32(&UCR1_2, 0, EUARTUCR1_UARTEN);
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imx31_regmod32(&UCR1_3, 0, EUARTUCR1_UARTEN);
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imx31_regmod32(&UCR1_4, 0, EUARTUCR1_UARTEN);
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imx31_regmod32(&UCR1_5, 0, EUARTUCR1_UARTEN);
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for (i = 0; i < ARRAYLEN(disable_clocks); i++)
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imx31_clkctl_module_clock_gating(disable_clocks[i], CGM_OFF);
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avic_init();
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gpio_init();
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}
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void imx31_regmod32(volatile uint32_t *reg_p, uint32_t value, uint32_t mask)
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{
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value &= mask;
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mask = ~mask;
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int oldlevel = disable_interrupt_save(IRQ_FIQ_STATUS);
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*reg_p = (*reg_p & mask) | value;
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restore_interrupt(oldlevel);
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}
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#ifdef BOOTLOADER
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void system_prepare_fw_start(void)
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{
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disable_interrupt(IRQ_FIQ_STATUS);
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avic_disable_int(ALL);
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mc13783_close();
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tick_stop();
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}
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#endif
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inline void dumpregs(void)
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{
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asm volatile ("mov %0,r0\n\t"
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"mov %1,r1\n\t"
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"mov %2,r2\n\t"
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"mov %3,r3":
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"=r"(regs.r0),"=r"(regs.r1),
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"=r"(regs.r2),"=r"(regs.r3):);
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asm volatile ("mov %0,r4\n\t"
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"mov %1,r5\n\t"
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"mov %2,r6\n\t"
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"mov %3,r7":
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"=r"(regs.r4),"=r"(regs.r5),
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"=r"(regs.r6),"=r"(regs.r7):);
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asm volatile ("mov %0,r8\n\t"
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"mov %1,r9\n\t"
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"mov %2,r10\n\t"
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"mov %3,r12":
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"=r"(regs.r8),"=r"(regs.r9),
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"=r"(regs.r10),"=r"(regs.r11):);
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asm volatile ("mov %0,r12\n\t"
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"mov %1,sp\n\t"
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"mov %2,lr\n\t"
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"mov %3,pc\n"
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"sub %3,%3,#8":
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"=r"(regs.r12),"=r"(regs.sp),
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"=r"(regs.lr),"=r"(regs.pc):);
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#ifdef HAVE_SERIAL
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dprintf("Register Dump :\n");
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dprintf("R0=0x%x\tR1=0x%x\tR2=0x%x\tR3=0x%x\n",regs.r0,regs.r1,regs.r2,regs.r3);
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dprintf("R4=0x%x\tR5=0x%x\tR6=0x%x\tR7=0x%x\n",regs.r4,regs.r5,regs.r6,regs.r7);
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dprintf("R8=0x%x\tR9=0x%x\tR10=0x%x\tR11=0x%x\n",regs.r8,regs.r9,regs.r10,regs.r11);
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dprintf("R12=0x%x\tSP=0x%x\tLR=0x%x\tPC=0x%x\n",regs.r12,regs.sp,regs.lr,regs.pc);
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//dprintf("CPSR=0x%x\t\n",regs.cpsr);
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#endif
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DEBUGF("Register Dump :\n");
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DEBUGF("R0=0x%x\tR1=0x%x\tR2=0x%x\tR3=0x%x\n",regs.r0,regs.r1,regs.r2,regs.r3);
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DEBUGF("R4=0x%x\tR5=0x%x\tR6=0x%x\tR7=0x%x\n",regs.r4,regs.r5,regs.r6,regs.r7);
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DEBUGF("R8=0x%x\tR9=0x%x\tR10=0x%x\tR11=0x%x\n",regs.r8,regs.r9,regs.r10,regs.r11);
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DEBUGF("R12=0x%x\tSP=0x%x\tLR=0x%x\tPC=0x%x\n",regs.r12,regs.sp,regs.lr,regs.pc);
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//DEBUGF("CPSR=0x%x\t\n",regs.cpsr);
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}
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#ifdef HAVE_ADJUSTABLE_CPU_FREQ
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void set_cpu_frequency(long frequency)
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{
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(void)freqency;
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}
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#endif
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