00bda90a21
Configures uncached memory region and adds some defines for misc HW, for compability with the bootloader and other future use, current functionality should not be affected. Change-Id: I390e79bea1aef5b10dfbc72ad327d7fe438ec6f5
161 lines
4.2 KiB
ArmAsm
161 lines
4.2 KiB
ArmAsm
/***************************************************************************
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* __________ __ ___.
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* Open \______ \ ____ ____ | | _\_ |__ _______ ___
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* Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
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* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
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* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
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* \/ \/ \/ \/ \/
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* $Id: crt0.S 18776 2008-10-11 18:32:17Z gevaerts $
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*
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* Copyright (C) 2008 by Marcoen Hirschberg
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* Copyright (C) 2008 by Denes Balatoni
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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*
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* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
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* KIND, either express or implied.
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*
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****************************************************************************/
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#define ASM
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#include "config.h"
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#include "cpu.h"
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.section .intvect,"ax",%progbits
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.global start
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.global _newstart
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/* Exception vectors */
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start:
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b _newstart
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ldr pc, =undef_instr_handler
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ldr pc, =software_int_handler
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ldr pc, =prefetch_abort_handler
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ldr pc, =data_abort_handler
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ldr pc, =reserved_handler
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ldr pc, =irq_handler
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ldr pc, =fiq_handler
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.ltorg
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_newstart:
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#if !defined(BOOTLOADER)
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ldr pc, =newstart2 // we do not want to execute from 0x0 as iram will be mapped there
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.section .init.text,"ax",%progbits
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newstart2:
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#endif
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msr cpsr_c, #0xd3 /* enter supervisor mode, disable IRQ/FIQ */
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#ifdef BOOTLOADER
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/* Relocate ourself to IRAM - we have been loaded to DRAM */
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mov r0, #0x08000000 /* source (DRAM) */
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mov r1, #0x22000000 /* dest (IRAM) */
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ldr r2, =_dataend
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1:
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cmp r2, r1
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ldrhi r3, [r0], #4
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strhi r3, [r1], #4
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bhi 1b
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ldr pc, =start_loc /* jump to the relocated start_loc: */
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start_loc:
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#endif
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mrc p15, 0, r0, c1, c0, 0
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bic r0, r0, #0x1000
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bic r0, r0, #0x5
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mcr p15, 0, r0, c1, c0, 0 /* disable caches and protection unit */
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.cleancache:
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mrc p15, 0, r15,c7,c10,3
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bne .cleancache
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mov r0, #0
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mcr p15, 0, r0,c7,c10,4
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mcr p15, 0, r0,c7,c5,0
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/* reset VIC controller */
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ldr r1, =0x38e00000
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add r2, r1, #0x00001000
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add r3, r1, #0x00002000
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sub r4, r0, #1
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str r4, [r1,#0x14]
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str r4, [r2,#0x14]
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str r4, [r1,#0xf00]
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str r4, [r2,#0xf00]
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str r4, [r3,#0x08]
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str r4, [r3,#0x0c]
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str r0, [r1,#0x14]
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str r0, [r2,#0x14]
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#if !defined(BOOTLOADER)
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bl memory_init
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/* Copy interrupt vectors to iram */
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ldr r2, =_intvectstart
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ldr r3, =_intvectend
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ldr r4, =_intvectcopy
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1:
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cmp r3, r2
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ldrhi r1, [r4], #4
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strhi r1, [r2], #4
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bhi 1b
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#endif
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/* Initialise bss section to zero */
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ldr r2, =_edata
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ldr r3, =_end
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mov r4, #0
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1:
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cmp r3, r2
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strhi r4, [r2], #4
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bhi 1b
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#ifndef BOOTLOADER
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/* Copy icode and data to ram */
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ldr r2, =_iramstart
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ldr r3, =_iramend
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ldr r4, =_iramcopy
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1:
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cmp r3, r2
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ldrhi r1, [r4], #4
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strhi r1, [r2], #4
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bhi 1b
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/* Initialise ibss section to zero */
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ldr r2, =_iedata
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ldr r3, =_iend
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mov r4, #0
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1:
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cmp r3, r2
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strhi r4, [r2], #4
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bhi 1b
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#endif
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/* Set up stack for IRQ mode */
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msr cpsr_c, #0xd2
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ldr sp, =_irqstackend
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/* Set up stack for FIQ mode */
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msr cpsr_c, #0xd1
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ldr sp, =_fiqstackend
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/* Let svc, abort and undefined modes use irq stack */
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msr cpsr_c, #0xd3
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ldr sp, =_irqstackend
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msr cpsr_c, #0xd7
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ldr sp, =_irqstackend
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msr cpsr_c, #0xdb
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ldr sp, =_irqstackend
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/* Switch to sys mode */
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msr cpsr_c, #0xdf
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/* Set up some stack and munge it with 0xdeadbeef */
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ldr sp, =stackend
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ldr r2, =stackbegin
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ldr r3, =0xdeadbeef
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1:
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cmp sp, r2
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strhi r3, [r2], #4
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bhi 1b
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b main
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