427 lines
12 KiB
C
427 lines
12 KiB
C
/***************************************************************************
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* __________ __ ___.
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* Open \______ \ ____ ____ | | _\_ |__ _______ ___
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* Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
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* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
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* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
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* \/ \/ \/ \/ \/
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* $Id: pcm-s5l8700.c 28600 2010-11-14 19:49:20Z Buschel $
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*
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* Copyright © 2011 Michael Sparmann
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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*
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* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
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* KIND, either express or implied.
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*
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****************************************************************************/
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#include <string.h>
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#include "config.h"
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#include "system.h"
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#include "audio.h"
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#include "s5l8702.h"
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#include "panic.h"
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#include "audiohw.h"
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#include "pcm.h"
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#include "pcm-internal.h"
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#include "pcm_sampr.h"
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#include "mmu-arm.h"
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#include "pcm-target.h"
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#include "dma-s5l8702.h"
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/* DMA configuration */
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/* 3 DMA tasks needed, one chunk task and two dblbuf tasks */
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#define DMA_PLAY_TSKBUF_SZ 4 /* N tasks, MUST be pow2 */
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#define DMA_PLAY_LLIBUF_SZ 4 /* N LLIs, MUST be pow2 */
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static struct dmac_tsk dma_play_tskbuf[DMA_PLAY_TSKBUF_SZ];
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static struct dmac_lli volatile \
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dma_play_llibuf[DMA_PLAY_LLIBUF_SZ] CACHEALIGN_ATTR;
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static void dma_play_callback(void *data) ICODE_ATTR;
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static struct dmac_ch dma_play_ch = {
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.dmac = &s5l8702_dmac0,
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.prio = DMAC_CH_PRIO(2),
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.cb_fn = dma_play_callback,
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.tskbuf = dma_play_tskbuf,
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.tskbuf_mask = DMA_PLAY_TSKBUF_SZ - 1,
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.queue_mode = QUEUE_LINK,
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.llibuf = dma_play_llibuf,
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.llibuf_mask = DMA_PLAY_LLIBUF_SZ - 1,
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.llibuf_bus = DMAC_MASTER_AHB1,
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};
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static struct dmac_ch_cfg dma_play_ch_cfg = {
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.srcperi = S5L8702_DMAC0_PERI_MEM,
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.dstperi = S5L8702_DMAC0_PERI_IIS0_TX,
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.sbsize = DMACCxCONTROL_BSIZE_8,
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.dbsize = DMACCxCONTROL_BSIZE_4,
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.swidth = DMACCxCONTROL_WIDTH_16,
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.dwidth = DMACCxCONTROL_WIDTH_16,
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.sbus = DMAC_MASTER_AHB1,
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.dbus = DMAC_MASTER_AHB1,
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.sinc = DMACCxCONTROL_INC_ENABLE,
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.dinc = DMACCxCONTROL_INC_DISABLE,
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.prot = DMAC_PROT_CACH | DMAC_PROT_BUFF | DMAC_PROT_PRIV,
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/* align LLI transfers to L-R pairs (samples) */
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.lli_xfer_max_count = DMAC_LLI_MAX_COUNT & ~1,
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};
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#define LLI_MAX_BYTES 8188 /* lli_xfer_max_count << swidth */
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/* Use all available LLIs for chunk */
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/*#define CHUNK_MAX_BYTES (LLI_MAX_BYTES * (DMA_PLAY_LLIBUF_SZ - 2))*/
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#define CHUNK_MAX_BYTES (LLI_MAX_BYTES * 1)
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#define WATERMARK_BYTES (PCM_WATERMARK * 4)
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static volatile int locked = 0;
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static unsigned char dblbuf[2][WATERMARK_BYTES] CACHEALIGN_ATTR;
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static int active_dblbuf;
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size_t pcm_remaining;
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/* Mask the DMA interrupt */
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void pcm_play_lock(void)
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{
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if (locked++ == 0)
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dmac_ch_lock_int(&dma_play_ch);
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}
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/* Unmask the DMA interrupt if enabled */
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void pcm_play_unlock(void)
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{
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if (--locked == 0)
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dmac_ch_unlock_int(&dma_play_ch);
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}
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static inline void play_queue_dma(void *addr, size_t size, void *cb_data)
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{
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commit_dcache_range(addr, size);
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dmac_ch_queue(&dma_play_ch, addr,
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(void*)S5L8702_DADDR_PERI_IIS0_TX, size, cb_data);
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}
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static void dma_play_callback(void *cb_data)
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{
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if (!cb_data)
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return; /* dblbuf callback entered, nothing to do */
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const void *dataptr = cb_data;
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if (!pcm_remaining)
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if (!pcm_play_dma_complete_callback(
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PCM_DMAST_OK, &dataptr, &pcm_remaining))
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return;
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uint32_t lastsize = MIN(WATERMARK_BYTES, pcm_remaining >> 1);
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pcm_remaining -= lastsize;
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uint32_t chunksize = MIN(CHUNK_MAX_BYTES, pcm_remaining);
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/* last chunk should be at least 2*WATERMARK_BYTES in size */
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if ((pcm_remaining > chunksize) &&
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(pcm_remaining < chunksize + WATERMARK_BYTES * 2))
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chunksize = pcm_remaining - WATERMARK_BYTES * 2;
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pcm_remaining -= chunksize;
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/* first part */
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play_queue_dma((void*)dataptr, chunksize,
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(void*)dataptr + chunksize + lastsize); /* cb_data */
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/* second part */
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memcpy(dblbuf[active_dblbuf], dataptr + chunksize, lastsize);
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play_queue_dma(dblbuf[active_dblbuf], lastsize, NULL);
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active_dblbuf ^= 1;
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pcm_play_dma_status_callback(PCM_DMAST_STARTED);
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}
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void pcm_play_dma_start(const void* addr, size_t size)
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{
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pcm_play_dma_stop();
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pcm_remaining = size;
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I2STXCOM = 0xe;
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dma_play_callback((void*)addr);
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}
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void pcm_play_dma_stop(void)
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{
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dmac_ch_stop(&dma_play_ch);
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I2STXCOM = 0xa;
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}
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/* MCLK = 12MHz (MCLKDIV2=1), [CS42L55 DS, s4.8] */
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#define MCLK_FREQ 12000000
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/* set the configured PCM frequency */
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void pcm_dma_apply_settings(void)
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{
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static uint16_t last_clkcon3l = 0;
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uint16_t clkcon3l;
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int fsel;
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/* For unknown reasons, s5l8702 I2S controller does not synchronize
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* with CS42L55 at 32000 Hz. To fix it, the CODEC is configured with
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* a sample rate of 48000 Hz and MCLK is decreased 1/3 to 8 Mhz,
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* obtaining 32 KHz in LRCK controller input and 8 MHz in SCLK input.
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* OF uses this trick.
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*/
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if (pcm_fsel == HW_FREQ_32) {
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fsel = HW_FREQ_48;
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clkcon3l = 0x3028; /* PLL2 / 3 / 9 -> 8 MHz */
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}
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else {
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fsel = pcm_fsel;
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clkcon3l = 0; /* OSC0 -> 12 MHz */
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}
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/* configure MCLK */
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/* TODO: maybe all CLKCON management should be moved to
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cscodec-ipod6g.c and system-s5l8702.c */
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if (last_clkcon3l != clkcon3l) {
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CLKCON3 = (CLKCON3 & ~0xffff) | 0x8000 | clkcon3l;
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udelay(100);
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CLKCON3 &= ~0x8000; /* CLKCON3L on */
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last_clkcon3l = clkcon3l;
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}
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/* configure I2S clock ratio */
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I2SCLKDIV = MCLK_FREQ / hw_freq_sampr[fsel];
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/* select CS42L55 sample rate */
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audiohw_set_frequency(fsel);
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}
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void pcm_play_dma_init(void)
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{
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PWRCON(1) &= ~(1 << 7);
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dmac_ch_init(&dma_play_ch, &dma_play_ch_cfg);
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I2STXCON = 0xb100019;
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I2SCLKCON = 1;
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audiohw_preinit();
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pcm_dma_apply_settings();
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}
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void pcm_play_dma_postinit(void)
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{
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audiohw_postinit();
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}
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#ifdef HAVE_PCM_DMA_ADDRESS
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void * pcm_dma_addr(void *addr)
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{
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return addr;
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}
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#endif
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/****************************************************************************
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** Recording DMA transfer
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**/
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#ifdef HAVE_RECORDING
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static volatile int rec_locked = 0;
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static void *rec_dma_addr;
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static size_t rec_dma_size;
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static bool pcm_rec_initialized = false;
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static int completed_task;
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/* ahead capture buffer */
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#define PCM_AHEADBUF_SAMPLES 128
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#define AHEADBUF_SZ (PCM_AHEADBUF_SAMPLES * 4)
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static unsigned char ahead_buf[AHEADBUF_SZ] CACHEALIGN_ATTR;
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/* DMA configuration */
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static void dma_rec_callback(void *cb_data) ICODE_ATTR;
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enum { /* cb_data */
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TASK_AHEADBUF,
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TASK_RECBUF
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};
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#define DMA_REC_TSKBUF_SZ 2 /* N tasks, MUST be pow2 */
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#define DMA_REC_LLIBUF_SZ 8 /* N LLIs, MUST be pow2 */
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static struct dmac_tsk dma_rec_tskbuf[DMA_REC_TSKBUF_SZ];
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static struct dmac_lli volatile \
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dma_rec_llibuf[DMA_REC_LLIBUF_SZ] CACHEALIGN_ATTR;
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static struct dmac_ch dma_rec_ch = {
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.dmac = &s5l8702_dmac0,
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.prio = DMAC_CH_PRIO(1),
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.cb_fn = dma_rec_callback,
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.llibuf = dma_rec_llibuf,
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.llibuf_mask = DMA_REC_LLIBUF_SZ - 1,
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.llibuf_bus = DMAC_MASTER_AHB1,
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.tskbuf = dma_rec_tskbuf,
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.tskbuf_mask = DMA_REC_TSKBUF_SZ - 1,
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.queue_mode = QUEUE_LINK,
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};
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static struct dmac_ch_cfg dma_rec_ch_cfg = {
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.srcperi = S5L8702_DMAC0_PERI_IIS0_RX,
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.dstperi = S5L8702_DMAC0_PERI_MEM,
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.sbsize = DMACCxCONTROL_BSIZE_4,
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.dbsize = DMACCxCONTROL_BSIZE_4,
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.swidth = DMACCxCONTROL_WIDTH_16,
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.dwidth = DMACCxCONTROL_WIDTH_16,
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.sbus = DMAC_MASTER_AHB1,
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.dbus = DMAC_MASTER_AHB1,
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.sinc = DMACCxCONTROL_INC_DISABLE,
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.dinc = DMACCxCONTROL_INC_ENABLE,
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.prot = DMAC_PROT_CACH | DMAC_PROT_BUFF | DMAC_PROT_PRIV,
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/* align LLI transfers to L-R pairs (samples) */
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.lli_xfer_max_count = DMAC_LLI_MAX_COUNT & ~1,
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};
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/* maximum and minimum supported block sizes in bytes */
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#define MIN_SIZE ((size_t) (AHEADBUF_SZ * 2))
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#define MAX_SIZE ((size_t) (AHEADBUF_SZ + ((DMA_REC_LLIBUF_SZ - 1) * \
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(dma_rec_ch_cfg.lli_xfer_max_count << dma_rec_ch_cfg.swidth))))
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#if 0
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#define SIZE_PANIC(sz) { \
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if (((sz) < MIN_SIZE) || ((sz) > MAX_SIZE)) \
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panicf("pcm record: unsupported size: %d", (sz)); \
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}
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#else
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#define SIZE_PANIC(sz) {}
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#endif
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static void rec_dmac_ch_queue(void *addr, size_t size, int cb_data)
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{
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discard_dcache_range(addr, size);
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dmac_ch_queue(&dma_rec_ch, (void*)S5L8702_DADDR_PERI_IIS0_RX,
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addr, size, (void *)cb_data);
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}
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static void dma_rec_callback(void *cb_data)
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{
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completed_task = (int)cb_data;
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if (completed_task == TASK_AHEADBUF)
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{
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/* safety check */
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if (rec_dma_addr == NULL)
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return; /* capture finished */
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/* move ahead buffer to record buffer and queue
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next capture-ahead task */
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memcpy(rec_dma_addr, ahead_buf, AHEADBUF_SZ);
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rec_dmac_ch_queue(ahead_buf, AHEADBUF_SZ, TASK_AHEADBUF);
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}
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else /* TASK_RECBUF */
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{
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/* Inform middle layer */
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if (pcm_rec_dma_complete_callback(
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PCM_DMAST_OK, &rec_dma_addr, &rec_dma_size))
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{
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SIZE_PANIC(rec_dma_size);
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rec_dmac_ch_queue(rec_dma_addr + AHEADBUF_SZ,
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rec_dma_size - AHEADBUF_SZ, TASK_RECBUF);
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pcm_rec_dma_status_callback(PCM_DMAST_STARTED);
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}
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}
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}
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void pcm_rec_lock(void)
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{
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if ((rec_locked++ == 0) && pcm_rec_initialized)
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dmac_ch_lock_int(&dma_rec_ch);
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}
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void pcm_rec_unlock(void)
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{
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if ((--rec_locked == 0) && pcm_rec_initialized)
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dmac_ch_unlock_int(&dma_rec_ch);
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}
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void pcm_rec_dma_stop(void)
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{
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if (!pcm_rec_initialized)
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return;
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dmac_ch_stop(&dma_rec_ch);
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I2SRXCOM = 0x2; /* stop Rx I2S */
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}
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void pcm_rec_dma_start(void *addr, size_t size)
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{
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SIZE_PANIC(size);
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pcm_rec_dma_stop();
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rec_dma_addr = addr;
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rec_dma_size = size;
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completed_task = -1;
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/* launch first DMA transfer to capture into ahead buffer,
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link the second task to capture into record buffer */
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rec_dmac_ch_queue(ahead_buf, AHEADBUF_SZ, TASK_AHEADBUF);
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rec_dmac_ch_queue(addr + AHEADBUF_SZ, size - AHEADBUF_SZ, TASK_RECBUF);
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I2SRXCOM = 0x6; /* start Rx I2S */
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}
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void pcm_rec_dma_close(void)
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{
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pcm_rec_dma_stop();
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}
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void pcm_rec_dma_init(void)
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{
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if (pcm_rec_initialized)
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return;
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PWRCON(1) &= ~(1 << 7);
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dmac_ch_init(&dma_rec_ch, &dma_rec_ch_cfg);
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/* synchronize lock status */
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if (rec_locked)
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dmac_ch_lock_int(&dma_rec_ch);
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I2SRXCON = 0x1000;
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I2SCLKCON = 1;
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pcm_rec_initialized = true;
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}
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const void * pcm_rec_dma_get_peak_buffer(void)
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{
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void *dstaddr;
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pcm_rec_lock();
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if (completed_task == TASK_AHEADBUF) {
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dstaddr = dmac_ch_get_info(&dma_rec_ch, NULL, NULL);
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if ((dstaddr < rec_dma_addr) ||
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(dstaddr > rec_dma_addr + rec_dma_size))
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/* At this moment, interrupt for TASK_RECBUF is waiting to
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be handled. TASK_RECBUF is already finished and HW is
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transfering next TASK_AHEADBUF. Return whole block. */
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dstaddr = rec_dma_addr + rec_dma_size;
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}
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else {
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/* Ahead buffer not yet captured _and_ moved to
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record buffer. Return nothing. */
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dstaddr = rec_dma_addr;
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}
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pcm_rec_unlock();
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return CACHEALIGN_DOWN(dstaddr);
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}
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#endif /* HAVE_RECORDING */
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