295367686e
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@11850 a1c6a512-1295-4272-9138-f99709370657
84 lines
2.3 KiB
C
84 lines
2.3 KiB
C
#include <string.h>
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#include "s3c2440.h"
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void map_memory(void);
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static void enable_mmu(void);
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static void set_ttb(void);
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static void set_page_tables(void);
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static void map_section(unsigned int pa, unsigned int va, int mb, int cache_flags);
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#define SECTION_ADDRESS_MASK (-1 << 20)
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#define CACHE_ALL (1 << 3 | 1 << 2 )
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#define CACHE_NONE 0
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#define BUFFERED (1 << 2)
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#define MB (1 << 20)
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void map_memory(void) {
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set_ttb();
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set_page_tables();
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enable_mmu();
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}
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unsigned int* ttb_base;
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const int ttb_size = 4096;
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void set_ttb() {
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int i;
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int* ttbPtr;
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int domain_access;
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/* must be 16Kb (0x4000) aligned */
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ttb_base = (int*)0x31F00000;
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for (i=0; i<ttb_size; i++,ttbPtr++)
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ttbPtr = 0;
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asm volatile("mcr p15, 0, %0, c2, c0, 0" : : "r" (ttb_base));
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/* set domain D0 to "client" permission access */
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domain_access = 3;
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asm volatile("mcr p15, 0, %0, c3, c0, 0" : : "r" (domain_access));
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}
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void set_page_tables() {
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map_section(0, 0, 0x1000, CACHE_NONE);
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map_section(0x30000000, 0, 32, CACHE_NONE); /* map RAM to 0 */
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map_section(0x30000000, 0, 30, CACHE_ALL); /* cache the first 30 MB or RAM */
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map_section(0x31E00000, 0x31E00000, 1, BUFFERED); /* enable buffered writing for the framebuffer */
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}
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void map_section(unsigned int pa, unsigned int va, int mb, int cache_flags) {
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unsigned int* ttbPtr;
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int i;
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int section_no;
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section_no = va >> 20; /* sections are 1Mb size */
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ttbPtr = ttb_base + section_no;
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pa &= SECTION_ADDRESS_MASK; /* align to 1Mb */
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for(i=0; i<mb; i++, pa += MB) {
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*(ttbPtr + i) =
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pa |
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1 << 10 | /* superuser - r/w, user - no access */
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0 << 5 | /* domain 0th */
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1 << 4 | /* should be "1" */
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cache_flags |
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1 << 1; /* Section signature */
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}
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}
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static void enable_mmu(void) {
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asm volatile("mov r0, #0\n"
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"mcr p15, 0, r0, c8, c7, 0\n" /* invalidate TLB */
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"mcr p15, 0, r0, c7, c7,0\n" /* invalidate both icache and dcache */
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"mrc p15, 0, r0, c1, c0, 0\n"
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"orr r0, r0, #1<<0\n" /* enable mmu bit, icache and dcache */
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"orr r0, r0, #1<<2\n" /* enable dcache */
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"orr r0, r0, #1<<12\n" /* enable icache */
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"mcr p15, 0, r0, c1, c0, 0" : : : "r0");
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asm volatile("nop \n nop \n nop \n nop");
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}
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