62c4a2838e
* Overall cleanup (still needs work) * Add preliminary USB support * Add power off support * Add preliminary MMU handling git-svn-id: svn://svn.rockbox.org/rockbox/trunk@18348 a1c6a512-1295-4272-9138-f99709370657
309 lines
9.2 KiB
C
309 lines
9.2 KiB
C
/***************************************************************************
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* __________ __ ___.
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* Open \______ \ ____ ____ | | _\_ |__ _______ ___
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* Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
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* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
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* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
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* \/ \/ \/ \/ \/
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* $Id$
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*
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* Copyright (C) 2008 by Maurus Cuelenaere
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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*
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* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
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* KIND, either express or implied.
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*
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****************************************************************************/
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#include "config.h"
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#include "jz4740.h"
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#include "ata.h"
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#include "nand_id.h"
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#include "system.h"
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#include "panic.h"
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#define NAND_CMD_READ1_00 0x00
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#define NAND_CMD_READ1_01 0x01
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#define NAND_CMD_READ2 0x50
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#define NAND_CMD_READ_ID1 0x90
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#define NAND_CMD_READ_ID2 0x91
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#define NAND_CMD_RESET 0xFF
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#define NAND_CMD_PAGE_PROGRAM_START 0x80
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#define NAND_CMD_PAGE_PROGRAM_STOP 0x10
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#define NAND_CMD_BLOCK_ERASE_START 0x60
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#define NAND_CMD_BLOCK_ERASE_CONFIRM 0xD0
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#define NAND_CMD_READ_STATUS 0x70
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#define NANDFLASH_CLE 0x00008000 //PA[15]
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#define NANDFLASH_ALE 0x00010000 //PA[16]
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#define NANDFLASH_BASE 0xB8000000
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#define REG_NAND_DATA8 (*((volatile unsigned char *)NANDFLASH_BASE))
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#define REG_NAND_DATA16 (*((volatile unsigned short *)NANDFLASH_BASE))
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#define REG_NAND_DATA REG_NAND_DATA8
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#define REG_NAND_CMD (*((volatile unsigned char *)(NANDFLASH_BASE + NANDFLASH_CLE)))
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#define REG_NAND_ADDR (*((volatile unsigned char *)(NANDFLASH_BASE + NANDFLASH_ALE)))
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#define JZ_NAND_SELECT (REG_EMC_NFCSR |= EMC_NFCSR_NFCE1 )
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#define JZ_NAND_DESELECT (REG_EMC_NFCSR &= ~(EMC_NFCSR_NFCE1))
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#define __nand_enable() (REG_EMC_NFCSR |= (EMC_NFCSR_NFE1 | EMC_NFCSR_NFCE1))
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#define __nand_disable() (REG_EMC_NFCSR &= ~(EMC_NFCSR_NFCE1))
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#define __nand_ecc_disable() (REG_EMC_NFECR &= ~EMC_NFECR_ECCE)
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#define __nand_ecc_encode_sync() while (!(REG_EMC_NFINTS & EMC_NFINTS_ENCF))
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#define __nand_ecc_decode_sync() while (!(REG_EMC_NFINTS & EMC_NFINTS_DECF))
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#define __nand_ecc_rs_encoding() \
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(REG_EMC_NFECR = EMC_NFECR_ECCE | EMC_NFECR_ERST | EMC_NFECR_RS | EMC_NFECR_RS_ENCODING)
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#define __nand_ecc_rs_decoding() \
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(REG_EMC_NFECR = EMC_NFECR_ECCE | EMC_NFECR_ERST | EMC_NFECR_RS | EMC_NFECR_RS_DECODING)
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#define my__gpio_as_nand() \
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do { \
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REG_GPIO_PXFUNS(1) = 0x1E018000; \
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REG_GPIO_PXSELC(1) = 0x1E018000; \
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REG_GPIO_PXFUNS(2) = 0x30000000; \
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REG_GPIO_PXSELC(2) = 0x30000000; \
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REG_GPIO_PXFUNC(2) = 0x40000000; \
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REG_GPIO_PXSELC(2) = 0x40000000; \
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REG_GPIO_PXDIRC(2) = 0x40000000; \
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REG_GPIO_PXFUNS(1) = 0x00400000; \
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REG_GPIO_PXSELC(1) = 0x00400000; \
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} while (0)
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static struct nand_info* chip_info = NULL;
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#define NAND_BLOCK_SIZE (chip_info->pages_per_block * chip_info->page_size)
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#define NAND_OOB_SIZE (chip_info->page_size / 32)
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struct nand_page_info_t
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{
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unsigned char block_status;
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unsigned int reserved;
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unsigned short block_addr_field;
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unsigned int lifetime;
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unsigned char ecc_field[50];//[NAND_OOB_SIZE - 11];
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} __attribute__ ((packed));
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static void nand_wait_ready(void)
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{
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int wait = 100;
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while(REG_GPIO_PXPIN(2) & (1 << 30) && wait--);
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while (!(REG_GPIO_PXPIN(2) & 0x40000000));
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}
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static inline void nand_read_memcpy(void *target, void *source, unsigned int len)
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{
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int ch = 2;
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if(((unsigned int)source < 0xa0000000) && len)
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dma_cache_wback_inv((unsigned long)source, len);
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if(((unsigned int)target < 0xa0000000) && len)
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dma_cache_wback_inv((unsigned long)target, len);
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REG_DMAC_DSAR(ch) = PHYSADDR((unsigned long)source);
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REG_DMAC_DTAR(ch) = PHYSADDR((unsigned long)target);
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REG_DMAC_DTCR(ch) = len / 4;
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REG_DMAC_DRSR(ch) = DMAC_DRSR_RS_AUTO;
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REG_DMAC_DCMD(ch) = DMAC_DCMD_SAI | DMAC_DCMD_DAI | DMAC_DCMD_SWDH_8 | DMAC_DCMD_DWDH_32 | DMAC_DCMD_DS_32BIT;
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REG_DMAC_DCCSR(ch) = DMAC_DCCSR_EN | DMAC_DCCSR_NDES;
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while ( REG_DMAC_DTCR(ch) );
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}
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static void rs_correct(unsigned char *buf, int idx, int mask)
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{
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int i, j;
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unsigned short d, d1, dm;
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i = (idx * 9) >> 3;
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j = (idx * 9) & 0x7;
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i = (j == 0) ? (i - 1) : i;
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j = (j == 0) ? 7 : (j - 1);
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if(i >= 512)
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return;
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d = (buf[i] << 8) | buf[i - 1];
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d1 = (d >> j) & 0x1ff;
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d1 ^= mask;
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dm = ~(0x1ff << j);
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d = (d & dm) | (d1 << j);
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buf[i - 1] = d & 0xff;
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buf[i] = (d >> 8) & 0xff;
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}
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static inline int nand_rs_correct(unsigned char *data)
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{
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unsigned int stat = REG_EMC_NFINTS;
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if (stat & EMC_NFINTS_ERR) {
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if (stat & EMC_NFINTS_UNCOR)
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{
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panicf("Uncorrectable ECC error occurred!\n stat = 0x%x", stat);
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return -1;
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}
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else
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{
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unsigned int errcnt = (stat & EMC_NFINTS_ERRCNT_MASK) >> EMC_NFINTS_ERRCNT_BIT;
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switch (errcnt)
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{
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case 4:
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rs_correct(data, (REG_EMC_NFERR3 & EMC_NFERR_INDEX_MASK) >> EMC_NFERR_INDEX_BIT, (REG_EMC_NFERR3 & EMC_NFERR_MASK_MASK) >> EMC_NFERR_MASK_BIT);
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break;
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case 3:
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rs_correct(data, (REG_EMC_NFERR2 & EMC_NFERR_INDEX_MASK) >> EMC_NFERR_INDEX_BIT, (REG_EMC_NFERR2 & EMC_NFERR_MASK_MASK) >> EMC_NFERR_MASK_BIT);
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break;
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case 2:
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rs_correct(data, (REG_EMC_NFERR1 & EMC_NFERR_INDEX_MASK) >> EMC_NFERR_INDEX_BIT, (REG_EMC_NFERR1 & EMC_NFERR_MASK_MASK) >> EMC_NFERR_MASK_BIT);
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break;
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case 1:
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rs_correct(data, (REG_EMC_NFERR0 & EMC_NFERR_INDEX_MASK) >> EMC_NFERR_INDEX_BIT, (REG_EMC_NFERR0 & EMC_NFERR_MASK_MASK) >> EMC_NFERR_MASK_BIT);
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break;
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}
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}
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}
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return 0;
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}
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static inline void nand_send_readaddr(unsigned int pageaddr, unsigned int offset)
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{
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int i;
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/* Read command */
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REG_NAND_CMD = 0x00;
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/* Write column address */
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for (i = 0; i < chip_info->col_cycles; i++)
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{
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REG_NAND_ADDR = offset & 0xFF;
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offset = offset >> 8;
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}
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/* Write row address */
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for (i = 0; i < chip_info->row_cycles; i++)
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{
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REG_NAND_ADDR = pageaddr & 0xFF;
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pageaddr = pageaddr >> 8;
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}
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}
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static inline void nand_send_readcacheaddr(unsigned short offset)
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{
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REG_NAND_CMD = 0x05;
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REG_NAND_ADDR = (unsigned char)((offset & 0x000000FF) >> 0);
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REG_NAND_ADDR = (unsigned char)((offset & 0x0000FF00) >> 8);
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REG_NAND_CMD = 0xe0;
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}
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static inline int nand_read_oob(int page, unsigned char *data)
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{
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unsigned short i;
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nand_send_readaddr(page, chip_info->page_size);
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REG_NAND_CMD = 0x30;
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nand_wait_ready();
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for ( i = 0; i < NAND_OOB_SIZE; i++)
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*data++ = REG_NAND_ADDR;
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return 0;
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}
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static int nand_read_page_info(int page, struct nand_page_info_t *info)
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{
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int ret;
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JZ_NAND_SELECT;
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ret = nand_read_oob(page, (unsigned char*)info);
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JZ_NAND_DESELECT;
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return ret;
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}
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static struct nand_page_info_t page_info;
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int jz_nand_read_page (int page, unsigned char *data)
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{
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int ret, i;
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JZ_NAND_SELECT;
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ret = nand_read_oob(page, &page_info);
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nand_send_readcacheaddr(0);
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/* TODO: use information from page_info */
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for ( i = 0; i < chip_info->page_size; i++)
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*data++ = REG_NAND_ADDR;
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JZ_NAND_DESELECT;
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return ret;
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}
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int ata_read_sectors(IF_MV2(int drive,) unsigned long start, int count, void* buf)
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{
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(void)start;
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(void)count;
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(void)buf;
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return 0;
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}
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int ata_write_sectors(IF_MV2(int drive,) unsigned long start, int count, const void* buf)
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{
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(void)start;
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(void)count;
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(void)buf;
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return 0;
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}
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int ata_init(void)
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{
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/* Read/Write timings */
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#define SET_STANDARD_TIMING(x) x = (((x) & ~0xFF) | 0x4621200)
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SET_STANDARD_TIMING(REG_EMC_SMCR1);
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SET_STANDARD_TIMING(REG_EMC_SMCR2);
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SET_STANDARD_TIMING(REG_EMC_SMCR3);
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SET_STANDARD_TIMING(REG_EMC_SMCR4);
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/* Set NFE bit */
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REG_EMC_NFCSR = EMC_NFCSR_NFE1;
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__nand_ecc_disable();
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unsigned char cData[5];
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JZ_NAND_SELECT;
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REG_NAND_CMD = NAND_CMD_READ_ID1;
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REG_NAND_ADDR = NAND_CMD_READ1_00;
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cData[0] = REG_NAND_DATA;
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cData[1] = REG_NAND_DATA;
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cData[2] = REG_NAND_DATA;
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cData[3] = REG_NAND_DATA;
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cData[4] = REG_NAND_DATA;
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JZ_NAND_DESELECT;
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chip_info = nand_identify(cData);
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if(chip_info == NULL)
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{
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panicf("Unknown NAND flash chip: 0x%x 0x%x 0x%x 0x%x 0x%x", cData[0],
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cData[1], cData[2], cData[3], cData[4]);
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return -1;
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}
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/* Set timings */
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return 0;
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}
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