5f53612441
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@26223 a1c6a512-1295-4272-9138-f99709370657
237 lines
14 KiB
C
237 lines
14 KiB
C
/***************************************************************************
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* __________ __ ___.
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* Open \______ \ ____ ____ | | _\_ |__ _______ ___
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* Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
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* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
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* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
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* \/ \/ \/ \/ \/
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* $Id$
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*
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* Copyright © 2010 Amaury Pouly
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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*
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* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
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* KIND, either express or implied.
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*
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****************************************************************************/
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#ifndef __USB_DRV_AS3525v2_H__
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#define __USB_DRV_AS3525v2_H__
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#include "as3525v2.h"
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#define USB_DEVICE (USB_BASE + 0x0800) /** USB Device base address */
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/**
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* Core Global Registers
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*/
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#define USB_GOTGCTL (*(volatile unsigned long *)(USB_BASE + 0x000)) /** OTG Control and Status Register */
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#define USB_GOTGINT (*(volatile unsigned long *)(USB_BASE + 0x004)) /** OTG Interrupt Register */
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#define USB_GAHBCFG (*(volatile unsigned long *)(USB_BASE + 0x008)) /** Core AHB Configuration Register */
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#define USB_GUSBCFG (*(volatile unsigned long *)(USB_BASE + 0x00C)) /** Core USB Configuration Register */
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#define USB_GRSTCTL (*(volatile unsigned long *)(USB_BASE + 0x010)) /** Core Reset Register */
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#define USB_GINTSTS (*(volatile unsigned long *)(USB_BASE + 0x014)) /** Core Interrupt Register */
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#define USB_GINTMSK (*(volatile unsigned long *)(USB_BASE + 0x018)) /** Core Interrupt Mask Register */
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#define USB_GRXSTSR (*(volatile unsigned long *)(USB_BASE + 0x01C)) /** Receive Status Debug Read Register (Read Only) */
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#define USB_GRXSTSP (*(volatile unsigned long *)(USB_BASE + 0x020)) /** Receive Status Read /Pop Register (Read Only) */
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#define USB_GRXFSIZ (*(volatile unsigned long *)(USB_BASE + 0x024)) /** Receive FIFO Size Register */
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#define USB_GNPTXFSIZ (*(volatile unsigned long *)(USB_BASE + 0x028)) /** Periodic Transmit FIFO Size Register */
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#define USB_GNPTXSTS (*(volatile unsigned long *)(USB_BASE + 0x02C)) /** Non-Periodic Transmit FIFO/Queue Status Register */
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#define USB_GI2CCTL (*(volatile unsigned long *)(USB_BASE + 0x030)) /** I2C Access Register */
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#define USB_GPVNDCTL (*(volatile unsigned long *)(USB_BASE + 0x034)) /** PHY Vendor Control Register */
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#define USB_GGPIO (*(volatile unsigned long *)(USB_BASE + 0x038)) /** General Purpose Input/Output Register */
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#define USB_GUID (*(volatile unsigned long *)(USB_BASE + 0x03C)) /** User ID Register */
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#define USB_GSNPSID (*(volatile unsigned long *)(USB_BASE + 0x040)) /** Synopsys ID Register */
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#define USB_GHWCFG1 (*(volatile unsigned long *)(USB_BASE + 0x044)) /** User HW Config1 Register */
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#define USB_GHWCFG2 (*(volatile unsigned long *)(USB_BASE + 0x048)) /** User HW Config2 Register */
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#define USB_GHWCFG3 (*(volatile unsigned long *)(USB_BASE + 0x04C)) /** User HW Config3 Register */
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#define USB_GHWCFG4 (*(volatile unsigned long *)(USB_BASE + 0x050)) /** User HW Config4 Register */
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/* 1<=ep<=15, don't use ep=0 !!! */
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/** Device IN Endpoint Transmit FIFO (ep) Size Register */
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#define USB_DIEPTXFSIZ(ep) (*(volatile unsigned long *)(USB_BASE + 0x100 + 4 * (ep)))
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#define USB_MAKE_FIFOSIZE_DATA(startadr, depth) \
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(((startadr) & 0xffff) | ((depth) << 16))
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#define USB_GET_FIFOSIZE_DEPTH(data) \
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((data) >> 16)
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#define USB_GET_FIFOSIZE_START_ADR(data) \
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((data) & 0xffff)
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#define USB_GRSTCTL_csftrst (1 << 0) /** Core soft reset */
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#define USB_GRSTCTL_hsftrst (1 << 1) /** Hclk soft reset */
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#define USB_GRSTCTL_intknqflsh (1 << 3) /** In Token Sequence Learning Queue Flush */
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#define USB_GRSTCTL_txfnum_bit_pos 6 /** TxFIFO Number */
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#define USB_GRSTCTL_txfnum_bits (0x1f << 6)
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#define USB_GRSTCTL_txfflsh_flush (1 << 5) /** TxFIFO Flush */
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#define USB_GRSTCTL_rxfflsh_flush (1 << 4) /** RxFIFO Flush */
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#define USB_GRSTCTL_ahbidle (1 << 31) /** AHB idle state*/
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#define USB_GHWCFG1_IN_EP(ep) ((USB_GHWCFG1 >> ((ep) *2)) & 0x1) /** 1 if EP(ep) has in cap */
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#define USB_GHWCFG1_OUT_EP(ep) ((USB_GHWCFG1 >> ((ep) *2 + 1)) & 0x1)/** 1 if EP(ep) has out cap */
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#define USB_GHWCFG2_ARCH ((USB_GHWCFG2 >> 3) & 0x3) /** Architecture */
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#define USB_GHWCFG2_HS_PHY_TYPE ((USB_GHWCFG2 >> 6) & 0x3) /** High speed PHY type */
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#define USB_GHWCFG2_FS_PHY_TYPE ((USB_GHWCFG2 >> 8) & 0x3) /** Full speed PHY type */
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#define USB_GHWCFG2_NUM_EP ((USB_GHWCFG2 >> 10) & 0xf) /** Number of endpoints */
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#define USB_GHWCFG2_DYN_FIFO ((USB_GHWCFG2 >> 19) & 0x1) /** Dynamic FIFO */
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#define USB_PHY_TYPE_UNSUPPORTED 0
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#define USB_PHY_TYPE_UTMI 1
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#define USB_INT_DMA_ARCH 2
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#define USB_GHWCFG3_DFIFO_LEN (USB_GHWCFG3 >> 16) /** Total fifo size */
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#define USB_GHWCFG4_UTMI_PHY_DATA_WIDTH ((USB_GHWCFG4 >> 14) & 0x3)
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#define USB_GHWCFG4_DED_FIFO_EN ((USB_GHWCFG4 >> 25) & 0x1)
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#define USB_GHWCFG4_NUM_IN_EP ((USB_GHWCFG4 >> 26) & 0xf) /** Number of IN endpoints */
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#define USB_GUSBCFG_ulpi_utmi_sel (1 << 4) /** select ulpi:1 or utmi:0 */
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#define USB_GUSBCFG_phy_if (1 << 3) /** select utmi bus width ? */
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#define USB_GUSBCFG_SRP_cap 0x100
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#define USB_GUSBCFG_HNP_cap 0x200
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#define USB_GAHBCFG_glblintrmsk (1 << 0)
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#define USB_GAHBCFG_hburstlen_bit_pos 1
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#define USB_GAHBCFG_INT_DMA_BURST_INCR 1 /** note: the linux patch has several other value, this is one picked for internal dma */
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#define USB_GAHBCFG_dma_enable (1 << 5)
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#define USB_GINTMSK_usb_rst 0x00001000 /*!< USB Reset Mask */
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#define USB_GINTMSK_EnumDone 0x00000200 /*!< Enumeration Done Mask */
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#define USB_GINTMSK_ErlySusp 0x00000400 /*!< Early Suspend Mask */
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#define USB_GINTMSK_USBSusp 0x00000800 /*!< USB Suspend Mask */
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#define USB_GINTMSK_SOF 0x00000008 /*!< Start of (micro)Frame Mask */
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#define USB_GINTMSK_NPTxFEmp 0x00000020 /*!< Non-periodic TxFIFO Empty Mask */
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#define USB_GINTMSK_wkupintr (1 << 31)
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#define USB_GINTMSK_sessreqintr (1 << 30)
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#define USB_GINTMSK_disconnect (1 << 29)
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#define USB_GINTMSK_conidstschng (1 << 28)
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#define USB_GINTMSK_ptxfempty (1 << 26)
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#define USB_GINTMSK_hcintr (1 << 25)
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#define USB_GINTMSK_portintr (1 << 24)
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#define USB_GINTMSK_incomplisoout (1 << 21)
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#define USB_GINTMSK_incomplisoin (1 << 20)
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#define USB_GINTMSK_outepintr (1 << 19)
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#define USB_GINTMSK_inepintr (1 << 18)
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#define USB_GINTMSK_epmismatch (1 << 17)
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#define USB_GINTMSK_eopframe (1 << 15)
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#define USB_GINTMSK_isooutdrop (1 << 14)
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#define USB_GINTMSK_enumdone (1 << 13)
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#define USB_GINTMSK_usbreset (1 << 12)
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#define USB_GINTMSK_usbsuspend (1 << 11)
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#define USB_GINTMSK_erlysuspend (1 << 10)
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#define USB_GINTMSK_i2cintr (1 << 9)
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#define USB_GINTMSK_goutnakeff (1 << 7)
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#define USB_GINTMSK_ginnakeff (1 << 6)
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#define USB_GINTMSK_nptxfempty (1 << 5)
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#define USB_GINTMSK_rxstsqlvl (1 << 4)
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#define USB_GINTMSK_sofintr (1 << 3)
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#define USB_GINTMSK_otgintr (1 << 2)
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#define USB_GINTMSK_modemismatch (1 << 1)
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/**
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* Device Registers Base Addresses
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*/
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#define USB_DCFG (*(volatile unsigned long *)(USB_DEVICE + 0x00)) /** Device Configuration Register */
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#define USB_DCTL (*(volatile unsigned long *)(USB_DEVICE + 0x04)) /** Device Control Register */
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#define USB_DSTS (*(volatile unsigned long *)(USB_DEVICE + 0x08)) /** Device Status Register */
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#define USB_DIEPMSK (*(volatile unsigned long *)(USB_DEVICE + 0x10)) /** Device IN Endpoint Common Interrupt Mask Register */
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#define USB_DOEPMSK (*(volatile unsigned long *)(USB_DEVICE + 0x14)) /** Device OUT Endpoint Common Interrupt Mask Register */
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#define USB_DAINT (*(volatile unsigned long *)(USB_DEVICE + 0x18)) /** Device All Endpoints Interrupt Register */
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#define USB_DAINTMSK (*(volatile unsigned long *)(USB_DEVICE + 0x1C)) /** Device Endpoints Interrupt Mask Register */
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#define USB_DTKNQR1 (*(volatile unsigned long *)(USB_DEVICE + 0x20)) /** Device IN Token Sequence Learning Queue Read Register 1 */
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#define USB_DTKNQR2 (*(volatile unsigned long *)(USB_DEVICE + 0x24)) /** Device IN Token Sequence Learning Queue Register 2 */
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#define USB_DTKNQP (*(volatile unsigned long *)(USB_DEVICE + 0x28)) /** Device IN Token Queue Pop register */
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/* fixme: those registers are not present in usb_registers.h but are in dwc_otgh_regs.h.
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* the previous registers exists but has a different name :( */
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#define USB_DVBUSDIS (*(volatile unsigned long *)(USB_DEVICE + 0x28)) /** Device VBUS discharge register*/
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#define USB_DVBUSPULSE (*(volatile unsigned long *)(USB_DEVICE + 0x2C)) /** Device VBUS pulse register */
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#define USB_DTKNQR3 (*(volatile unsigned long *)(USB_DEVICE + 0x30)) /** Device IN Token Queue Read Register 3 (RO) */
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#define USB_DTHRCTL (*(volatile unsigned long *)(USB_DEVICE + 0x30)) /** Device Thresholding control register */
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#define USB_DTKNQR4 (*(volatile unsigned long *)(USB_DEVICE + 0x34)) /** Device IN Token Queue Read Register 4 (RO) */
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#define USB_FFEMPTYMSK (*(volatile unsigned long *)(USB_DEVICE + 0x34)) /** Device IN EPs empty Inr. Mask Register */
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#define USB_DCFG_devspd_bits 0x3
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#define USB_DCFG_devspd_hs_phy_hs 0 /** High speed PHY running at high speed */
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#define USB_DCFG_devspd_hs_phy_fs 1 /** High speed PHY running at full speed */
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#define USB_DCFG_perfrint_bit_pos 11 /** Periodic Frame Interval */
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#define USB_DCFG_perfrint_bits (0x3 << USB_DCFG_perfrint_bit_pos)
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#define USB_DCFG_FRAME_INTERVAL_80 0
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#define USB_DCFG_FRAME_INTERVAL_85 1
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#define USB_DCFG_FRAME_INTERVAL_90 2
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#define USB_DCFG_FRAME_INTERVAL_95 3
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#define USB_DTHRCTL_non_iso_thr_en (1 << 0)
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#define USB_DTHRCTL_iso_thr_en (1 << 1)
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#define USB_DTHRCTL_tx_thr_len_bit_pos 2
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#define USB_DTHRCTL_tx_thr_len_bits (0x1FF << USB_DTHRCTL_tx_thr_len_bit_pos)
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#define USB_DTHRCTL_rx_thr_en (1 << 16)
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#define USB_DTHRCTL_rx_thr_len_bit_pos 17
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#define USB_DTHRCTL_rx_thr_len_bits (0x1FF << USB_DTHRCTL_rx_thr_len_bit_pos)
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/* 0<=ep<=15, you can use ep=0 */
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/** Device IN Endpoint (ep) Control Register */
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#define USB_DIEPCTL(ep) (*(volatile unsigned long *)(USB_DEVICE + 0x100 + (ep) * 0x20))
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/** Device IN Endpoint (ep) Interrupt Register */
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#define USB_DIEPINT(ep) (*(volatile unsigned long *)(USB_DEVICE + 0x100 + (ep) * 0x20 + 0x8))
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/** Device IN Endpoint (ep) Transfer Size Register */
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#define USB_DIEPTSIZ(ep) (*(volatile unsigned long *)(USB_DEVICE + 0x100 + (ep) * 0x20 + 0x10))
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/** Device IN Endpoint (ep) DMA Address Register */
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#define USB_DIEPDMA(ep) (*(volatile unsigned long *)(USB_DEVICE + 0x100 + (ep) * 0x20 + 0x14))
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/** Device IN Endpoint (ep) Transmit FIFO Status Register */
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#define USB_DTXFSTS(ep) (*(volatile unsigned long *)(USB_DEVICE + 0x100 + (ep) * 0x20 + 0x18))
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/* the following also apply to DIEPMSK */
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#define USB_DIEPINT_xfercompl (1 << 0) /** Transfer complete */
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#define USB_DIEPINT_epdisabled (1 << 1) /** Endpoint disabled */
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#define USB_DIEPINT_ahberr (1 << 2) /** AHB error */
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#define USB_DIEPINT_timeout (1 << 3) /** Timeout handshake (non-iso TX) */
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#define USB_DIEPINT_intktxfemp (1 << 4) /** IN token received with tx fifo empty */
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#define USB_DIEPINT_intknepmis (1 << 5) /** IN token received with ep mismatch */
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#define USB_DIEPINT_inepnakeff (1 << 6) /** IN endpoint NAK effective */
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#define USB_DIEPINT_emptyintr (1 << 7) /** linux doc broken on this, empty fifo ? */
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#define USB_DIEPINT_txfifoundrn (1 << 8) /** linux doc void on this, tx fifo underrun ? */
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/** Device OUT Endpoint (ep) Control Register */
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#define USB_DOEPCTL(ep) (*(volatile unsigned long *)(USB_DEVICE + 0x300 + (ep) * 0x20))
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/** Device OUT Endpoint (ep) Frame number Register */
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#define USB_DOEPFN(ep) (*(volatile unsigned long *)(USB_DEVICE + 0x300 + (ep) * 0x20 + 0x4))
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/** Device Endpoint (ep) Interrupt Register */
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#define USB_DOEPINT(ep) (*(volatile unsigned long *)(USB_DEVICE + 0x300 + (ep) * 0x20 + 0x8))
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/** Device OUT Endpoint (ep) Transfer Size Register */
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#define USB_DOEPTSIZ(ep) (*(volatile unsigned long *)(USB_DEVICE + 0x300 + (ep) * 0x20 + 0x10))
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/** Device Endpoint (ep) DMA Address Register */
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#define USB_DOEPDMA(ep) (*(volatile unsigned long *)(USB_DEVICE + 0x300 + (ep) * 0x20 + 0x14))
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#define USB_PCGCCTL (*(volatile unsigned long *)(USB_BASE + 0xE00)) /** Power and Clock Gating Control Register */
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#define USB_DEPCTL_epena (1 << 31) /** Endpoint enable */
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#define USB_DEPCTL_epdis (1 << 30) /** Endpoint disable */
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#define USB_DEPCTL_snak (1 << 27) /** Set NAK */
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#define USB_DEPCTL_cnak (1 << 28) /** Clear NAK */
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/**
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* Parameters
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*/
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#ifdef USB_USE_CUSTOM_FIFO_LAYOUT
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/* Data fifo: includes RX fifo, non period TX fifo and periodic fifos
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* NOTE: this is a hardware parameter, it cannot be changed ! */
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#define USB_DATA_FIFO_DEPTH 1333u
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/* size of the FX fifo */
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#define USB_RX_FIFO_SIZE 256u
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/* size of the non periodic TX fifo */
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#define USB_NPTX_FIFO_SIZE 256u
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/* size of each TX ep fifo size */
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#define USB_EPTX_FIFO_SIZE 256u
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#endif /* USB_USE_CUSTOM_FIFO_LAYOUT */
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/* Number of IN/OUT endpoints */
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#define USB_NUM_IN_EP 3u
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#define USB_NUM_OUT_EP 2u
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#endif /* __USB_DRV_AS3525v2_H__ */
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