905e19905b
This appears to solve _some_ of the crashes experienced when using gcc494 on the multicore PP targets (eg most older ipods). (With this change, the asm vs plain-C versions behave identically) corelock_lock(), corelock_unlock(), and corelock_trylock() were declared with the 'naked' attribute. However, naked functions are only allowed to have 'Basic Asm' components, and we used some extended asm, but without declaring clobbered registers, making assumptions about register arguments, and also directly returned to the caller via asm code. This is what the GCC docs have to say about this stuff: "While using extended asm or a mixture of basic asm and C code may appear to work, they cannot be depended upon to work reliably and are not supported." Change-Id: I79a9c4895584f9af365e6c2387595e9c45d89c7d
99 lines
4.1 KiB
C
99 lines
4.1 KiB
C
/***************************************************************************
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* __________ __ ___.
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* Open \______ \ ____ ____ | | _\_ |__ _______ ___
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* Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
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* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
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* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
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* \/ \/ \/ \/ \/
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* $Id$
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*
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* Copyright (C) 2007 by Daniel Ankers
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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*
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* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
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* KIND, either express or implied.
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*
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****************************************************************************/
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/* Core locks using Peterson's mutual exclusion algorithm.
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* ASM optimized version of C code, see firmware/asm/corelock.c */
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#include "cpu.h"
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/*---------------------------------------------------------------------------
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* Wait for the corelock to become free and acquire it when it does.
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*---------------------------------------------------------------------------
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*/
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void corelock_lock(struct corelock *cl)
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{
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/* Relies on the fact that core IDs are complementary bitmasks (0x55,0xaa) */
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asm volatile (
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"mov r1, %[id] \n" /* r1 = PROCESSOR_ID */
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"ldrb r1, [r1] \n"
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"strb r1, [%[cl], r1, lsr #7] \n" /* cl->myl[core] = core */
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"eor r2, r1, #0xff \n" /* r2 = othercore */
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"strb r2, [%[cl], #2] \n" /* cl->turn = othercore */
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"1: \n"
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"ldrb r2, [%[cl], r2, lsr #7] \n" /* cl->myl[othercore] == 0 ? */
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"cmp r2, #0 \n" /* yes? lock acquired */
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"beq 2f \n"
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"ldrb r2, [%[cl], #2] \n" /* || cl->turn == core ? */
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"cmp r2, r1 \n"
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"bne 1b \n" /* no? try again */
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"2: \n" /* Done */
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:
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: [id] "i"(&PROCESSOR_ID), [cl] "r" (cl)
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: "r1","r2","cc"
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);
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}
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/*---------------------------------------------------------------------------
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* Try to aquire the corelock. If free, caller gets it, otherwise return 0.
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*---------------------------------------------------------------------------
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*/
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int corelock_try_lock(struct corelock *cl)
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{
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int rval = 0;
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/* Relies on the fact that core IDs are complementary bitmasks (0x55,0xaa) */
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asm volatile (
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"mov r1, %[id] \n" /* r1 = PROCESSOR_ID */
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"ldrb r1, [r1] \n"
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"strb r1, [%[cl], r1, lsr #7] \n" /* cl->myl[core] = core */
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"eor r2, r1, #0xff \n" /* r2 = othercore */
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"strb r2, [%[cl], #2] \n" /* cl->turn = othercore */
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"ldrb %[rv], [%[cl], r2, lsr #7] \n" /* cl->myl[othercore] == 0 ? */
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"eors %[rv], %[rv], r2 \n"
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"bne 1f \n" /* yes? lock acquired */
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"ldrb %[rv], [%[cl], #2] \n" /* || cl->turn == core? */
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"ands %[rv], %[rv], r1 \n"
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"streqb %[rv], [%[cl], r1, lsr #7] \n" /* if not, cl->myl[core] = 0 */
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"1: \n" /* Done */
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: [rv] "=r"(rval)
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: [id] "i" (&PROCESSOR_ID), [cl] "r" (cl)
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: "r1","r2","cc"
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);
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return rval;
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}
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/*---------------------------------------------------------------------------
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* Release ownership of the corelock
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*---------------------------------------------------------------------------
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*/
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void corelock_unlock(struct corelock *cl)
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{
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asm volatile (
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"mov r1, %[id] \n" /* r1 = PROCESSOR_ID */
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"ldrb r1, [r1] \n"
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"mov r2, #0 \n" /* cl->myl[core] = 0 */
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"strb r2, [%[cl], r1, lsr #7] \n"
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:
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: [id] "i" (&PROCESSOR_ID), [cl] "r" (cl)
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: "r1","r2"
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);
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}
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