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rockbox/utils/regtools/desc/regs-rk27xx.xml
Marcin Bukat bb48fa02d2 regtools: Convert rk27xx register description file to v2 format 
Change-Id: I60a764567d2fc73ed87fca2a8b0eaf643d4984bc
2016-03-14 13:51:33 +01:00

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<?xml version="1.0"?>
<soc version="2">
<name>rk27xx</name>
<title>Rockchip rk27xx</title>
<author>Marcin Bukat</author>
<version>1.1</version>
<node>
<name>GPIO0</name>
<title>GPIO</title>
<desc>GPIO</desc>
<instance>
<name>GPIO0</name>
<address>0x1800c000</address>
</instance>
<node>
<name>PADR</name>
<instance>
<name>PADR</name>
<address>0x0</address>
</instance>
<register/>
</node>
<node>
<name>PACON</name>
<instance>
<name>PACON</name>
<address>0x4</address>
</instance>
<register/>
</node>
<node>
<name>PBDR</name>
<instance>
<name>PBDR</name>
<address>0x8</address>
</instance>
<register/>
</node>
<node>
<name>PBCON</name>
<instance>
<name>PBCON</name>
<address>0xc</address>
</instance>
<register/>
</node>
<node>
<name>PCDR</name>
<instance>
<name>PCDR</name>
<address>0x10</address>
</instance>
<register/>
</node>
<node>
<name>PCCON</name>
<instance>
<name>PCCON</name>
<address>0x14</address>
</instance>
<register/>
</node>
<node>
<name>PDDR</name>
<instance>
<name>PDDR</name>
<address>0x18</address>
</instance>
<register/>
</node>
<node>
<name>PDCON</name>
<instance>
<name>PDCON</name>
<address>0x1c</address>
</instance>
<register/>
</node>
<node>
<name>TEST</name>
<instance>
<name>TEST</name>
<address>0x20</address>
</instance>
<register/>
</node>
<node>
<name>IEA</name>
<instance>
<name>IEA</name>
<address>0x24</address>
</instance>
<register/>
</node>
<node>
<name>IEB</name>
<instance>
<name>IEB</name>
<address>0x28</address>
</instance>
<register/>
</node>
<node>
<name>IEC</name>
<instance>
<name>IEC</name>
<address>0x2c</address>
</instance>
<register/>
</node>
<node>
<name>IED</name>
<instance>
<name>IED</name>
<address>0x30</address>
</instance>
<register/>
</node>
<node>
<name>ISA</name>
<instance>
<name>ISA</name>
<address>0x34</address>
</instance>
<register/>
</node>
<node>
<name>ISB</name>
<instance>
<name>ISB</name>
<address>0x38</address>
</instance>
<register/>
</node>
<node>
<name>ISC</name>
<instance>
<name>ISC</name>
<address>0x3c</address>
</instance>
<register/>
</node>
<node>
<name>ISD</name>
<instance>
<name>ISD</name>
<address>0x40</address>
</instance>
<register/>
</node>
<node>
<name>IBEA</name>
<instance>
<name>IBEA</name>
<address>0x44</address>
</instance>
<register/>
</node>
<node>
<name>IBEB</name>
<instance>
<name>IBEB</name>
<address>0x48</address>
</instance>
<register/>
</node>
<node>
<name>IBEC</name>
<instance>
<name>IBEC</name>
<address>0x4c</address>
</instance>
<register/>
</node>
<node>
<name>IBED</name>
<instance>
<name>IBED</name>
<address>0x50</address>
</instance>
<register/>
</node>
<node>
<name>IEVA</name>
<instance>
<name>IEVA</name>
<address>0x54</address>
</instance>
<register/>
</node>
<node>
<name>IEVB</name>
<instance>
<name>IEVB</name>
<address>0x58</address>
</instance>
<register/>
</node>
<node>
<name>IEVC</name>
<instance>
<name>IEVC</name>
<address>0x5c</address>
</instance>
<register/>
</node>
<node>
<name>IEVD</name>
<instance>
<name>IEVD</name>
<address>0x60</address>
</instance>
<register/>
</node>
<node>
<name>ICA</name>
<instance>
<name>ICA</name>
<address>0x64</address>
</instance>
<register/>
</node>
<node>
<name>ICB</name>
<instance>
<name>ICB</name>
<address>0x68</address>
</instance>
<register/>
</node>
<node>
<name>ICC</name>
<instance>
<name>ICC</name>
<address>0x6c</address>
</instance>
<register/>
</node>
<node>
<name>ICD</name>
<instance>
<name>ICD</name>
<address>0x70</address>
</instance>
<register/>
</node>
<node>
<name>ISR</name>
<instance>
<name>ISR</name>
<address>0x74</address>
</instance>
<register/>
</node>
</node>
<node>
<name>WDT</name>
<title>Watchdog</title>
<desc>Watchdog</desc>
<instance>
<name>WDT</name>
<address>0x18010000</address>
</instance>
<node>
<name>LR</name>
<instance>
<name>LR</name>
<address>0x0</address>
</instance>
<register/>
</node>
<node>
<name>CVR</name>
<instance>
<name>CVR</name>
<address>0x4</address>
</instance>
<register/>
</node>
<node>
<name>CON</name>
<instance>
<name>CON</name>
<address>0x8</address>
</instance>
<register/>
</node>
</node>
<node>
<name>RTC</name>
<title>Real time clock</title>
<desc>Real time clock</desc>
<instance>
<name>RTC</name>
<address>0x18014000</address>
</instance>
<node>
<name>TIME</name>
<instance>
<name>TIME</name>
<address>0x0</address>
</instance>
<register/>
</node>
<node>
<name>DATE</name>
<instance>
<name>DATE</name>
<address>0x4</address>
</instance>
<register/>
</node>
<node>
<name>TALARM</name>
<instance>
<name>TALARM</name>
<address>0x8</address>
</instance>
<register/>
</node>
<node>
<name>DALARM</name>
<instance>
<name>DALARM</name>
<address>0xc</address>
</instance>
<register/>
</node>
<node>
<name>CTRL</name>
<instance>
<name>CTRL</name>
<address>0x10</address>
</instance>
<register/>
</node>
<node>
<name>RESET</name>
<instance>
<name>RESET</name>
<address>0x14</address>
</instance>
<register/>
</node>
<node>
<name>PWOFF</name>
<instance>
<name>PWOFF</name>
<address>0x18</address>
</instance>
<register/>
</node>
<node>
<name>PWFAIL</name>
<instance>
<name>PWFAIL</name>
<address>0x1c</address>
</instance>
<register/>
</node>
</node>
<node>
<name>SPI</name>
<title>Serial peripherial interface</title>
<desc>Serial peripherial interface</desc>
<instance>
<name>SPI</name>
<address>0x18018000</address>
</instance>
<node>
<name>TXR</name>
<instance>
<name>TXR</name>
<address>0x0</address>
</instance>
<register/>
</node>
<node>
<name>RXR</name>
<instance>
<name>RXR</name>
<address>0x0</address>
</instance>
<register/>
</node>
<node>
<name>IER</name>
<instance>
<name>IER</name>
<address>0x4</address>
</instance>
<register/>
</node>
<node>
<name>FCR</name>
<instance>
<name>FCR</name>
<address>0x8</address>
</instance>
<register/>
</node>
<node>
<name>FWCR</name>
<instance>
<name>FWCR</name>
<address>0xc</address>
</instance>
<register/>
</node>
<node>
<name>DLYCR</name>
<instance>
<name>DLYCR</name>
<address>0x10</address>
</instance>
<register/>
</node>
<node>
<name>TXCR</name>
<instance>
<name>TXCR</name>
<address>0x14</address>
</instance>
<register/>
</node>
<node>
<name>RXCR</name>
<instance>
<name>RXCR</name>
<address>0x18</address>
</instance>
<register/>
</node>
<node>
<name>SSCR</name>
<instance>
<name>SSCR</name>
<address>0x1c</address>
</instance>
<register/>
</node>
<node>
<name>ISR</name>
<instance>
<name>ISR</name>
<address>0x20</address>
</instance>
<register/>
</node>
</node>
<node>
<name>SCU</name>
<title>System control unit</title>
<desc>System control unit</desc>
<instance>
<name>SCU</name>
<address>0x1801c000</address>
</instance>
<node>
<name>ID</name>
<instance>
<name>ID</name>
<address>0x0</address>
</instance>
<register>
<field>
<name>SOC_ID</name>
<position>0</position>
<width>32</width>
<enum>
<name>REVISION_B</name>
<value>0xa100027b</value>
</enum>
<enum>
<name>REVISION_A</name>
<value>0xa1000604</value>
</enum>
</field>
</register>
</node>
<node>
<name>REMAP</name>
<instance>
<name>REMAP</name>
<address>0x4</address>
</instance>
<register>
<field>
<name>MEM_REMAP</name>
<position>0</position>
<width>32</width>
<enum>
<name>ROM_0x000000</name>
<value>0x0</value>
</enum>
<enum>
<name>IRAM_0x000000</name>
<value>0xdeadbeef</value>
</enum>
</field>
</register>
</node>
<node>
<name>PLLCON1</name>
<instance>
<name>PLLCON1</name>
<address>0x8</address>
</instance>
<register>
<field>
<name>ARM_PLL_TEST_CONTROL</name>
<position>25</position>
<enum>
<name>NORMAL</name>
<value>0x0</value>
</enum>
<enum>
<name>TEST</name>
<value>0x1</value>
</enum>
</field>
<field>
<name>ARM_PLL_SATURATION</name>
<position>24</position>
<enum>
<name>DISABLE</name>
<value>0x0</value>
</enum>
<enum>
<name>ENABLE</name>
<value>0x1</value>
</enum>
</field>
<field>
<name>ARM_PLL_FAST_LOCK</name>
<position>23</position>
<enum>
<name>DISABLE</name>
<value>0x0</value>
</enum>
<enum>
<name>ENABLE</name>
<value>0x1</value>
</enum>
</field>
<field>
<name>ARM_PLL_POWERDOWN</name>
<position>22</position>
<enum>
<name>PLL_ON</name>
<value>0x0</value>
</enum>
<enum>
<name>PLL_OFF</name>
<value>0x1</value>
</enum>
</field>
<field>
<name>ARM_PLL_CLKR</name>
<position>16</position>
<width>6</width>
</field>
<field>
<name>ARM_PLL_CLKF</name>
<position>4</position>
<width>12</width>
</field>
<field>
<name>ARM_PLL_CLKOD</name>
<position>1</position>
<width>3</width>
</field>
<field>
<name>ARM_PLL_BYPASS</name>
<position>0</position>
<enum>
<name>DISABLE</name>
<value>0x0</value>
</enum>
<enum>
<name>ENABLE</name>
<value>0x1</value>
</enum>
</field>
</register>
</node>
<node>
<name>PLLCON2</name>
<instance>
<name>PLLCON2</name>
<address>0xc</address>
</instance>
<register>
<field>
<name>DSP_PLL_TEST_CONTROL</name>
<position>25</position>
<enum>
<name>NORMAL</name>
<value>0x0</value>
</enum>
<enum>
<name>TEST</name>
<value>0x1</value>
</enum>
</field>
<field>
<name>DSP_PLL_SATURATION</name>
<position>24</position>
<enum>
<name>DISABLE</name>
<value>0x0</value>
</enum>
<enum>
<name>ENABLE</name>
<value>0x1</value>
</enum>
</field>
<field>
<name>DSP_PLL_FAST_LOCK</name>
<position>23</position>
<enum>
<name>DISABLE</name>
<value>0x0</value>
</enum>
<enum>
<name>ENABLE</name>
<value>0x1</value>
</enum>
</field>
<field>
<name>DSP_PLL_POWERDOWN</name>
<position>22</position>
<enum>
<name>PLL_ON</name>
<value>0x0</value>
</enum>
<enum>
<name>PLL_OFF</name>
<value>0x1</value>
</enum>
</field>
<field>
<name>DSP_PLL_CLKR</name>
<position>16</position>
<width>6</width>
</field>
<field>
<name>DSP_PLL_CLKF</name>
<position>4</position>
<width>12</width>
</field>
<field>
<name>DSP_PLL_CLKOD</name>
<position>1</position>
<width>3</width>
</field>
<field>
<name>DSP_PLL_BYPASS</name>
<position>0</position>
<enum>
<name>DISABLE</name>
<value>0x0</value>
</enum>
<enum>
<name>ENABLE</name>
<value>0x1</value>
</enum>
</field>
</register>
</node>
<node>
<name>PLLCON3</name>
<instance>
<name>PLLCON3</name>
<address>0x10</address>
</instance>
<register>
<field>
<name>CODEC_PLL_TEST_CONTROL</name>
<position>25</position>
<enum>
<name>NORMAL</name>
<value>0x0</value>
</enum>
<enum>
<name>TEST</name>
<value>0x1</value>
</enum>
</field>
<field>
<name>CODEC_PLL_SATURATION</name>
<position>24</position>
<enum>
<name>DISABLE</name>
<value>0x0</value>
</enum>
<enum>
<name>ENABLE</name>
<value>0x1</value>
</enum>
</field>
<field>
<name>CODEC_PLL_FAST_LOCK</name>
<position>23</position>
<enum>
<name>DISABLE</name>
<value>0x0</value>
</enum>
<enum>
<name>ENABLE</name>
<value>0x1</value>
</enum>
</field>
<field>
<name>CODEC_PLL_POWERDOWN</name>
<position>22</position>
<enum>
<name>PLL_ON</name>
<value>0x0</value>
</enum>
<enum>
<name>PLL_OFF</name>
<value>0x1</value>
</enum>
</field>
<field>
<name>CODEC_PLL_CLKR</name>
<position>16</position>
<width>6</width>
</field>
<field>
<name>CODEC_PLL_CLKF</name>
<position>4</position>
<width>12</width>
</field>
<field>
<name>CODEC_PLL_CLKOD</name>
<position>1</position>
<width>3</width>
</field>
<field>
<name>CODEC_PLL_BYPASS</name>
<position>0</position>
<enum>
<name>DISABLE</name>
<value>0x0</value>
</enum>
<enum>
<name>ENABLE</name>
<value>0x1</value>
</enum>
</field>
</register>
</node>
<node>
<name>DIVCON1</name>
<instance>
<name>DIVCON1</name>
<address>0x14</address>
</instance>
<register>
<field>
<name>USB_PHY_CLK</name>
<position>31</position>
<enum>
<name>24MHz</name>
<value>0x0</value>
</enum>
<enum>
<name>12MHz</name>
<value>0x1</value>
</enum>
</field>
<field>
<name>VIP_SENSOR_CLK</name>
<position>29</position>
<width>2</width>
<enum>
<name>24MHz</name>
<value>0x0</value>
</enum>
<enum>
<name>48MHz</name>
<value>0x1</value>
</enum>
<enum>
<name>27MHz</name>
<value>0x2</value>
</enum>
</field>
<field>
<name>LCDC_CLK</name>
<position>28</position>
<enum>
<name>EXT_SOC_27MHz</name>
<value>0x0</value>
</enum>
<enum>
<name>LCDC_CLK_DIV_OUT</name>
<value>0x1</value>
</enum>
</field>
<field>
<name>LCDC_CLK_DIV</name>
<position>20</position>
<width>8</width>
</field>
<field>
<name>LCDC_CLK_DIV_SRC</name>
<position>18</position>
<width>2</width>
<enum>
<name>ARM_PLL</name>
<value>0x0</value>
</enum>
<enum>
<name>DSP_PLL</name>
<value>0x1</value>
</enum>
<enum>
<name>CODEC_PLL</name>
<value>0x2</value>
</enum>
</field>
<field>
<name>LSADC_CLK_DIV</name>
<position>10</position>
<width>8</width>
</field>
<field>
<name>CODEC_CLK_SRC</name>
<position>9</position>
<enum>
<name>CODEC_CLK_DIV_OUT</name>
<value>0x0</value>
</enum>
<enum>
<name>12MHz_OSC</name>
<value>0x1</value>
</enum>
</field>
<field>
<name>CODEC_CLK_DIV</name>
<position>5</position>
<width>4</width>
</field>
<field>
<name>PCLK_CLK_DIV</name>
<position>3</position>
<width>2</width>
<enum>
<name>HCLK_to_PCLK_1_1</name>
<value>0x0</value>
</enum>
<enum>
<name>HCLK_to_PCLK_2_1</name>
<value>0x1</value>
</enum>
<enum>
<name>HCLK_to_PCLK_4_1</name>
<value>0x2</value>
</enum>
</field>
<field>
<name>ARM_CLK_DIV</name>
<position>2</position>
<enum>
<name>ARMPLL_to_ARMCLK_1_1</name>
<value>0x0</value>
</enum>
<enum>
<name>ARMPLL_to_ARMCLK_2_1</name>
<value>0x1</value>
</enum>
</field>
<field>
<name>DSP_SLOW_MODE</name>
<position>1</position>
<enum>
<name>DISABLE</name>
<value>0x0</value>
</enum>
<enum>
<name>ENABLE</name>
<value>0x1</value>
</enum>
</field>
<field>
<name>ARM_SLOW_MODE</name>
<position>0</position>
<enum>
<name>DISABLE</name>
<value>0x0</value>
</enum>
<enum>
<name>ENABLE</name>
<value>0x1</value>
</enum>
</field>
</register>
</node>
<node>
<name>CLKCFG</name>
<instance>
<name>CLKCFG</name>
<address>0x18</address>
</instance>
<register>
<field>
<name>WDT_PCLK</name>
<position>31</position>
<enum>
<name>UNGATE</name>
<value>0x0</value>
</enum>
<enum>
<name>GATE</name>
<value>0x1</value>
</enum>
</field>
<field>
<name>RTC_PCLK</name>
<position>30</position>
<enum>
<name>UNGATE</name>
<value>0x0</value>
</enum>
<enum>
<name>GATE</name>
<value>0x1</value>
</enum>
</field>
<field>
<name>PWM_PCLK</name>
<position>29</position>
<enum>
<name>UNGATE</name>
<value>0x0</value>
</enum>
<enum>
<name>GATE</name>
<value>0x1</value>
</enum>
</field>
<field>
<name>TIMER_PCLK</name>
<position>28</position>
<enum>
<name>UNGATE</name>
<value>0x0</value>
</enum>
<enum>
<name>GATE</name>
<value>0x1</value>
</enum>
</field>
<field>
<name>GPIO_PCLK</name>
<position>27</position>
<enum>
<name>UNGATE</name>
<value>0x0</value>
</enum>
<enum>
<name>GATE</name>
<value>0x1</value>
</enum>
</field>
<field>
<name>HSADC_PCLK</name>
<position>26</position>
<enum>
<name>UNGATE</name>
<value>0x0</value>
</enum>
<enum>
<name>GATE</name>
<value>0x1</value>
</enum>
</field>
<field>
<name>HSADC_HCLK</name>
<position>25</position>
<enum>
<name>UNGATE</name>
<value>0x0</value>
</enum>
<enum>
<name>GATE</name>
<value>0x1</value>
</enum>
</field>
<field>
<name>LSADC_CLK</name>
<position>24</position>
<enum>
<name>UNGATE</name>
<value>0x0</value>
</enum>
<enum>
<name>GATE</name>
<value>0x1</value>
</enum>
</field>
<field>
<name>LSADC_PCLK</name>
<position>23</position>
<enum>
<name>UNGATE</name>
<value>0x0</value>
</enum>
<enum>
<name>GATE</name>
<value>0x1</value>
</enum>
</field>
<field>
<name>SD_CLK</name>
<position>22</position>
<enum>
<name>UNGATE</name>
<value>0x0</value>
</enum>
<enum>
<name>GATE</name>
<value>0x1</value>
</enum>
</field>
<field>
<name>SPI_CLK</name>
<position>21</position>
<enum>
<name>UNGATE</name>
<value>0x0</value>
</enum>
<enum>
<name>GATE</name>
<value>0x1</value>
</enum>
</field>
<field>
<name>I2C_CLK</name>
<position>20</position>
<enum>
<name>UNGATE</name>
<value>0x0</value>
</enum>
<enum>
<name>GATE</name>
<value>0x1</value>
</enum>
</field>
<field>
<name>UART1_CLK</name>
<position>19</position>
<enum>
<name>UNGATE</name>
<value>0x0</value>
</enum>
<enum>
<name>GATE</name>
<value>0x1</value>
</enum>
</field>
<field>
<name>UART0_CLK</name>
<position>18</position>
<enum>
<name>UNGATE</name>
<value>0x0</value>
</enum>
<enum>
<name>GATE</name>
<value>0x1</value>
</enum>
</field>
<field>
<name>I2S_PCLK</name>
<position>17</position>
<enum>
<name>UNGATE</name>
<value>0x0</value>
</enum>
<enum>
<name>GATE</name>
<value>0x1</value>
</enum>
</field>
<field>
<name>I2S_CLK</name>
<position>16</position>
<enum>
<name>UNGATE</name>
<value>0x0</value>
</enum>
<enum>
<name>GATE</name>
<value>0x1</value>
</enum>
</field>
<field>
<name>VIP_CLK</name>
<position>15</position>
<enum>
<name>UNGATE</name>
<value>0x0</value>
</enum>
<enum>
<name>GATE</name>
<value>0x1</value>
</enum>
</field>
<field>
<name>VIP_HCLK</name>
<position>14</position>
<enum>
<name>UNGATE</name>
<value>0x0</value>
</enum>
<enum>
<name>GATE</name>
<value>0x1</value>
</enum>
</field>
<field>
<name>LCDC_CLK</name>
<position>13</position>
<enum>
<name>UNGATE</name>
<value>0x0</value>
</enum>
<enum>
<name>GATE</name>
<value>0x1</value>
</enum>
</field>
<field>
<name>LCDC_HCLK</name>
<position>12</position>
<enum>
<name>UNGATE</name>
<value>0x0</value>
</enum>
<enum>
<name>GATE</name>
<value>0x1</value>
</enum>
</field>
<field>
<name>IRAM_HCLK</name>
<position>11</position>
<enum>
<name>UNGATE</name>
<value>0x0</value>
</enum>
<enum>
<name>GATE</name>
<value>0x1</value>
</enum>
</field>
<field>
<name>A2A_HCLK</name>
<position>10</position>
<enum>
<name>UNGATE</name>
<value>0x0</value>
</enum>
<enum>
<name>GATE</name>
<value>0x1</value>
</enum>
</field>
<field>
<name>NANDC_HCLK</name>
<position>9</position>
<enum>
<name>UNGATE</name>
<value>0x0</value>
</enum>
<enum>
<name>GATE</name>
<value>0x1</value>
</enum>
</field>
<field>
<name>UDC_CLK</name>
<position>6</position>
<enum>
<name>UNGATE</name>
<value>0x0</value>
</enum>
<enum>
<name>GATE</name>
<value>0x1</value>
</enum>
</field>
<field>
<name>UHC_CLK</name>
<position>5</position>
<enum>
<name>UNGATE</name>
<value>0x0</value>
</enum>
<enum>
<name>GATE</name>
<value>0x1</value>
</enum>
</field>
<field>
<name>DWDMA_CLK</name>
<position>4</position>
<enum>
<name>UNGATE</name>
<value>0x0</value>
</enum>
<enum>
<name>GATE</name>
<value>0x1</value>
</enum>
</field>
<field>
<name>HDMA_CLK</name>
<position>3</position>
<enum>
<name>UNGATE</name>
<value>0x0</value>
</enum>
<enum>
<name>GATE</name>
<value>0x1</value>
</enum>
</field>
<field>
<name>SDRAM_HCLK</name>
<position>2</position>
<enum>
<name>UNGATE</name>
<value>0x0</value>
</enum>
<enum>
<name>GATE</name>
<value>0x1</value>
</enum>
</field>
<field>
<name>DSP_CLK</name>
<position>1</position>
<enum>
<name>UNGATE</name>
<value>0x0</value>
</enum>
<enum>
<name>GATE</name>
<value>0x1</value>
</enum>
</field>
<field>
<name>OTP_CLK</name>
<position>0</position>
<enum>
<name>UNGATE</name>
<value>0x0</value>
</enum>
<enum>
<name>GATE</name>
<value>0x1</value>
</enum>
</field>
</register>
</node>
<node>
<name>RSTCFG</name>
<instance>
<name>RSTCFG</name>
<address>0x1c</address>
</instance>
<register>
<field>
<name>ARM_RST</name>
<position>12</position>
<enum>
<name>DEASSERT</name>
<value>0x0</value>
</enum>
<enum>
<name>ASSERT</name>
<value>0x1</value>
</enum>
</field>
<field>
<name>DUALCORE_ECT_RST</name>
<position>11</position>
<enum>
<name>DEASSERT</name>
<value>0x0</value>
</enum>
<enum>
<name>ASSERT</name>
<value>0x1</value>
</enum>
</field>
<field>
<name>DUALCORE_MAILBOX_RST</name>
<position>10</position>
<enum>
<name>DEASSERT</name>
<value>0x0</value>
</enum>
<enum>
<name>ASSERT</name>
<value>0x1</value>
</enum>
</field>
<field>
<name>SD_RST</name>
<position>9</position>
<enum>
<name>DEASSERT</name>
<value>0x0</value>
</enum>
<enum>
<name>ASSERT</name>
<value>0x1</value>
</enum>
</field>
<field>
<name>HSADC_RST</name>
<position>8</position>
<enum>
<name>DEASSERT</name>
<value>0x0</value>
</enum>
<enum>
<name>ASSERT</name>
<value>0x1</value>
</enum>
</field>
<field>
<name>LSADC_RST</name>
<position>7</position>
<enum>
<name>DEASSERT</name>
<value>0x0</value>
</enum>
<enum>
<name>ASSERT</name>
<value>0x1</value>
</enum>
</field>
<field>
<name>CODEC_RST</name>
<position>6</position>
<enum>
<name>DEASSERT</name>
<value>0x0</value>
</enum>
<enum>
<name>ASSERT</name>
<value>0x1</value>
</enum>
</field>
<field>
<name>DSP_PERIPHERAL_RST</name>
<position>5</position>
<enum>
<name>DEASSERT</name>
<value>0x0</value>
</enum>
<enum>
<name>ASSERT</name>
<value>0x1</value>
</enum>
</field>
<field>
<name>DSP_CORE_RST</name>
<position>4</position>
<enum>
<name>DEASSERT</name>
<value>0x0</value>
</enum>
<enum>
<name>ASSERT</name>
<value>0x1</value>
</enum>
</field>
<field>
<name>VIP_RST</name>
<position>3</position>
<enum>
<name>DEASSERT</name>
<value>0x0</value>
</enum>
<enum>
<name>ASSERT</name>
<value>0x1</value>
</enum>
</field>
<field>
<name>LCDC_RST</name>
<position>2</position>
<enum>
<name>DEASSERT</name>
<value>0x0</value>
</enum>
<enum>
<name>ASSERT</name>
<value>0x1</value>
</enum>
</field>
<field>
<name>UDC_RST</name>
<position>1</position>
<enum>
<name>DEASSERT</name>
<value>0x0</value>
</enum>
<enum>
<name>ASSERT</name>
<value>0x1</value>
</enum>
</field>
<field>
<name>UHC_RST</name>
<position>0</position>
<enum>
<name>DEASSERT</name>
<value>0x0</value>
</enum>
<enum>
<name>ASSERT</name>
<value>0x1</value>
</enum>
</field>
</register>
</node>
<node>
<name>PWM</name>
<instance>
<name>PWM</name>
<address>0x20</address>
</instance>
<register>
<field>
<name>PLL_LOCK_PERIOD</name>
<position>16</position>
<width>16</width>
</field>
<field>
<name>EXT_WAKEUP_PIN_POLARITY</name>
<position>6</position>
<enum>
<name>POSITIVE</name>
<value>0x0</value>
</enum>
<enum>
<name>NEGATIVE</name>
<value>0x1</value>
</enum>
</field>
<field>
<name>RTC_ALARM_WAKEUP</name>
<position>5</position>
<enum>
<name>ENABLE</name>
<value>0x0</value>
</enum>
<enum>
<name>DISABLE</name>
<value>0x1</value>
</enum>
</field>
<field>
<name>EXT_WAKEUP</name>
<position>4</position>
<enum>
<name>ENABLE</name>
<value>0x0</value>
</enum>
<enum>
<name>DISABLE</name>
<value>0x1</value>
</enum>
</field>
<field>
<name>SCU_IRQ_CLEAR</name>
<position>3</position>
<enum>
<name>PENDING</name>
<value>0x0</value>
</enum>
<enum>
<name>CLEAR</name>
<value>0x1</value>
</enum>
</field>
<field>
<name>POWERMANAGEMENT_MODE</name>
<position>0</position>
<width>3</width>
<enum>
<name>NORMAL</name>
<value>0x0</value>
</enum>
<enum>
<name>STOP</name>
<value>0x4</value>
</enum>
</field>
</register>
</node>
<node>
<name>CPUPD</name>
<instance>
<name>CPUPD</name>
<address>0x24</address>
</instance>
<register/>
</node>
<node>
<name>CHIPCFG</name>
<instance>
<name>CHIPCFG</name>
<address>0x28</address>
</instance>
<register>
<field>
<name>NOR_FLASH_BUSWIDTH</name>
<position>19</position>
<enum>
<name>16BIT</name>
<value>0x0</value>
</enum>
<enum>
<name>8BIT</name>
<value>0x1</value>
</enum>
</field>
<field>
<name>DSP2ARM_IRQ</name>
<position>17</position>
</field>
<field>
<name>ARM2DSP_IRQ</name>
<position>16</position>
</field>
<field>
<name>ARM_HIGHVECTOR</name>
<position>3</position>
</field>
<field>
<name>UHC_DATABUS_WIDTH</name>
<position>2</position>
<enum>
<name>8BIT</name>
<value>0x0</value>
</enum>
<enum>
<name>16BIT</name>
<value>0x1</value>
</enum>
</field>
<field>
<name>USB_PHY_MUX</name>
<position>1</position>
<enum>
<name>USB_PHY_UDC</name>
<value>0x0</value>
</enum>
<enum>
<name>USB_PHY_UHC</name>
<value>0x1</value>
</enum>
</field>
</register>
</node>
<node>
<name>STATUS</name>
<instance>
<name>STATUS</name>
<address>0x2c</address>
</instance>
<register>
<field>
<name>DSPSYSCLKVALID</name>
<position>4</position>
<enum>
<name>UNSTABLE</name>
<value>0x0</value>
</enum>
<enum>
<name>VALID</name>
<value>0x1</value>
</enum>
</field>
<field>
<name>ARMSYSCLKVALID</name>
<position>3</position>
<enum>
<name>UNSTABLE</name>
<value>0x0</value>
</enum>
<enum>
<name>VALID</name>
<value>0x1</value>
</enum>
</field>
<field>
<name>CODEC_PLL_LOCKED</name>
<position>2</position>
<enum>
<name>UNSTABLE</name>
<value>0x0</value>
</enum>
<enum>
<name>LOCKED</name>
<value>0x1</value>
</enum>
</field>
<field>
<name>DSP_PLL_LOCKED</name>
<position>1</position>
<enum>
<name>UNSTABLE</name>
<value>0x0</value>
</enum>
<enum>
<name>LOCKED</name>
<value>0x1</value>
</enum>
</field>
<field>
<name>ARM_PLL_LOCKED</name>
<position>0</position>
<enum>
<name>UNSTABLE</name>
<value>0x0</value>
</enum>
<enum>
<name>LOCKED</name>
<value>0x1</value>
</enum>
</field>
</register>
</node>
<node>
<name>IOMUXA_CON</name>
<instance>
<name>IOMUXA_CON</name>
<address>0x30</address>
</instance>
<register>
<field>
<name>I2S_CODEC_EXT_SEL</name>
<position>19</position>
<enum>
<name>INTERNAL_CODEC</name>
<value>0x0</value>
</enum>
<enum>
<name>PIN</name>
<value>0x1</value>
</enum>
</field>
<field>
<name>I2C_CODEC_EXT_SEL</name>
<position>18</position>
<enum>
<name>INTERNAL_CODEC</name>
<value>0x0</value>
</enum>
<enum>
<name>PIN</name>
<value>0x1</value>
</enum>
</field>
<field>
<name>I2C_FLASHCS3_GPIOB_SEL</name>
<position>16</position>
<width>2</width>
<enum>
<name>I2C_SDA</name>
<value>0x0</value>
</enum>
<enum>
<name>FLASH_CS3</name>
<value>0x1</value>
</enum>
<enum>
<name>GPIOB7</name>
<value>0x2</value>
</enum>
</field>
<field>
<name>I2C_FLASHCS2_GPIOB_SEL</name>
<position>14</position>
<width>2</width>
<enum>
<name>I2C_SCL</name>
<value>0x0</value>
</enum>
<enum>
<name>FLASH_CS2</name>
<value>0x1</value>
</enum>
<enum>
<name>GPIOB6</name>
<value>0x2</value>
</enum>
</field>
<field>
<name>GPIOB_SD_SPI_SEL</name>
<position>12</position>
<width>2</width>
<enum>
<name>GPIOB_0_5</name>
<value>0x0</value>
</enum>
<enum>
<name>SD</name>
<value>0x1</value>
</enum>
<enum>
<name>SPI</name>
<value>0x2</value>
</enum>
</field>
<field>
<name>GPIO_LCDVSYN_SEL</name>
<position>11</position>
<enum>
<name>GPIOA7</name>
<value>0x0</value>
</enum>
<enum>
<name>LCD_VSYN</name>
<value>0x1</value>
</enum>
</field>
<field>
<name>GPIO_LCDEN_SEL</name>
<position>10</position>
<enum>
<name>GPIOA6</name>
<value>0x0</value>
</enum>
<enum>
<name>LCD_DATA_ENABLE</name>
<value>0x1</value>
</enum>
</field>
<field>
<name>GPIO_FLASHCS1_SEL</name>
<position>9</position>
<enum>
<name>GPIOA5</name>
<value>0x0</value>
</enum>
<enum>
<name>FLASH_CS1</name>
<value>0x1</value>
</enum>
</field>
<field>
<name>GPIO_LCD22_SEL</name>
<position>8</position>
<enum>
<name>GPIOA4</name>
<value>0x0</value>
</enum>
<enum>
<name>LCD_DATA22</name>
<value>0x1</value>
</enum>
</field>
<field>
<name>GPIOA_LCD20_NRTS0_SEL</name>
<position>6</position>
<width>2</width>
<enum>
<name>GPIOA3</name>
<value>0x0</value>
</enum>
<enum>
<name>LCD_DATA20</name>
<value>0x1</value>
</enum>
<enum>
<name>UART0_NRTS</name>
<value>0x2</value>
</enum>
</field>
<field>
<name>GPIOA_LCD18_NCTS0_SEL</name>
<position>4</position>
<width>2</width>
<enum>
<name>GPIOA2</name>
<value>0x0</value>
</enum>
<enum>
<name>LCD_DATA18</name>
<value>0x1</value>
</enum>
<enum>
<name>UART0_NCTS</name>
<value>0x2</value>
</enum>
</field>
<field>
<name>GPIOA_LCD17_TXD0_SEL</name>
<position>2</position>
<width>2</width>
<enum>
<name>GPIOA1</name>
<value>0x0</value>
</enum>
<enum>
<name>LCD_DATA17</name>
<value>0x1</value>
</enum>
<enum>
<name>UART0_TXD</name>
<value>0x2</value>
</enum>
</field>
<field>
<name>GPIOA_LCD16_RXD0_SEL</name>
<position>0</position>
<width>2</width>
<enum>
<name>GPIOA0</name>
<value>0x0</value>
</enum>
<enum>
<name>LCD_DATA16</name>
<value>0x1</value>
</enum>
<enum>
<name>UART0_RXD</name>
<value>0x2</value>
</enum>
</field>
</register>
</node>
<node>
<name>IOMUXB_CON</name>
<instance>
<name>IOMUXB_CON</name>
<address>0x34</address>
</instance>
<register>
<field>
<name>VIP_HSADC_SEL</name>
<position>22</position>
<enum>
<name>VIP</name>
<value>0x0</value>
</enum>
<enum>
<name>HSADC</name>
<value>0x1</value>
</enum>
</field>
<field>
<name>GPIOD_SDCKE_SEL</name>
<position>21</position>
<enum>
<name>GPIOD3</name>
<value>0x0</value>
</enum>
<enum>
<name>SDRAM_CKE</name>
<value>0x1</value>
</enum>
</field>
<field>
<name>GPIOF_UHCVBUS_SEL</name>
<position>20</position>
<enum>
<name>GPIOF4</name>
<value>0x0</value>
</enum>
<enum>
<name>UHC_VBUS</name>
<value>0x1</value>
</enum>
</field>
<field>
<name>GPIOF_UHCOCUR_SEL</name>
<position>19</position>
<enum>
<name>GPIOF3</name>
<value>0x0</value>
</enum>
<enum>
<name>UHC_OCUR</name>
<value>0x1</value>
</enum>
</field>
<field>
<name>SDTADDR12_GPIOF_SEL</name>
<position>18</position>
<enum>
<name>SDT_ADDR12</name>
<value>0x0</value>
</enum>
<enum>
<name>GPIOF2</name>
<value>0x1</value>
</enum>
</field>
<field>
<name>SDTADDR11_GPIOF_SEL</name>
<position>17</position>
<enum>
<name>SDT_ADDR11</name>
<value>0x0</value>
</enum>
<enum>
<name>GPIOF1</name>
<value>0x1</value>
</enum>
</field>
<field>
<name>GPIOF_VIPCLK_SEL</name>
<position>16</position>
<enum>
<name>GPIOF0</name>
<value>0x0</value>
</enum>
<enum>
<name>VIP_CLK</name>
<value>0x1</value>
</enum>
</field>
<field>
<name>GPIOE_LCD_SEL</name>
<position>15</position>
<enum>
<name>GPIOE_0_7</name>
<value>0x0</value>
</enum>
<enum>
<name>LCD_DATA_8_15</name>
<value>0x1</value>
</enum>
</field>
<field>
<name>GPIOD_PWM3_SEL</name>
<position>14</position>
<enum>
<name>GPIOD7</name>
<value>0x0</value>
</enum>
<enum>
<name>PWM3</name>
<value>0x1</value>
</enum>
</field>
<field>
<name>GPIOD_PWM2_SEL</name>
<position>13</position>
<enum>
<name>GPIOD6</name>
<value>0x0</value>
</enum>
<enum>
<name>PWM2</name>
<value>0x1</value>
</enum>
</field>
<field>
<name>GPIOD_PWM1_SEL</name>
<position>12</position>
<enum>
<name>GPIOD5</name>
<value>0x0</value>
</enum>
<enum>
<name>PWM1</name>
<value>0x1</value>
</enum>
</field>
<field>
<name>GPIOD_PWM0_SEL</name>
<position>11</position>
<enum>
<name>GPIOD4</name>
<value>0x0</value>
</enum>
<enum>
<name>PWM0</name>
<value>0x1</value>
</enum>
</field>
<field>
<name>GPIOD_SDWPA_SEL</name>
<position>10</position>
<enum>
<name>GPIOD2</name>
<value>0x0</value>
</enum>
<enum>
<name>SD_WPA</name>
<value>0x1</value>
</enum>
</field>
<field>
<name>GPIOD_SDCDA_RXD1_SEL</name>
<position>8</position>
<width>2</width>
<enum>
<name>GPIOD1</name>
<value>0x0</value>
</enum>
<enum>
<name>SD_CDA</name>
<value>0x1</value>
</enum>
<enum>
<name>UART1_RXD</name>
<value>0x2</value>
</enum>
</field>
<field>
<name>GPIOD_SDPCA_TXD1_SEL</name>
<position>6</position>
<width>2</width>
<enum>
<name>GPIOD0</name>
<value>0x0</value>
</enum>
<enum>
<name>SD_PCA</name>
<value>0x1</value>
</enum>
<enum>
<name>UART1_RXD</name>
<value>0x2</value>
</enum>
</field>
<field>
<name>GPIOC_STCS1_SEL</name>
<position>5</position>
<enum>
<name>GPIOC7</name>
<value>0x0</value>
</enum>
<enum>
<name>ST_CS1</name>
<value>0x1</value>
</enum>
</field>
<field>
<name>GPIOC_I2SCLK1_SEL</name>
<position>4</position>
<enum>
<name>GPIOC6</name>
<value>0x0</value>
</enum>
<enum>
<name>I2S_CLK</name>
<value>0x1</value>
</enum>
</field>
<field>
<name>GPIOC_I2SSDO_SEL</name>
<position>3</position>
<enum>
<name>GPIOC5</name>
<value>0x0</value>
</enum>
<enum>
<name>I2S_SDO</name>
<value>0x1</value>
</enum>
</field>
<field>
<name>GPIOC_I2SSDI_SEL</name>
<position>2</position>
<enum>
<name>GPIOC4</name>
<value>0x0</value>
</enum>
<enum>
<name>I2S_SDI</name>
<value>0x1</value>
</enum>
</field>
<field>
<name>GPIOC_I2SLRCK_SEL</name>
<position>1</position>
<enum>
<name>GPIOC3</name>
<value>0x0</value>
</enum>
<enum>
<name>I2S_LRCK</name>
<value>0x1</value>
</enum>
</field>
<field>
<name>GPIOC_I2SSCLK_SEL</name>
<position>0</position>
<enum>
<name>GPIOC2</name>
<value>0x0</value>
</enum>
<enum>
<name>I2S_SCLK</name>
<value>0x1</value>
</enum>
</field>
</register>
</node>
<node>
<name>SCU_GPIOUPCON</name>
<instance>
<name>SCU_GPIOUPCON</name>
<address>0x38</address>
</instance>
<register/>
</node>
<node>
<name>SCU_DIVCON2</name>
<instance>
<name>SCU_DIVCON2</name>
<address>0x3c</address>
</instance>
<register/>
</node>
</node>
<node>
<name>I2C</name>
<title>I2C controller</title>
<desc>I2C controller</desc>
<instance>
<name>I2C</name>
<address>0x18020000</address>
</instance>
<node>
<name>MTXR</name>
<instance>
<name>MTXR</name>
<address>0x0</address>
</instance>
<register/>
</node>
<node>
<name>MRXR</name>
<instance>
<name>MRXR</name>
<address>0x4</address>
</instance>
<register/>
</node>
<node>
<name>STXR</name>
<instance>
<name>STXR</name>
<address>0x8</address>
</instance>
<register/>
</node>
<node>
<name>SRXR</name>
<instance>
<name>SRXR</name>
<address>0xc</address>
</instance>
<register/>
</node>
<node>
<name>SADDR</name>
<instance>
<name>SADDR</name>
<address>0x10</address>
</instance>
<register/>
</node>
<node>
<name>IER</name>
<instance>
<name>IER</name>
<address>0x14</address>
</instance>
<register/>
</node>
<node>
<name>ISR</name>
<instance>
<name>ISR</name>
<address>0x18</address>
</instance>
<register/>
</node>
<node>
<name>LCMR</name>
<instance>
<name>LCMR</name>
<address>0x1c</address>
</instance>
<register/>
</node>
<node>
<name>LSR</name>
<instance>
<name>LSR</name>
<address>0x20</address>
</instance>
<register/>
</node>
<node>
<name>CONR</name>
<instance>
<name>CONR</name>
<address>0x24</address>
</instance>
<register/>
</node>
<node>
<name>OPR</name>
<instance>
<name>OPR</name>
<address>0x28</address>
</instance>
<register/>
</node>
</node>
<node>
<name>SD</name>
<title>SD controller</title>
<desc>SD controller</desc>
<instance>
<name>SD</name>
<address>0x18024000</address>
</instance>
<node>
<name>MMU_CTRL</name>
<instance>
<name>MMU_CTRL</name>
<address>0x0</address>
</instance>
<register>
<field>
<name>RESERVED31_13</name>
<position>13</position>
<width>19</width>
</field>
<field>
<name>ENDIANEESE</name>
<desc>Endian control when CPU access to data buffer.</desc>
<position>12</position>
<enum>
<name>LITTLE_ENDIAN</name>
<value>0x0</value>
</enum>
<enum>
<name>BIG_ENDIAN</name>
<value>0x1</value>
</enum>
</field>
<field>
<name>MMU_DMA_XFER</name>
<position>11</position>
</field>
<field>
<name>MMU_DMA_DIR</name>
<position>10</position>
<enum>
<name>READ</name>
<value>0x0</value>
</enum>
<enum>
<name>WRITE</name>
<value>0x1</value>
</enum>
</field>
<field>
<name>MMU_BUF_PTR</name>
<position>9</position>
<enum>
<name>BUF1</name>
<value>0x0</value>
</enum>
<enum>
<name>BUF2</name>
<value>0x1</value>
</enum>
</field>
<field>
<name>CPU_BUF_PTR</name>
<position>8</position>
<enum>
<name>BUF1</name>
<value>0x0</value>
</enum>
<enum>
<name>BUF2</name>
<value>0x1</value>
</enum>
</field>
<field>
<name>BUF2_RST</name>
<position>7</position>
</field>
<field>
<name>BUF2_END_SIGNAL</name>
<position>6</position>
</field>
<field>
<name>BUF2_XFER_WIDTH</name>
<position>4</position>
<width>2</width>
<enum>
<name>BYTE</name>
<value>0x0</value>
</enum>
<enum>
<name>HALFWORD</name>
<value>0x1</value>
</enum>
<enum>
<name>RESERVED</name>
<value>0x2</value>
</enum>
<enum>
<name>WORD</name>
<value>0x3</value>
</enum>
</field>
<field>
<name>BUF1_RST</name>
<position>3</position>
</field>
<field>
<name>BUF1_END_SIGNAL</name>
<position>2</position>
</field>
<field>
<name>BUF1_XFER_WIDTH</name>
<position>0</position>
<width>2</width>
<enum>
<name>BYTE</name>
<value>0x0</value>
</enum>
<enum>
<name>HALFWORD</name>
<value>0x1</value>
</enum>
<enum>
<name>RESERVED</name>
<value>0x2</value>
</enum>
<enum>
<name>WORD</name>
<value>0x3</value>
</enum>
</field>
</register>
</node>
<node>
<name>MMU_PNRI</name>
<instance>
<name>MMU_PNRI</name>
<address>0x4</address>
</instance>
<register>
<field>
<name>RESERVED31_11</name>
<position>11</position>
<width>21</width>
</field>
<field>
<name>BUF1_PTR</name>
<position>0</position>
<width>11</width>
</field>
</register>
</node>
<node>
<name>CUR_PNRI</name>
<instance>
<name>CUR_PNRI</name>
<address>0x8</address>
</instance>
<register>
<field>
<name>RESERVED31_11</name>
<position>11</position>
<width>21</width>
</field>
<field>
<name>BUF1_PTR</name>
<position>0</position>
<width>11</width>
</field>
</register>
</node>
<node>
<name>MMU_PNRII</name>
<instance>
<name>MMU_PNRII</name>
<address>0xc</address>
</instance>
<register>
<field>
<name>RESERVED31_11</name>
<position>11</position>
<width>21</width>
</field>
<field>
<name>BUF2_PTR</name>
<position>0</position>
<width>11</width>
</field>
</register>
</node>
<node>
<name>CUR_PNRII</name>
<instance>
<name>CUR_PNRII</name>
<address>0x10</address>
</instance>
<register>
<field>
<name>RESERVED31_11</name>
<position>11</position>
<width>21</width>
</field>
<field>
<name>BUF2_PTR</name>
<position>0</position>
<width>11</width>
</field>
</register>
</node>
<node>
<name>MMU_ADDR</name>
<instance>
<name>MMU_ADDR</name>
<address>0x14</address>
</instance>
<register>
<field>
<name>RESERVED31_24</name>
<position>24</position>
<width>8</width>
</field>
<field>
<name>ADDR</name>
<position>0</position>
<width>24</width>
</field>
</register>
</node>
<node>
<name>CUR_ADDR</name>
<instance>
<name>CUR_ADDR</name>
<address>0x18</address>
</instance>
<register>
<field>
<name>RESERVED31_24</name>
<position>24</position>
<width>8</width>
</field>
<field>
<name>ADDR</name>
<position>0</position>
<width>24</width>
</field>
</register>
</node>
<node>
<name>MMU_DATA</name>
<instance>
<name>MMU_DATA</name>
<address>0x1c</address>
</instance>
<register/>
</node>
<node>
<name>CTRL</name>
<instance>
<name>CTRL</name>
<address>0x20</address>
</instance>
<register>
<field>
<name>RESERVED31_14</name>
<position>14</position>
<width>18</width>
</field>
<field>
<name>PWR_CTRL</name>
<desc>Power control type for SD/MMC cards</desc>
<position>13</position>
<enum>
<name>CPU</name>
<desc>The SD/MMC card power is controlled by CPU
</desc>
<value>0x0</value>
</enum>
<enum>
<name>CD</name>
<desc>The SD/MMC card power is controlled by CD/DAT3</desc>
<value>0x1</value>
</enum>
</field>
<field>
<name>DETECT_CTRL</name>
<desc>Card detect type for SD cards</desc>
<position>12</position>
<enum>
<name>SWITCH</name>
<desc>The card detect function is used by mechanism</desc>
<value>0x0</value>
</enum>
<enum>
<name>CD</name>
<desc>The card detect function is used by CD/DAT3</desc>
<value>0x1</value>
</enum>
</field>
<field>
<name>STOP</name>
<position>11</position>
<enum>
<name>SD_CLK_EN</name>
<desc>Run the SD/MMC Card clock</desc>
<value>0x0</value>
</enum>
<enum>
<name>SD_CLK_DIS</name>
<desc>Stop the SD/MMC Card clock</desc>
<value>0x1</value>
</enum>
</field>
<field>
<name>DIVIDER</name>
<position>0</position>
<width>11</width>
</field>
</register>
</node>
<node>
<name>INT</name>
<instance>
<name>INT</name>
<address>0x24</address>
</instance>
<register>
<field>
<name>RESERVED31_7</name>
<position>7</position>
<width>25</width>
</field>
<field>
<name>CMD_RSP_STS</name>
<desc>Command and response transfer interrupt status</desc>
<position>6</position>
<enum>
<name>NO</name>
<value>0x0</value>
</enum>
<enum>
<name>YES</name>
<value>0x1</value>
</enum>
</field>
<field>
<name>DATA_STS</name>
<desc>Data transfer interrupt status</desc>
<position>5</position>
<enum>
<name>NO</name>
<value>0x0</value>
</enum>
<enum>
<name>YES</name>
<value>0x1</value>
</enum>
</field>
<field>
<name>CARD_DETECT_STS</name>
<desc>Card detect interrupt status</desc>
<position>4</position>
<enum>
<name>NO</name>
<value>0x0</value>
</enum>
<enum>
<name>YES</name>
<value>0x1</value>
</enum>
</field>
<field>
<name>RESERVED3</name>
<position>3</position>
</field>
<field>
<name>CMD_RSP_INT_EN</name>
<desc>Command and response transfer interrupt enable</desc>
<position>2</position>
<enum>
<name>DISABLE</name>
<value>0x0</value>
</enum>
<enum>
<name>ENABLE</name>
<value>0x1</value>
</enum>
</field>
<field>
<name>DATA_INT_EN</name>
<desc>Data transfer interrupt enable</desc>
<position>1</position>
<enum>
<name>DISABLE</name>
<value>0x0</value>
</enum>
<enum>
<name>ENABLE</name>
<value>0x1</value>
</enum>
</field>
<field>
<name>CARD_DETECT_INT_EN</name>
<desc>Card detect interrupt enable</desc>
<position>0</position>
<enum>
<name>DISABLE</name>
<value>0x0</value>
</enum>
<enum>
<name>ENABLE</name>
<value>0x1</value>
</enum>
</field>
</register>
</node>
<node>
<name>CARD</name>
<instance>
<name>CARD</name>
<address>0x28</address>
</instance>
<register>
<field>
<name>RESERVED31_7</name>
<position>7</position>
<width>25</width>
</field>
<field>
<name>SELECT</name>
<position>6</position>
<enum>
<name>NO</name>
<value>0x0</value>
</enum>
<enum>
<name>YES</name>
<value>0x1</value>
</enum>
</field>
<field>
<name>PWR_CTRL</name>
<position>5</position>
<enum>
<name>NO</name>
<value>0x0</value>
</enum>
<enum>
<name>YES</name>
<value>0x1</value>
</enum>
</field>
<field>
<name>DETECT_INT_EN</name>
<position>4</position>
<enum>
<name>NO</name>
<value>0x0</value>
</enum>
<enum>
<name>YES</name>
<value>0x1</value>
</enum>
</field>
<field>
<name>RESERVED3</name>
<position>3</position>
</field>
<field>
<name>BUSY</name>
<position>2</position>
</field>
<field>
<name>WR_PROTECT</name>
<position>1</position>
</field>
<field>
<name>CARD_DETECT</name>
<position>0</position>
</field>
</register>
</node>
<node>
<name>CMDREST</name>
<instance>
<name>CMDREST</name>
<address>0x30</address>
</instance>
<register>
<desc>SD/MMC command and response transfer register</desc>
<field>
<name>RESERVED31_14</name>
<position>14</position>
<width>18</width>
</field>
<field>
<name>CMD_XFER</name>
<desc>Command transfer signal</desc>
<position>13</position>
<enum>
<name>END</name>
<value>0x0</value>
</enum>
<enum>
<name>BEGIN</name>
<value>0x1</value>
</enum>
</field>
<field>
<name>RSP_XFER</name>
<desc>Response transfer signal</desc>
<position>12</position>
<enum>
<name>END</name>
<value>0x0</value>
</enum>
<enum>
<name>BEGIN</name>
<value>0x1</value>
</enum>
</field>
<field>
<name>RSP_TYPE</name>
<desc>Response transfer type</desc>
<position>9</position>
<width>3</width>
<enum>
<name>R1</name>
<value>0x0</value>
</enum>
<enum>
<name>R1b</name>
<value>0x1</value>
</enum>
<enum>
<name>R2</name>
<value>0x2</value>
</enum>
<enum>
<name>R3</name>
<value>0x3</value>
</enum>
<enum>
<name>R6</name>
<value>0x6</value>
</enum>
</field>
<field>
<name>CMD_RSP_ERR_STS</name>
<position>8</position>
<enum>
<name>NO_ERROR</name>
<value>0x0</value>
</enum>
<enum>
<name>ERROR</name>
<value>0x1</value>
</enum>
</field>
<field>
<name>RESERVED7_6</name>
<position>6</position>
<width>2</width>
</field>
<field>
<name>CMD_INDEX</name>
<position>0</position>
<width>6</width>
</field>
</register>
</node>
<node>
<name>CMDRES</name>
<instance>
<name>CMDRES</name>
<address>0x34</address>
</instance>
<register>
<desc>SD/MMC command and response transfer status register</desc>
<field>
<name>RESERVED31_9</name>
<position>9</position>
<width>23</width>
</field>
<field>
<name>CMD_XFER</name>
<position>8</position>
<enum>
<name>END</name>
<value>0x0</value>
</enum>
<enum>
<name>BEGIN</name>
<value>0x1</value>
</enum>
</field>
<field>
<name>RSP_XFER</name>
<position>7</position>
<enum>
<name>END</name>
<value>0x0</value>
</enum>
<enum>
<name>BEGIN</name>
<value>0x1</value>
</enum>
</field>
<field>
<name>CMD_RSP_ERR</name>
<desc>Card command and response error status</desc>
<position>6</position>
<enum>
<name>NO_ERROR</name>
<value>0x0</value>
</enum>
<enum>
<name>ERROR</name>
<value>0x1</value>
</enum>
</field>
<field>
<name>CMD_RSP_BUS_ERR</name>
<desc>Card command and response bus conflict error</desc>
<position>5</position>
<enum>
<name>NO_ERROR</name>
<value>0x0</value>
</enum>
<enum>
<name>ERROR</name>
<value>0x1</value>
</enum>
</field>
<field>
<name>RSP_TIMEOUT_ERR</name>
<position>4</position>
<enum>
<name>NO_ERROR</name>
<value>0x0</value>
</enum>
<enum>
<name>ERROR</name>
<value>0x1</value>
</enum>
</field>
<field>
<name>RSP_BIT_ERR</name>
<position>3</position>
<enum>
<name>NO_ERROR</name>
<value>0x0</value>
</enum>
<enum>
<name>ERROR</name>
<value>0x1</value>
</enum>
</field>
<field>
<name>RSP_INDEX_ERR</name>
<position>2</position>
<enum>
<name>NO_ERROR</name>
<value>0x0</value>
</enum>
<enum>
<name>ERROR</name>
<value>0x1</value>
</enum>
</field>
<field>
<name>RSP_CRC_ERR</name>
<position>1</position>
<enum>
<name>NO_ERROR</name>
<value>0x0</value>
</enum>
<enum>
<name>ERROR</name>
<value>0x1</value>
</enum>
</field>
<field>
<name>RSP_END_BIT_ERR</name>
<position>0</position>
<enum>
<name>NO_ERROR</name>
<value>0x0</value>
</enum>
<enum>
<name>ERROR</name>
<value>0x1</value>
</enum>
</field>
</register>
</node>
<node>
<name>DATAT</name>
<instance>
<name>DATAT</name>
<address>0x3c</address>
</instance>
<register>
<desc>SD/MMC data transfer register
</desc>
<field>
<name>RESERVED_31_14</name>
<position>14</position>
<width>18</width>
</field>
<field>
<name>DATA_XFER</name>
<position>13</position>
<enum>
<name>END</name>
<value>0x0</value>
</enum>
<enum>
<name>BEGIN</name>
<value>0x1</value>
</enum>
</field>
<field>
<name>DATA_XFER_DIR</name>
<position>12</position>
<enum>
<name>READ</name>
<value>0x0</value>
</enum>
<enum>
<name>WRITE</name>
<value>0x1</value>
</enum>
</field>
<field>
<name>DATA_BUS_WIDTH</name>
<position>11</position>
<enum>
<name>1BIT</name>
<value>0x0</value>
</enum>
<enum>
<name>4BITS</name>
<value>0x1</value>
</enum>
</field>
<field>
<name>DMA_EN</name>
<position>10</position>
<enum>
<name>DISABLE</name>
<value>0x0</value>
</enum>
<enum>
<name>ENABLE</name>
<value>0x1</value>
</enum>
</field>
<field>
<name>DATA_XFER_CYCLE</name>
<position>9</position>
<enum>
<name>SINGLE_LAST</name>
<value>0x0</value>
</enum>
<enum>
<name>MULTIPLE</name>
<value>0x1</value>
</enum>
</field>
<field>
<name>DATA_XFER_ERR</name>
<position>8</position>
<enum>
<name>NO_ERROR</name>
<value>0x0</value>
</enum>
<enum>
<name>ERROR</name>
<value>0x1</value>
</enum>
</field>
<field>
<name>DATA_XFER_TIMEOUT</name>
<position>6</position>
<enum>
<name>NO_ERROR</name>
<value>0x0</value>
</enum>
<enum>
<name>ERROR</name>
<value>0x1</value>
</enum>
</field>
<field>
<name>DATA_XFER_CRC_ERR</name>
<position>5</position>
<enum>
<name>NO_ERROR</name>
<value>0x0</value>
</enum>
<enum>
<name>ERROR</name>
<value>0x1</value>
</enum>
</field>
<field>
<name>RX_DATA_START_BIT_ERR</name>
<position>4</position>
<enum>
<name>NO_ERROR</name>
<value>0x0</value>
</enum>
<enum>
<name>ERROR</name>
<value>0x1</value>
</enum>
</field>
<field>
<name>RX_DATA_END_BIT_ERR</name>
<position>3</position>
<enum>
<name>NO_ERROR</name>
<value>0x0</value>
</enum>
<enum>
<name>ERROR</name>
<value>0x1</value>
</enum>
</field>
<field>
<name>DATA_XFER_CRC_STS</name>
<position>0</position>
<width>3</width>
<enum>
<name>NO_ERROR</name>
<value>0x2</value>
</enum>
<enum>
<name>CRC_ERROR</name>
<value>0x5</value>
</enum>
<enum>
<name>NO_RSP</name>
<value>0x7</value>
</enum>
</field>
</register>
</node>
<node>
<name>CMD</name>
<instance>
<name>CMD</name>
<address>0x40</address>
</instance>
<register/>
</node>
<node>
<name>RES3</name>
<instance>
<name>RES3</name>
<address>0x44</address>
</instance>
<register/>
</node>
<node>
<name>RES2</name>
<instance>
<name>RES2</name>
<address>0x48</address>
</instance>
<register/>
</node>
<node>
<name>RES1</name>
<instance>
<name>RES1</name>
<address>0x4c</address>
</instance>
<register/>
</node>
<node>
<name>RES0</name>
<instance>
<name>RES0</name>
<address>0x50</address>
</instance>
<register/>
</node>
</node>
<node>
<name>I2S</name>
<title>I2S controller</title>
<desc>I2S controller</desc>
<instance>
<name>I2S</name>
<address>0x18028000</address>
</instance>
<node>
<name>OPR</name>
<instance>
<name>OPR</name>
<address>0x0</address>
</instance>
<register>
<field>
<name>I2S_VERSION</name>
<position>24</position>
<width>8</width>
</field>
<field>
<name>RESERVED23_18</name>
<position>18</position>
<width>6</width>
</field>
<field>
<name>TX_RESET</name>
<position>17</position>
</field>
<field>
<name>RX_RESET</name>
<position>16</position>
</field>
<field>
<name>RESERVED15_7</name>
<position>7</position>
<width>9</width>
</field>
<field>
<name>HDMA_REQ1_DIS</name>
<position>6</position>
<enum>
<name>ENABLE</name>
<value>0x0</value>
</enum>
<enum>
<name>DISABLE</name>
<desc>HDMA REQ1 Always 1
</desc>
<value>0x1</value>
</enum>
</field>
<field>
<name>HDMA_REQ2_DIS</name>
<position>5</position>
<enum>
<name>ENABLE</name>
<value>0x0</value>
</enum>
<enum>
<name>DISABLE</name>
<desc>HDMA REQ2 Always 1</desc>
<value>0x1</value>
</enum>
</field>
<field>
<name>HDMA_REQ1_CH</name>
<desc>This bit is to indicate the Hardware DMA IF1 is used for which FIFO
</desc>
<position>4</position>
<enum>
<name>TX_FIFO</name>
<value>0x0</value>
</enum>
<enum>
<name>RX_FIFO</name>
<value>0x1</value>
</enum>
</field>
<field>
<name>HDMA_REQ2_CH</name>
<desc>his bit is to indicate the Hardware DMA IF2 is used for which FIFO</desc>
<position>3</position>
<enum>
<name>TX_FIFO</name>
<value>0x0</value>
</enum>
<enum>
<name>RX_FIFO</name>
<value>0x1</value>
</enum>
</field>
<field>
<name>I2S_LOOPBACK</name>
<position>2</position>
<enum>
<name>NORMAL</name>
<value>0x0</value>
</enum>
<enum>
<name>LOOPBACK</name>
<value>0x1</value>
</enum>
</field>
<field>
<name>I2S_TX_START</name>
<position>1</position>
</field>
<field>
<name>I2S_RX_START</name>
<position>0</position>
</field>
</register>
</node>
<node>
<name>TXR</name>
<instance>
<name>TXR</name>
<address>0x4</address>
</instance>
<register>
<desc>I2S transmit FIFO</desc>
</register>
</node>
<node>
<name>RXR</name>
<instance>
<name>RXR</name>
<address>0x8</address>
</instance>
<register>
<desc>I2S receive FIFO</desc>
</register>
</node>
<node>
<name>TXCTL</name>
<instance>
<name>TXCTL</name>
<address>0xc</address>
</instance>
<register>
<field>
<name>RESERVED31_18</name>
<position>18</position>
<width>14</width>
</field>
<field>
<name>OVERSAMPLING</name>
<desc>Oversampling rate = LRCK / SCLK</desc>
<position>16</position>
<width>2</width>
<enum>
<name>32FS</name>
<value>0x0</value>
</enum>
<enum>
<name>64FS</name>
<value>0x1</value>
</enum>
<enum>
<name>128FS</name>
<value>0x2</value>
</enum>
<enum>
<name>RESERVED</name>
<value>0x3</value>
</enum>
</field>
<field>
<name>MCLK_DIV</name>
<position>8</position>
<width>8</width>
</field>
<field>
<name>RESERVED7_6</name>
<position>6</position>
<width>2</width>
</field>
<field>
<name>SAMPLE_WIDTH</name>
<position>4</position>
<width>2</width>
<enum>
<name>8BITS</name>
<value>0x0</value>
</enum>
<enum>
<name>16BITS</name>
<value>0x1</value>
</enum>
</field>
<field>
<name>MONO_STEREO</name>
<desc>When the bit is set to 1, transmitter is at Mono mode and data output from left channel.
</desc>
<position>3</position>
<enum>
<name>STEREO</name>
<value>0x0</value>
</enum>
<enum>
<name>MONO</name>
<value>0x1</value>
</enum>
</field>
<field>
<name>IF_MODE</name>
<position>1</position>
<width>2</width>
<enum>
<name>I2S</name>
<value>0x0</value>
</enum>
<enum>
<name>LEFT_JUSTIFIED</name>
<value>0x1</value>
</enum>
<enum>
<name>RIGHT_JUSTIFIED</name>
<value>0x2</value>
</enum>
</field>
<field>
<name>MASTER_SLAVE</name>
<desc>This bit decides that transmitter acts as a master or slave.
</desc>
<position>0</position>
<enum>
<name>SLAVE</name>
<value>0x0</value>
</enum>
<enum>
<name>MASTER</name>
<value>0x1</value>
</enum>
</field>
</register>
</node>
<node>
<name>RXCTL</name>
<instance>
<name>RXCTL</name>
<address>0x10</address>
</instance>
<register>
<field>
<name>RESERVED31_25</name>
<position>25</position>
<width>7</width>
</field>
<field>
<name>RX_FIFO_RESET</name>
<position>24</position>
</field>
<field>
<name>RESERVED23_18</name>
<position>18</position>
<width>6</width>
</field>
<field>
<name>OVERSAMPLING</name>
<desc>Oversampling rate = LRCK / SCLK</desc>
<position>16</position>
<width>2</width>
<enum>
<name>32fs</name>
<value>0x0</value>
</enum>
<enum>
<name>64fs</name>
<value>0x1</value>
</enum>
<enum>
<name>128fs</name>
<value>0x2</value>
</enum>
</field>
<field>
<name>MCLK_DIV</name>
<position>8</position>
<width>8</width>
</field>
<field>
<name>RESERVED7_6</name>
<position>6</position>
<width>2</width>
</field>
<field>
<name>SAMPLE_WIDTH</name>
<position>4</position>
<width>2</width>
<enum>
<name>8BITS</name>
<value>0x0</value>
</enum>
<enum>
<name>16BITS</name>
<value>0x1</value>
</enum>
</field>
<field>
<name>MONO_STEREO</name>
<position>3</position>
<enum>
<name>STEREO</name>
<value>0x0</value>
</enum>
<enum>
<name>MONO</name>
<value>0x1</value>
</enum>
</field>
<field>
<name>IF_MODE</name>
<position>1</position>
<width>2</width>
<enum>
<name>I2S</name>
<value>0x0</value>
</enum>
<enum>
<name>LEFT_JUSTIFIED</name>
<value>0x1</value>
</enum>
<enum>
<name>RIGHT_JUSTIFIED</name>
<value>0x2</value>
</enum>
</field>
<field>
<name>MASTER_SLAVE</name>
<position>0</position>
<enum>
<name>SLAVE</name>
<value>0x0</value>
</enum>
<enum>
<name>MASTER</name>
<value>0x1</value>
</enum>
</field>
</register>
</node>
<node>
<name>FIFOSTS</name>
<instance>
<name>FIFOSTS</name>
<address>0x14</address>
</instance>
<register>
<desc>his register shows FIFO status and interrupts trigger level.</desc>
<field>
<name>RESERVED</name>
<position>20</position>
<width>12</width>
</field>
<field>
<name>TX_INT_TRIG</name>
<desc>Tx interrupt trigger level.</desc>
<position>18</position>
<width>2</width>
<enum>
<name>ALMOST_EMPTY</name>
<value>0x0</value>
</enum>
<enum>
<name>HALF_FULL</name>
<value>0x1</value>
</enum>
<enum>
<name>ALMOST_FULL</name>
<value>0x2</value>
</enum>
</field>
<field>
<name>RX_INT_TRIG</name>
<desc>Rx interrupt trigger level.</desc>
<position>16</position>
<width>2</width>
<enum>
<name>ALMOST_EMPTY</name>
<value>0x0</value>
</enum>
<enum>
<name>HALF_FULL</name>
<value>0x1</value>
</enum>
<enum>
<name>ALMOST_FULL</name>
<value>0x2</value>
</enum>
</field>
<field>
<name>RESERVED15_10</name>
<position>10</position>
<width>6</width>
</field>
<field>
<name>TX_FIFO_HALF</name>
<position>9</position>
</field>
<field>
<name>RX_FIFO_HALF</name>
<position>8</position>
</field>
<field>
<name>TX_FIFO_ALMOST_FULL</name>
<position>7</position>
</field>
<field>
<name>TX_FIFO_ALMOST_EMPTY</name>
<position>6</position>
</field>
<field>
<name>RX_FIFO_ALMOST_FULL</name>
<position>5</position>
</field>
<field>
<name>RX_FIFO_ALMOST_EMPTY</name>
<position>4</position>
</field>
<field>
<name>TX_FIFO_FULL</name>
<position>3</position>
</field>
<field>
<name>TX_FIFO_EMPTY</name>
<position>2</position>
</field>
<field>
<name>RX_FIFO_FULL</name>
<position>1</position>
</field>
<field>
<name>RX_FIFO_EMPTY</name>
<position>0</position>
</field>
</register>
</node>
<node>
<name>IER</name>
<instance>
<name>IER</name>
<address>0x18</address>
</instance>
<register>
<field>
<name>RESERVED31_3</name>
<position>3</position>
<width>29</width>
</field>
<field>
<name>TX_FIFO_LEVEL_EN</name>
<desc>This bit enables the interrupt when Tx FIFO trigger level is reached.</desc>
<position>2</position>
</field>
<field>
<name>RX_FIFO_LEVEL_EN</name>
<desc>This bit enables the interrupt when Rx FIFO trigger level is reached.</desc>
<position>1</position>
</field>
<field>
<name>RX_FIFO_OVERRUN_EN</name>
<desc>This bit enables the interrupt when Rx FIFO overrun condition occurred.</desc>
<position>0</position>
</field>
</register>
</node>
<node>
<name>ISR</name>
<instance>
<name>ISR</name>
<address>0x1c</address>
</instance>
<register>
<desc>I2S interrupt status register</desc>
<field>
<name>RESERVED31_3</name>
<position>3</position>
<width>29</width>
</field>
<field>
<name>TX_FIFO_LEVEL_INT</name>
<position>2</position>
</field>
<field>
<name>RX_FIFO_LEVEL_INT</name>
<position>1</position>
</field>
<field>
<name>RX_FIFO_OVERRUN_INT</name>
<position>0</position>
</field>
</register>
</node>
</node>
<node>
<name>ADC</name>
<title>ADC</title>
<desc>4 channels 10-bit SAR A/D converter</desc>
<instance>
<name>ADC</name>
<address>0x18030000</address>
</instance>
<node>
<name>DATA</name>
<instance>
<name>DATA</name>
<address>0x0</address>
</instance>
<register/>
</node>
<node>
<name>STAT</name>
<instance>
<name>STAT</name>
<address>0x4</address>
</instance>
<register/>
</node>
<node>
<name>CTRL</name>
<instance>
<name>CTRL</name>
<address>0x8</address>
</instance>
<register/>
</node>
</node>
<node>
<name>GPIO1</name>
<title>GPIO</title>
<desc>GPIO</desc>
<instance>
<name>GPIO1</name>
<address>0x18038000</address>
</instance>
<node>
<name>PEDR</name>
<instance>
<name>PEDR</name>
<address>0x0</address>
</instance>
<register/>
</node>
<node>
<name>PECON</name>
<instance>
<name>PECON</name>
<address>0x4</address>
</instance>
<register/>
</node>
<node>
<name>PFDR</name>
<instance>
<name>PFDR</name>
<address>0x8</address>
</instance>
<register/>
</node>
<node>
<name>PFCON</name>
<instance>
<name>PFCON</name>
<address>0xc</address>
</instance>
<register/>
</node>
<node>
<name>_TEST</name>
<instance>
<name>_TEST</name>
<address>0x20</address>
</instance>
<register/>
</node>
<node>
<name>IEE</name>
<instance>
<name>IEE</name>
<address>0x24</address>
</instance>
<register/>
</node>
<node>
<name>IEF</name>
<instance>
<name>IEF</name>
<address>0x28</address>
</instance>
<register/>
</node>
<node>
<name>ISE</name>
<instance>
<name>ISE</name>
<address>0x34</address>
</instance>
<register/>
</node>
<node>
<name>ISF</name>
<instance>
<name>ISF</name>
<address>0x38</address>
</instance>
<register/>
</node>
<node>
<name>IBEE</name>
<instance>
<name>IBEE</name>
<address>0x44</address>
</instance>
<register/>
</node>
<node>
<name>IBEF</name>
<instance>
<name>IBEF</name>
<address>0x48</address>
</instance>
<register/>
</node>
<node>
<name>IEVE</name>
<instance>
<name>IEVE</name>
<address>0x54</address>
</instance>
<register/>
</node>
<node>
<name>IEVF</name>
<instance>
<name>IEVF</name>
<address>0x58</address>
</instance>
<register/>
</node>
<node>
<name>ICE</name>
<instance>
<name>ICE</name>
<address>0x64</address>
</instance>
<register/>
</node>
<node>
<name>ICF</name>
<instance>
<name>ICF</name>
<address>0x68</address>
</instance>
<register/>
</node>
<node>
<name>ISR</name>
<instance>
<name>ISR</name>
<address>0x74</address>
</instance>
<register/>
</node>
</node>
<node>
<name>INTC</name>
<title>Interrupt controller</title>
<desc>Interrupt controller</desc>
<instance>
<name>INTC</name>
<address>0x18080000</address>
</instance>
<node>
<name>INTC_SCRn</name>
<instance>
<name>INTC_SCRn</name>
<range>
<first>0</first>
<count>32</count>
<base>0x0</base>
<stride>0x4</stride>
</range>
</instance>
<register/>
</node>
<node>
<name>ISR</name>
<instance>
<name>ISR</name>
<address>0x104</address>
</instance>
<register/>
</node>
<node>
<name>IPR</name>
<instance>
<name>IPR</name>
<address>0x108</address>
</instance>
<register/>
</node>
<node>
<name>IMR</name>
<instance>
<name>IMR</name>
<address>0x10c</address>
</instance>
<register/>
</node>
<node>
<name>IECR</name>
<instance>
<name>IECR</name>
<address>0x114</address>
</instance>
<register/>
</node>
<node>
<name>ICCR</name>
<instance>
<name>ICCR</name>
<address>0x118</address>
</instance>
<register/>
</node>
<node>
<name>ISCR</name>
<instance>
<name>ISCR</name>
<address>0x11c</address>
</instance>
<register/>
</node>
<node>
<name>TEST</name>
<instance>
<name>TEST</name>
<address>0x124</address>
</instance>
<register/>
</node>
</node>
<node>
<name>ARB</name>
<title>AHB bus arbiter</title>
<desc>AHB bus arbiter</desc>
<instance>
<name>ARB</name>
<address>0x18084000</address>
</instance>
<node>
<name>MODE</name>
<instance>
<name>MODE</name>
<address>0x0</address>
</instance>
<register/>
</node>
<node>
<name>PRIOn</name>
<instance>
<name>PRIOn</name>
<range>
<first>0</first>
<count>15</count>
<base>0x4</base>
<stride>0x4</stride>
</range>
</instance>
<register/>
</node>
</node>
<node>
<name>MAILBOX</name>
<title>CPU-DSP mailbox</title>
<desc>CPU-DSP mailbox</desc>
<instance>
<name>MAILBOX</name>
<address>0x18088000</address>
</instance>
<node>
<name>MAILBOX_ID</name>
<instance>
<name>MAILBOX_ID</name>
<address>0x0</address>
</instance>
<register/>
</node>
<node>
<name>H2C_STA</name>
<instance>
<name>H2C_STA</name>
<address>0x10</address>
</instance>
<register/>
</node>
<node>
<name>H2Cn_DATA</name>
<instance>
<name>H2Cn_DATA</name>
<range>
<first>0</first>
<count>4</count>
<base>0x20</base>
<stride>0x8</stride>
</range>
</instance>
<register/>
</node>
<node>
<name>H2Cn_CMD</name>
<instance>
<name>H2Cn_CMD</name>
<range>
<first>0</first>
<count>4</count>
<base>0x24</base>
<stride>0x8</stride>
</range>
</instance>
<register/>
</node>
<node>
<name>C2H_STA</name>
<instance>
<name>C2H_STA</name>
<address>0x40</address>
</instance>
<register/>
</node>
<node>
<name>C2Hn_DATA</name>
<instance>
<name>C2Hn_DATA</name>
<range>
<first>0</first>
<count>4</count>
<base>0x50</base>
<stride>0x8</stride>
</range>
</instance>
<register/>
</node>
<node>
<name>C2Hn_CMD</name>
<instance>
<name>C2Hn_CMD</name>
<range>
<first>0</first>
<count>4</count>
<base>0x54</base>
<stride>0x8</stride>
</range>
</instance>
<register/>
</node>
</node>
<node>
<name>HDMA</name>
<title>AHB DMA</title>
<desc>AHB DMA</desc>
<instance>
<name>HDMA</name>
<address>0x18090000</address>
</instance>
<node>
<name>CON</name>
<instance>
<name>CON0</name>
<address>0x0</address>
</instance>
<instance>
<name>CON1</name>
<address>0x4</address>
</instance>
<register/>
</node>
<node>
<name>ISRC</name>
<instance>
<name>ISRC0</name>
<address>0x8</address>
</instance>
<instance>
<name>ISRC1</name>
<address>0x14</address>
</instance>
<register/>
</node>
<node>
<name>IDST</name>
<instance>
<name>IDST0</name>
<address>0xc</address>
</instance>
<instance>
<name>IDST1</name>
<address>0x18</address>
</instance>
<register/>
</node>
<node>
<name>ICNT</name>
<instance>
<name>ICNT0</name>
<address>0x10</address>
</instance>
<instance>
<name>ICNT1</name>
<address>0x1c</address>
</instance>
<register/>
</node>
<node>
<name>CSRC</name>
<instance>
<name>CSRC0</name>
<address>0x20</address>
</instance>
<instance>
<name>CSRC1</name>
<address>0x2c</address>
</instance>
<register/>
</node>
<node>
<name>CDST</name>
<instance>
<name>CDST0</name>
<address>0x24</address>
</instance>
<instance>
<name>CDST1</name>
<address>0x30</address>
</instance>
<register/>
</node>
<node>
<name>CCNT</name>
<instance>
<name>CCNT0</name>
<address>0x28</address>
</instance>
<instance>
<name>CCNT1</name>
<address>0x34</address>
</instance>
<register/>
</node>
<node>
<name>ISR</name>
<instance>
<name>ISR</name>
<address>0x38</address>
</instance>
<register/>
</node>
<node>
<name>DSR</name>
<instance>
<name>DSR</name>
<address>0x3c</address>
</instance>
<register/>
</node>
<node>
<name>ISCNT</name>
<instance>
<name>ISCNT0</name>
<address>0x40</address>
</instance>
<instance>
<name>ISCNT1</name>
<address>0x4c</address>
</instance>
<register/>
</node>
<node>
<name>IPNCNTD</name>
<instance>
<name>IPNCNTD0</name>
<address>0x44</address>
</instance>
<instance>
<name>IPNCNTD1</name>
<address>0x50</address>
</instance>
<register/>
</node>
<node>
<name>IADDR_BS</name>
<instance>
<name>IADDR_BS0</name>
<address>0x48</address>
</instance>
<instance>
<name>IADDR_BS1</name>
<address>0x54</address>
</instance>
<register/>
</node>
<node>
<name>CSCNT</name>
<instance>
<name>CSCNT0</name>
<address>0x58</address>
</instance>
<instance>
<name>CSCNT1</name>
<address>0x64</address>
</instance>
<register/>
</node>
<node>
<name>CPNCNTD</name>
<instance>
<name>CPNCNTD0</name>
<address>0x5c</address>
</instance>
<instance>
<name>CPNCNTD1</name>
<address>0x68</address>
</instance>
<register/>
</node>
<node>
<name>CADDR_BS</name>
<instance>
<name>CADDR_BS0</name>
<address>0x60</address>
</instance>
<instance>
<name>CADDR_BS1</name>
<address>0x6c</address>
</instance>
<register/>
</node>
<node>
<name>PACNT</name>
<instance>
<name>PACNT0</name>
<address>0x70</address>
</instance>
<instance>
<name>PACNT1</name>
<address>0x74</address>
</instance>
<register/>
</node>
</node>
<node>
<name>A2A_DMA</name>
<title>AHB-to-AHB bridge</title>
<desc>AHB-to-AHB bridge with DMA</desc>
<instance>
<name>A2A_DMA</name>
<address>0x18094000</address>
</instance>
<node>
<name>CON</name>
<instance>
<name>CON0</name>
<address>0x0</address>
</instance>
<instance>
<name>CON1</name>
<address>0x1c</address>
</instance>
<register>
<field>
<name>RESERVED31_15</name>
<position>15</position>
<width>17</width>
</field>
<field>
<name>AUTO_RELOAD</name>
<position>14</position>
<enum>
<name>DISABLE</name>
<value>0x0</value>
</enum>
<enum>
<name>ENABLE</name>
<value>0x1</value>
</enum>
</field>
<field>
<name>DMA_HW_EN</name>
<position>13</position>
<enum>
<name>DISABLE</name>
<value>0x0</value>
</enum>
<enum>
<name>ENABLE</name>
<value>0x1</value>
</enum>
</field>
<field>
<name>INT_EN</name>
<position>12</position>
<enum>
<name>DISABLE</name>
<value>0x0</value>
</enum>
<enum>
<name>ENABLE</name>
<value>0x1</value>
</enum>
</field>
<field>
<name>ON_THE_FLY</name>
<desc>On the fly transfer can be applied on DMA which source and destination addresses are at the different bus domain.
</desc>
<position>11</position>
<enum>
<name>DISABLE</name>
<value>0x0</value>
</enum>
<enum>
<name>ENABLE</name>
<value>0x1</value>
</enum>
</field>
<field>
<name>XFER_MODE</name>
<desc>Burst size</desc>
<position>9</position>
<width>2</width>
<enum>
<name>SINGLE</name>
<value>0x0</value>
</enum>
<enum>
<name>INCR4</name>
<value>0x1</value>
</enum>
<enum>
<name>INCR8</name>
<value>0x2</value>
</enum>
<enum>
<name>INCR16</name>
<value>0x3</value>
</enum>
</field>
<field>
<name>HDREQ_SRC</name>
<position>7</position>
<width>2</width>
<enum>
<name>SDMMC</name>
<value>0x0</value>
</enum>
</field>
<field>
<name>SRC_INC</name>
<position>6</position>
<enum>
<name>INCREMENT</name>
<value>0x0</value>
</enum>
<enum>
<name>FIXED</name>
<value>0x1</value>
</enum>
</field>
<field>
<name>DST_INC</name>
<position>5</position>
<enum>
<name>INCREMENT</name>
<value>0x0</value>
</enum>
<enum>
<name>FIXED</name>
<value>0x1</value>
</enum>
</field>
<field>
<name>DMA_SW_CMD</name>
<position>3</position>
<width>2</width>
<enum>
<name>NO_CMD</name>
<value>0x0</value>
</enum>
<enum>
<name>START_SW_DMA</name>
<value>0x1</value>
</enum>
<enum>
<name>PAUSE_SW_DMA</name>
<value>0x2</value>
</enum>
<enum>
<name>CANCEL_SW_DMA</name>
<value>0x3</value>
</enum>
</field>
<field>
<name>XFER_WIDTH</name>
<position>1</position>
<width>2</width>
<enum>
<name>BYTE</name>
<value>0x0</value>
</enum>
<enum>
<name>HALFWORD</name>
<value>0x1</value>
</enum>
<enum>
<name>WORD</name>
<value>0x2</value>
</enum>
<enum>
<name>RESERVED</name>
<value>0x3</value>
</enum>
</field>
<field>
<name>DMA_MODE</name>
<position>0</position>
<enum>
<name>HW_BLOCK_MODE</name>
<value>0x0</value>
</enum>
<enum>
<name>SW_MODE</name>
<value>0x1</value>
</enum>
</field>
</register>
</node>
<node>
<name>ISRC</name>
<instance>
<name>ISRC0</name>
<address>0x4</address>
</instance>
<instance>
<name>ISRC1</name>
<address>0x20</address>
</instance>
<register>
<desc>A2A DMA initial source address register.</desc>
</register>
</node>
<node>
<name>IDST</name>
<instance>
<name>IDST0</name>
<address>0x8</address>
</instance>
<instance>
<name>IDST1</name>
<address>0x24</address>
</instance>
<register>
<desc>A2A DMA initial destination address register.</desc>
</register>
</node>
<node>
<name>ICNT</name>
<instance>
<name>ICNT0</name>
<address>0xc</address>
</instance>
<instance>
<name>ICNT1</name>
<address>0x28</address>
</instance>
<register>
<field>
<name>RESERVED31_16</name>
<position>16</position>
<width>16</width>
</field>
<field>
<name>CNT</name>
<desc>DMA initial terminate count register for channel x.</desc>
<position>0</position>
<width>16</width>
</field>
</register>
</node>
<node>
<name>CSRC</name>
<instance>
<name>CSRC0</name>
<address>0x10</address>
</instance>
<instance>
<name>CSRC1</name>
<address>0x2c</address>
</instance>
<register>
<desc>A2A DMA current source address register.</desc>
</register>
</node>
<node>
<name>CDST</name>
<instance>
<name>CDST0</name>
<address>0x14</address>
</instance>
<instance>
<name>CDST1</name>
<address>0x30</address>
</instance>
<register>
<desc>A2A DMA current destination address register.</desc>
</register>
</node>
<node>
<name>CCNT</name>
<instance>
<name>CCNT0</name>
<address>0x18</address>
</instance>
<instance>
<name>CCNT1</name>
<address>0x34</address>
</instance>
<register>
<field>
<name>RESERVED31_16</name>
<position>16</position>
<width>16</width>
</field>
<field>
<name>CNT</name>
<position>0</position>
<width>16</width>
</field>
</register>
</node>
<node>
<name>INT_STS</name>
<instance>
<name>INT_STS</name>
<address>0x38</address>
</instance>
<register>
<field>
<name>RESERVED31_4</name>
<position>4</position>
<width>28</width>
</field>
<field>
<name>AHB2_ERR_INT</name>
<position>3</position>
<enum>
<name>NO_ERROR</name>
<value>0x0</value>
</enum>
<enum>
<name>ERROR</name>
<value>0x1</value>
</enum>
</field>
<field>
<name>AHB1_ERR_INT</name>
<position>2</position>
<enum>
<name>NO_ERROR</name>
<value>0x0</value>
</enum>
<enum>
<name>ERROR</name>
<value>0x1</value>
</enum>
</field>
<field>
<name>CHANNEL1_INT</name>
<desc>Channel 1 Interrupt active, clear interrupt after write.</desc>
<position>1</position>
<enum>
<name>NOT_ACTIVE</name>
<value>0x0</value>
</enum>
<enum>
<name>ACTIVE</name>
<value>0x1</value>
</enum>
</field>
<field>
<name>CHANNEL0_INT</name>
<desc>Channel 0 Interrupt active, clear interrupt after write.</desc>
<position>0</position>
<enum>
<name>NOT_ACTIVE</name>
<value>0x0</value>
</enum>
<enum>
<name>ACTIVE</name>
<value>0x1</value>
</enum>
</field>
</register>
</node>
<node>
<name>DMA_STS</name>
<instance>
<name>DMA_STS</name>
<address>0x3c</address>
</instance>
<register>
<field>
<name>RESERVED31_2</name>
<position>2</position>
<width>30</width>
</field>
<field>
<name>CHANNEL1_BUSY</name>
<position>1</position>
<enum>
<name>FREE</name>
<value>0x0</value>
</enum>
<enum>
<name>BUSY</name>
<value>0x1</value>
</enum>
</field>
<field>
<name>CHANNEL0_BUSY</name>
<position>0</position>
<enum>
<name>FREE</name>
<value>0x0</value>
</enum>
<enum>
<name>BUSY</name>
<value>0x1</value>
</enum>
</field>
</register>
</node>
<node>
<name>ERR_ADR</name>
<instance>
<name>ERR_ADR0</name>
<address>0x40</address>
</instance>
<instance>
<name>ERR_ADR1</name>
<address>0x48</address>
</instance>
<register/>
</node>
<node>
<name>ERR_OP</name>
<instance>
<name>ERR_OP0</name>
<address>0x44</address>
</instance>
<instance>
<name>ERR_OP1</name>
<address>0x4c</address>
</instance>
<register>
<field>
<name>RESERVED31_1</name>
<position>1</position>
<width>31</width>
</field>
<field>
<name>DIR</name>
<position>0</position>
<enum>
<name>READ</name>
<value>0x0</value>
</enum>
<enum>
<name>WRITE</name>
<value>0x1</value>
</enum>
</field>
</register>
</node>
<node>
<name>LCNT</name>
<instance>
<name>LCNT0</name>
<address>0x50</address>
</instance>
<instance>
<name>LCNT1</name>
<address>0x54</address>
</instance>
<register>
<field>
<name>RESERVED31_3</name>
<position>3</position>
<width>29</width>
</field>
<field>
<name>LOCK_CNT</name>
<desc>Bus lock counts at on-the-fly mode.</desc>
<position>0</position>
<width>3</width>
<enum>
<name>NEVER</name>
<value>0x0</value>
</enum>
<enum>
<name>16BITS</name>
<value>0x1</value>
</enum>
<enum>
<name>32BITS</name>
<value>0x2</value>
</enum>
<enum>
<name>64BITS</name>
<value>0x3</value>
</enum>
<enum>
<name>128BITS</name>
<value>0x4</value>
</enum>
<enum>
<name>256BITS</name>
<value>0x5</value>
</enum>
<enum>
<name>512BITS</name>
<value>0x6</value>
</enum>
<enum>
<name>1024BITS</name>
<value>0x7</value>
</enum>
</field>
</register>
</node>
<node>
<name>DOMAIN</name>
<instance>
<name>DOMAIN</name>
<address>0x58</address>
</instance>
<register>
<field>
<name>RESERVED31_4</name>
<position>4</position>
<width>28</width>
</field>
<field>
<name>CH1_DST_DOMAIN</name>
<position>3</position>
<enum>
<name>AHB0</name>
<value>0x0</value>
</enum>
<enum>
<name>AHB1</name>
<value>0x1</value>
</enum>
</field>
<field>
<name>CH1_SRC_DOMAIN</name>
<position>2</position>
<enum>
<name>AHB0</name>
<value>0x0</value>
</enum>
<enum>
<name>AHB1</name>
<value>0x1</value>
</enum>
</field>
<field>
<name>CH0_DST_DOMAIN</name>
<position>1</position>
<enum>
<name>AHB0</name>
<value>0x0</value>
</enum>
<enum>
<name>AHB1</name>
<value>0x1</value>
</enum>
</field>
<field>
<name>CH0_SRC_DOMAIN</name>
<position>0</position>
<enum>
<name>AHB0</name>
<value>0x0</value>
</enum>
<enum>
<name>AHB1</name>
<value>0x1</value>
</enum>
</field>
</register>
</node>
</node>
<node>
<name>UDC</name>
<title>USB 2.0 Device Controller</title>
<desc>USB 2.0 Device Controller</desc>
<instance>
<name>UDC</name>
<address>0x180a0000</address>
</instance>
<node>
<name>DEV_CTL</name>
<instance>
<name>DEV_CTL</name>
<address>0x8</address>
</instance>
<register>
<field>
<name>RESERVED</name>
<position>10</position>
<width>22</width>
</field>
<field>
<name>TEST_MODE</name>
<position>9</position>
</field>
<field>
<name>CSR_DONE</name>
<position>8</position>
</field>
<field>
<name>SOFT_POR</name>
<position>7</position>
</field>
<field>
<name>DEV_PHYBUS16_8</name>
<position>6</position>
</field>
<field>
<name>DEV_RESUME</name>
<position>5</position>
</field>
<field>
<name>DEV_SOFT_CN</name>
<position>4</position>
</field>
<field>
<name>DEV_SELF_PWR</name>
<position>3</position>
</field>
<field>
<name>DEV_RMTWKP</name>
<position>2</position>
</field>
<field>
<name>DEV_SPEED</name>
<position>0</position>
<width>2</width>
<enum>
<name>HS</name>
<desc>High Speed</desc>
<value>0x0</value>
</enum>
</field>
</register>
</node>
<node>
<name>DEV_INFO</name>
<instance>
<name>DEV_INFO</name>
<address>0x10</address>
</instance>
<register>
<field>
<name>RESERVED</name>
<position>23</position>
<width>9</width>
</field>
<field>
<name>DEV_SPEED</name>
<position>21</position>
<width>2</width>
<enum>
<name>HS</name>
<desc>High Speed</desc>
<value>0x0</value>
</enum>
<enum>
<name>FS</name>
<desc>Full Speed</desc>
<value>0x3</value>
</enum>
</field>
<field>
<name>VBUS_SYNC</name>
<position>20</position>
<enum>
<name>DISCONNECTION</name>
<value>0x0</value>
</enum>
<enum>
<name>CONNECTION</name>
<value>0x1</value>
</enum>
</field>
<field>
<name>DEV_ALTINTF</name>
<position>16</position>
<width>4</width>
</field>
<field>
<name>INTF_NUMBER</name>
<position>12</position>
<width>4</width>
</field>
<field>
<name>CFG_NUMBER</name>
<position>8</position>
<width>4</width>
</field>
<field>
<name>DEV_EN</name>
<position>7</position>
</field>
<field>
<name>DEV_ADDRESS</name>
<position>0</position>
<width>7</width>
</field>
</register>
</node>
<node>
<name>EN_INT</name>
<instance>
<name>EN_INT</name>
<address>0x14</address>
</instance>
<register>
<field>
<name>RESERVED31_27</name>
<position>27</position>
<width>5</width>
</field>
<field>
<name>TEST_PKT</name>
<position>26</position>
</field>
<field>
<name>TEST_K</name>
<position>25</position>
</field>
<field>
<name>TEST_J</name>
<position>24</position>
</field>
<field>
<name>TEST_SE0_NAK</name>
<position>23</position>
</field>
<field>
<name>EN_IIN15_INTR</name>
<position>22</position>
</field>
<field>
<name>EN_BIN14_INTR</name>
<position>21</position>
</field>
<field>
<name>EN_BOUT13_INTR</name>
<position>20</position>
</field>
<field>
<name>EN_IIN12_INTR</name>
<position>19</position>
</field>
<field>
<name>EN_BIN11_INTR</name>
<position>18</position>
</field>
<field>
<name>EN_BOUT10_INTR</name>
<position>17</position>
</field>
<field>
<name>EN_IIN9_INTR</name>
<position>16</position>
</field>
<field>
<name>EN_BIN8_INTR</name>
<position>15</position>
</field>
<field>
<name>EN_BOUT7_INTR</name>
<position>14</position>
</field>
<field>
<name>EN_IIN6_INTR</name>
<position>13</position>
</field>
<field>
<name>EN_BIN5_INTR</name>
<position>12</position>
</field>
<field>
<name>EN_BOUT4_INTR</name>
<position>11</position>
</field>
<field>
<name>EN_IIN3_INTR</name>
<position>10</position>
</field>
<field>
<name>EN_BIN2_INTR</name>
<position>9</position>
</field>
<field>
<name>EN_BOUT1_INTR</name>
<position>8</position>
</field>
<field>
<name>RESERVED</name>
<position>7</position>
</field>
<field>
<name>EN_SUSP_INTR</name>
<position>6</position>
</field>
<field>
<name>EN_RSUME_INTR</name>
<position>5</position>
</field>
<field>
<name>EN_USBRST_INTR</name>
<position>4</position>
</field>
<field>
<name>EN_OUT0_INTR</name>
<position>3</position>
</field>
<field>
<name>EN_IN0_INTR</name>
<position>2</position>
</field>
<field>
<name>EN_SETUP_INTR</name>
<position>1</position>
</field>
<field>
<name>EN_SOF_INTR</name>
<position>0</position>
</field>
</register>
</node>
<node>
<name>INT2FLAG</name>
<instance>
<name>INT2FLAG</name>
<address>0x18</address>
</instance>
<register>
<field>
<name>RESERVED31_27</name>
<position>27</position>
<width>5</width>
</field>
<field>
<name>TEST_PKT</name>
<position>26</position>
</field>
<field>
<name>TEST_K</name>
<position>25</position>
</field>
<field>
<name>TEST_J</name>
<position>24</position>
</field>
<field>
<name>TEST_SE0_NAK</name>
<position>23</position>
</field>
<field>
<name>IIN15_INTR</name>
<position>22</position>
</field>
<field>
<name>BIN14_INTR</name>
<position>21</position>
</field>
<field>
<name>BOUT13_INTR</name>
<position>20</position>
</field>
<field>
<name>IIN12_INTR</name>
<position>19</position>
</field>
<field>
<name>BIN11_INTR</name>
<position>18</position>
</field>
<field>
<name>BOUT10_INTR</name>
<position>17</position>
</field>
<field>
<name>IIN9_INTR</name>
<position>16</position>
</field>
<field>
<name>BIN8_INTR</name>
<position>15</position>
</field>
<field>
<name>BOUT7_INTR</name>
<position>14</position>
</field>
<field>
<name>IIN6_INTR</name>
<position>13</position>
</field>
<field>
<name>BIN5_INTR</name>
<position>12</position>
</field>
<field>
<name>BOUT4_INTR</name>
<position>11</position>
</field>
<field>
<name>IIN3_INTR</name>
<position>10</position>
</field>
<field>
<name>BIN2_INTR</name>
<position>9</position>
</field>
<field>
<name>BOUT1_INTR</name>
<position>8</position>
</field>
<field>
<name>RESERVED7</name>
<position>7</position>
</field>
<field>
<name>SUSP_INTR</name>
<position>6</position>
</field>
<field>
<name>RSUME_INTR</name>
<position>5</position>
</field>
<field>
<name>USBRST_INTR</name>
<position>4</position>
</field>
<field>
<name>OUT0_INTR</name>
<position>3</position>
</field>
<field>
<name>IN0_INTR</name>
<position>2</position>
</field>
<field>
<name>SETUP_INTR</name>
<position>1</position>
</field>
<field>
<name>SOF_INTR</name>
<position>0</position>
</field>
</register>
</node>
<node>
<name>INTCON</name>
<instance>
<name>INTCON</name>
<address>0x1c</address>
</instance>
<register>
<field>
<name>RESERVED</name>
<position>3</position>
<width>29</width>
</field>
<field>
<name>INT0MODE</name>
<position>2</position>
<enum>
<name>ACTIVE_LOW</name>
<value>0x0</value>
</enum>
<enum>
<name>ACTIVE_HIGH</name>
<value>0x1</value>
</enum>
</field>
<field>
<name>INT0TYPE</name>
<position>1</position>
<enum>
<name>LEVEL_TRIGGER</name>
<value>0x0</value>
</enum>
<enum>
<name>EDGE_TRIGGER</name>
<value>0x1</value>
</enum>
</field>
<field>
<name>INT0EN</name>
<position>0</position>
<enum>
<name>DISABLE</name>
<value>0x0</value>
</enum>
<enum>
<name>ENABLE</name>
<value>0x1</value>
</enum>
</field>
</register>
</node>
<node>
<name>SETUP1</name>
<instance>
<name>SETUP1</name>
<address>0x20</address>
</instance>
<register>
<field>
<name>wValue</name>
<position>16</position>
<width>16</width>
</field>
<field>
<name>bRequest</name>
<position>8</position>
<width>8</width>
<enum>
<name>GetStatus</name>
<value>0x0</value>
</enum>
<enum>
<name>ClearFeature</name>
<value>0x1</value>
</enum>
<enum>
<name>Reserved2</name>
<value>0x2</value>
</enum>
<enum>
<name>SetFeature</name>
<value>0x3</value>
</enum>
<enum>
<name>Reserved4</name>
<value>0x4</value>
</enum>
<enum>
<name>SetAddress</name>
<value>0x5</value>
</enum>
<enum>
<name>GetDescriptor</name>
<value>0x6</value>
</enum>
<enum>
<name>SetDescriptor</name>
<value>0x7</value>
</enum>
<enum>
<name>GetConfiguration</name>
<value>0x8</value>
</enum>
<enum>
<name>SetConfiguration</name>
<value>0x9</value>
</enum>
<enum>
<name>GetInterface</name>
<value>0xa</value>
</enum>
<enum>
<name>SetInterface</name>
<value>0xb</value>
</enum>
<enum>
<name>SyncFrame</name>
<value>0xc</value>
</enum>
</field>
<field>
<name>bmRequestTypeDir</name>
<position>7</position>
<enum>
<name>Host2Device</name>
<value>0x0</value>
</enum>
<enum>
<name>Device2Host</name>
<value>0x1</value>
</enum>
</field>
<field>
<name>bmRequestType</name>
<position>5</position>
<width>2</width>
<enum>
<name>Standard</name>
<value>0x0</value>
</enum>
<enum>
<name>Class</name>
<value>0x1</value>
</enum>
<enum>
<name>Vendor</name>
<value>0x2</value>
</enum>
</field>
<field>
<name>bmRequestTypeRecipient</name>
<position>0</position>
<width>5</width>
<enum>
<name>Device</name>
<value>0x0</value>
</enum>
<enum>
<name>Interface</name>
<value>0x1</value>
</enum>
<enum>
<name>Endpoint</name>
<value>0x2</value>
</enum>
<enum>
<name>Other</name>
<value>0x3</value>
</enum>
</field>
</register>
</node>
<node>
<name>SETUP2</name>
<instance>
<name>SETUP2</name>
<address>0x24</address>
</instance>
<register>
<field>
<name>wLength</name>
<position>16</position>
<width>16</width>
</field>
<field>
<name>wIndex</name>
<position>0</position>
<width>16</width>
</field>
</register>
</node>
<node>
<name>AHBCON</name>
<instance>
<name>AHBCON</name>
<address>0x28</address>
</instance>
<register>
<field>
<name>RESERVED</name>
<position>4</position>
<width>28</width>
</field>
<field>
<name>MID</name>
<position>0</position>
<width>4</width>
</field>
</register>
</node>
<node>
<name>RX0STAT</name>
<instance>
<name>RX0STAT</name>
<address>0x30</address>
</instance>
<register>
<field>
<name>RESERVED31_26</name>
<position>26</position>
<width>6</width>
</field>
<field>
<name>RX0OVF</name>
<position>25</position>
</field>
<field>
<name>RX0FULL</name>
<position>24</position>
</field>
<field>
<name>RESERVED23_19</name>
<position>19</position>
<width>5</width>
</field>
<field>
<name>RX0ACK</name>
<position>18</position>
</field>
<field>
<name>RX0ERR</name>
<position>17</position>
</field>
<field>
<name>RX0VOID</name>
<position>16</position>
</field>
<field>
<name>RESERVED15_11</name>
<position>11</position>
<width>5</width>
</field>
<field>
<name>RX0LEN</name>
<position>0</position>
<width>11</width>
</field>
</register>
</node>
<node>
<name>RX0CON</name>
<instance>
<name>RX0CON</name>
<address>0x34</address>
</instance>
<register>
<field>
<name>RESERVED31_8</name>
<position>8</position>
<width>24</width>
</field>
<field>
<name>RX0ACKINTEN</name>
<position>7</position>
</field>
<field>
<name>RX0ERRINTEN</name>
<position>6</position>
</field>
<field>
<name>RX0VOIDINTEN</name>
<position>5</position>
</field>
<field>
<name>EP0EN</name>
<position>4</position>
</field>
<field>
<name>RX0NAK</name>
<position>3</position>
</field>
<field>
<name>RX0STALL</name>
<position>2</position>
</field>
<field>
<name>RX0CLR</name>
<position>1</position>
</field>
<field>
<name>RX0FFRC</name>
<position>0</position>
</field>
</register>
</node>
<node>
<name>RX0DMACTLO</name>
<instance>
<name>RX0DMACTLO</name>
<address>0x38</address>
</instance>
<register>
<field>
<name>RESERVED31_1</name>
<position>1</position>
<width>31</width>
</field>
<field>
<name>DMA0OUTSTA</name>
<position>0</position>
</field>
</register>
</node>
<node>
<name>RX0DMAOUTLMADDR</name>
<instance>
<name>RX0DMAOUTLMADDR</name>
<address>0x3c</address>
</instance>
<register>
<field>
<name>LM0OUTADDR</name>
<desc>DMA word aligned buffer address</desc>
<position>0</position>
<width>32</width>
</field>
</register>
</node>
<node>
<name>TX0STAT</name>
<instance>
<name>TX0STAT</name>
<address>0x40</address>
</instance>
<register>
<field>
<name>RESERVED31_19</name>
<position>19</position>
<width>13</width>
</field>
<field>
<name>TX0ACK</name>
<position>18</position>
</field>
<field>
<name>TX0ERR</name>
<position>17</position>
</field>
<field>
<name>TX0VOID</name>
<position>16</position>
</field>
<field>
<name>RESERVED15_11</name>
<position>11</position>
<width>5</width>
</field>
<field>
<name>TX0LEN</name>
<position>0</position>
<width>11</width>
</field>
</register>
</node>
<node>
<name>TX0CON</name>
<instance>
<name>TX0CON</name>
<address>0x44</address>
</instance>
<register>
<field>
<name>RESERVED31_7</name>
<position>7</position>
<width>25</width>
</field>
<field>
<name>TX0ACKINTEN</name>
<position>6</position>
</field>
<field>
<name>TX0ERRINTEN</name>
<position>5</position>
</field>
<field>
<name>TX0VOIDINTEN</name>
<position>4</position>
</field>
<field>
<name>RESERVED3</name>
<position>3</position>
</field>
<field>
<name>TX0NAK</name>
<position>2</position>
</field>
<field>
<name>TX0STALL</name>
<position>1</position>
</field>
<field>
<name>TX0CLR</name>
<position>0</position>
</field>
</register>
</node>
<node>
<name>TX0BUF</name>
<instance>
<name>TX0BUF</name>
<address>0x48</address>
</instance>
<register>
<field>
<name>RESERVED31_2</name>
<position>2</position>
<width>30</width>
</field>
<field>
<name>TX0URF</name>
<position>1</position>
</field>
<field>
<name>TX0FULL</name>
<position>0</position>
</field>
</register>
</node>
<node>
<name>TX0DMAINCTL</name>
<instance>
<name>TX0DMAINCTL</name>
<address>0x4c</address>
</instance>
<register>
<field>
<name>RESERVED31_1</name>
<position>1</position>
<width>31</width>
</field>
<field>
<name>DMA0INSTA</name>
<position>0</position>
</field>
</register>
</node>
<node>
<name>TX0DMALM_IADDR</name>
<instance>
<name>TX0DMALM_IADDR</name>
<address>0x50</address>
</instance>
<register>
<field>
<name>LM0INADDR</name>
<desc>DMA word aligned buffer address</desc>
<position>0</position>
<width>32</width>
</field>
</register>
</node>
<node>
<name>RX_BLK_STAT</name>
<instance>
<name>RX1STAT</name>
<address>0x54</address>
</instance>
<instance>
<name>RX4STAT</name>
<address>0x8c</address>
</instance>
<instance>
<name>RX7STAT</name>
<address>0xc4</address>
</instance>
<instance>
<name>RX10STAT</name>
<address>0xfc</address>
</instance>
<instance>
<name>RX13STAT</name>
<address>0x134</address>
</instance>
<register>
<field>
<name>RESERVED31_26</name>
<position>26</position>
<width>6</width>
</field>
<field>
<name>RXOVF</name>
<position>25</position>
</field>
<field>
<name>RXFULL</name>
<position>24</position>
</field>
<field>
<name>RESERVED23_20</name>
<position>20</position>
<width>4</width>
</field>
<field>
<name>RX_CF_INT</name>
<position>19</position>
</field>
<field>
<name>RXACK</name>
<position>18</position>
</field>
<field>
<name>RXERR</name>
<position>17</position>
</field>
<field>
<name>RXVOID</name>
<position>16</position>
</field>
<field>
<name>RESERVED15_11</name>
<position>11</position>
<width>5</width>
</field>
<field>
<name>RXCNT</name>
<position>0</position>
<width>11</width>
</field>
</register>
</node>
<node>
<name>RX_BLK_CON</name>
<instance>
<name>RX1CON</name>
<address>0x58</address>
</instance>
<instance>
<name>RX4CON</name>
<address>0x90</address>
</instance>
<instance>
<name>RX7CON</name>
<address>0xc8</address>
</instance>
<instance>
<name>RX10CON</name>
<address>0x100</address>
</instance>
<instance>
<name>RX13CON</name>
<address>0x138</address>
</instance>
<register>
<field>
<name>RESERVED31_14</name>
<position>14</position>
<width>18</width>
</field>
<field>
<name>RXSTALL_AUTOCLR</name>
<position>13</position>
</field>
<field>
<name>RX_CF_INTE</name>
<position>12</position>
</field>
<field>
<name>RXENDP_NUM</name>
<position>8</position>
<width>4</width>
</field>
<field>
<name>RXACKINTEN</name>
<position>7</position>
</field>
<field>
<name>RXERRINTEN</name>
<position>6</position>
</field>
<field>
<name>RXVOIDINTEN</name>
<position>5</position>
</field>
<field>
<name>EPEN</name>
<position>4</position>
</field>
<field>
<name>RXNAK</name>
<position>3</position>
</field>
<field>
<name>RXSTALL</name>
<position>2</position>
</field>
<field>
<name>RXCLR</name>
<position>1</position>
</field>
<field>
<name>RXFFRC</name>
<position>0</position>
</field>
</register>
</node>
<node>
<name>RX_BLK_DMACTLO</name>
<instance>
<name>RX1DMACTLO</name>
<address>0x5c</address>
</instance>
<instance>
<name>RX4DMACTLO</name>
<address>0x94</address>
</instance>
<instance>
<name>RX7DMACTLO</name>
<address>0xcc</address>
</instance>
<instance>
<name>RX10DMACTLO</name>
<address>0x104</address>
</instance>
<instance>
<name>RX13DMACTLO</name>
<address>0x13c</address>
</instance>
<register>
<field>
<name>RESERVED31_1</name>
<position>1</position>
<width>31</width>
</field>
<field>
<name>DMAOUTSTA</name>
<position>0</position>
</field>
</register>
</node>
<node>
<name>RX_BLK_DMAOUTLMADDR</name>
<instance>
<name>RX1DMAOUTLMADDR</name>
<address>0x60</address>
</instance>
<instance>
<name>RX4DMAOUTLMADDR</name>
<address>0x98</address>
</instance>
<instance>
<name>RX7DMAOUTLMADDR</name>
<address>0xd0</address>
</instance>
<instance>
<name>RX10DMAOUTLMADDR</name>
<address>0x108</address>
</instance>
<instance>
<name>RX13DMAOUTLMADDR</name>
<address>0x140</address>
</instance>
<register>
<field>
<name>LMOUTADDR</name>
<desc>Address of word aligned buffer</desc>
<position>0</position>
<width>32</width>
</field>
</register>
</node>
<node>
<name>TX_BLK_STAT</name>
<instance>
<name>TX2STAT</name>
<address>0x64</address>
</instance>
<instance>
<name>TX5STAT</name>
<address>0xc9</address>
</instance>
<instance>
<name>TX8STAT</name>
<address>0xd4</address>
</instance>
<instance>
<name>TX11STAT</name>
<address>0x10c</address>
</instance>
<instance>
<name>TX14STAT</name>
<address>0x144</address>
</instance>
<register>
<field>
<name>RESERVED31_21</name>
<position>21</position>
<width>11</width>
</field>
<field>
<name>TX_CF_INT</name>
<position>20</position>
</field>
<field>
<name>TXDMA_DN</name>
<position>19</position>
</field>
<field>
<name>TXACK</name>
<position>18</position>
</field>
<field>
<name>TXERR</name>
<position>17</position>
</field>
<field>
<name>TXVOID</name>
<position>16</position>
</field>
<field>
<name>RESERVED15_11</name>
<position>11</position>
<width>5</width>
</field>
<field>
<name>TXLEN</name>
<position>0</position>
<width>11</width>
</field>
</register>
</node>
<node>
<name>TX_BLK_CON</name>
<instance>
<name>TX2CON</name>
<address>0x68</address>
</instance>
<instance>
<name>TX5CON</name>
<address>0xa0</address>
</instance>
<instance>
<name>TX8CON</name>
<address>0xd8</address>
</instance>
<instance>
<name>TX11CON</name>
<address>0x110</address>
</instance>
<instance>
<name>TX14CON</name>
<address>0x148</address>
</instance>
<register>
<field>
<name>RESERVED31_14</name>
<position>14</position>
<width>18</width>
</field>
<field>
<name>TXSTALL_AUTOCLR</name>
<position>13</position>
</field>
<field>
<name>TX_CF_INTE</name>
<position>12</position>
</field>
<field>
<name>TXENDP_NUM</name>
<position>8</position>
<width>4</width>
</field>
<field>
<name>TXDMADN_EN</name>
<position>7</position>
</field>
<field>
<name>TXACKINTEN</name>
<position>6</position>
</field>
<field>
<name>TXERRINTEN</name>
<position>5</position>
</field>
<field>
<name>TXVOIDINTEN</name>
<position>4</position>
</field>
<field>
<name>TXEPEN</name>
<position>3</position>
</field>
<field>
<name>TXNAK</name>
<position>2</position>
</field>
<field>
<name>TXSTALL</name>
<position>1</position>
</field>
<field>
<name>TXCLR</name>
<position>0</position>
</field>
</register>
</node>
<node>
<name>TX_BLK_BUF</name>
<instance>
<name>TX2BUF</name>
<address>0x6c</address>
</instance>
<instance>
<name>TX5BUF</name>
<address>0xa4</address>
</instance>
<instance>
<name>TX8BUF</name>
<address>0xdc</address>
</instance>
<instance>
<name>TX11BUF</name>
<address>0x114</address>
</instance>
<instance>
<name>TX14BUF</name>
<address>0x14c</address>
</instance>
<register>
<field>
<name>RESERVED31_4</name>
<position>4</position>
<width>28</width>
</field>
<field>
<name>TXDS1</name>
<position>3</position>
</field>
<field>
<name>TXDS0</name>
<position>2</position>
</field>
<field>
<name>TXURF</name>
<position>1</position>
</field>
<field>
<name>TXFULL</name>
<position>0</position>
</field>
</register>
</node>
<node>
<name>TX_BLK_DMAINCTL</name>
<instance>
<name>TX2DMAINCTL</name>
<address>0x70</address>
</instance>
<instance>
<name>TX5DMAINCTL</name>
<address>0xa8</address>
</instance>
<instance>
<name>TX8DMAINCTL</name>
<address>0xe0</address>
</instance>
<instance>
<name>TX11DMAINCTL</name>
<address>0x118</address>
</instance>
<instance>
<name>TX14DMAINCTL</name>
<address>0x150</address>
</instance>
<register>
<field>
<name>RESERVED31_1</name>
<position>1</position>
<width>31</width>
</field>
<field>
<name>DMAINSTA</name>
<position>0</position>
</field>
</register>
</node>
<node>
<name>TX_BLK_DMALM_IADDR</name>
<instance>
<name>TX2DMALM_IADDR</name>
<address>0x74</address>
</instance>
<instance>
<name>TX5DMALM_IADDR</name>
<address>0xac</address>
</instance>
<instance>
<name>TX8DMALM_IADDR</name>
<address>0xe4</address>
</instance>
<instance>
<name>TX11DMALM_IADDR</name>
<address>0x11c</address>
</instance>
<instance>
<name>TX14DMALM_IADDR</name>
<address>0x154</address>
</instance>
<register>
<field>
<name>LMINADDR</name>
<desc>DMA word aligned buffer address</desc>
<position>0</position>
<width>32</width>
</field>
</register>
</node>
<node>
<name>TX_INT_STAT</name>
<instance>
<name>TX3STAT</name>
<address>0x78</address>
</instance>
<instance>
<name>TX6STAT</name>
<address>0xb0</address>
</instance>
<instance>
<name>TX9STAT</name>
<address>0xe8</address>
</instance>
<instance>
<name>TX12STAT</name>
<address>0x120</address>
</instance>
<instance>
<name>TX15STAT</name>
<address>0x158</address>
</instance>
<register>
<field>
<name>RESERVED31_20</name>
<position>20</position>
<width>12</width>
</field>
<field>
<name>TX_CF_INT</name>
<position>19</position>
</field>
<field>
<name>TXACK</name>
<position>18</position>
</field>
<field>
<name>TXERR</name>
<position>17</position>
</field>
<field>
<name>TXVOID</name>
<position>16</position>
</field>
<field>
<name>RESERVED15_11</name>
<position>11</position>
<width>5</width>
</field>
<field>
<name>TXLEN</name>
<position>0</position>
<width>11</width>
</field>
</register>
</node>
<node>
<name>TX_INT_CON</name>
<instance>
<name>TX3CON</name>
<address>0x7c</address>
</instance>
<instance>
<name>TX6CON</name>
<address>0xb4</address>
</instance>
<instance>
<name>TX9CON</name>
<address>0xec</address>
</instance>
<instance>
<name>TX12CON</name>
<address>0x124</address>
</instance>
<instance>
<name>TX15CON</name>
<address>0x15c</address>
</instance>
<register>
<field>
<name>RESERVED31_14</name>
<position>14</position>
<width>18</width>
</field>
<field>
<name>TXSTALL_AUTOCLR</name>
<position>13</position>
</field>
<field>
<name>TX_CF_INTE</name>
<position>12</position>
</field>
<field>
<name>TXENDP_NUM</name>
<position>8</position>
<width>4</width>
</field>
<field>
<name>RESERVED7</name>
<position>7</position>
</field>
<field>
<name>TXACKINTEN</name>
<position>6</position>
</field>
<field>
<name>TXERRINTEN</name>
<position>5</position>
</field>
<field>
<name>TXVOIDINTEN</name>
<position>4</position>
</field>
<field>
<name>TXEPEN</name>
<position>3</position>
</field>
<field>
<name>TXNAK</name>
<position>2</position>
</field>
<field>
<name>TXSTALL</name>
<position>1</position>
</field>
<field>
<name>TXCLR</name>
<position>0</position>
</field>
</register>
</node>
<node>
<name>TX_INT_BUF</name>
<instance>
<name>TX3BUF</name>
<address>0x80</address>
</instance>
<instance>
<name>TX6BUF</name>
<address>0xb8</address>
</instance>
<instance>
<name>TX9BUF</name>
<address>0xf0</address>
</instance>
<instance>
<name>TX12BUF</name>
<address>0x128</address>
</instance>
<instance>
<name>TX15BUF</name>
<address>0x160</address>
</instance>
<register>
<field>
<name>RESERVED31_2</name>
<position>2</position>
<width>30</width>
</field>
<field>
<name>TXURF</name>
<position>1</position>
</field>
<field>
<name>TXFULL</name>
<position>0</position>
</field>
</register>
</node>
<node>
<name>TX_INT_DMAINCTL</name>
<instance>
<name>TX3DMAINCTL</name>
<address>0x84</address>
</instance>
<instance>
<name>TX6DMAINCTL</name>
<address>0xbc</address>
</instance>
<instance>
<name>TX9DMAINCTL</name>
<address>0xf4</address>
</instance>
<instance>
<name>TX12DMAINCTL</name>
<address>0x12c</address>
</instance>
<instance>
<name>TX15DMAINCTL</name>
<address>0x164</address>
</instance>
<register>
<field>
<name>RESERVED31_1</name>
<position>1</position>
<width>31</width>
</field>
<field>
<name>DMAINSTA</name>
<position>0</position>
</field>
</register>
</node>
<node>
<name>TX_INT_DMALM_IADDR</name>
<instance>
<name>TX3DMALM_IADDR</name>
<address>0x88</address>
</instance>
<instance>
<name>TX6DMALM_IADDR</name>
<address>0xc0</address>
</instance>
<instance>
<name>TX9DMALM_IADDR</name>
<address>0xf8</address>
</instance>
<instance>
<name>TX12DMALM_IADDR</name>
<address>0x130</address>
</instance>
<instance>
<name>TX15DMALM_IADDR</name>
<address>0x168</address>
</instance>
<register>
<field>
<name>LMINADDR</name>
<desc>DMA word aligned buffer address</desc>
<position>0</position>
<width>32</width>
</field>
</register>
</node>
</node>
<node>
<name>UHC</name>
<title>USB 2.0 Host Controller</title>
<desc>USB 2.0 Host Controller</desc>
<instance>
<name>UHC</name>
<address>0x180a4000</address>
</instance>
</node>
<node>
<name>SDRSTMC</name>
<title>SDRSTMC Static/SDRAM Memory Controller</title>
<desc>SDRSTMC Static/SDRAM Memory Controller</desc>
<instance>
<name>SDRSTMC</name>
<address>0x180b0000</address>
</instance>
<node>
<name>MCSDR_MODE</name>
<instance>
<name>MCSDR_MODE</name>
<address>0x100</address>
</instance>
<register/>
</node>
<node>
<name>MCSDR_ADDMAP</name>
<instance>
<name>MCSDR_ADDMAP</name>
<address>0x104</address>
</instance>
<register/>
</node>
<node>
<name>MCSDR_ADDCFG</name>
<instance>
<name>MCSDR_ADDCFG</name>
<address>0x108</address>
</instance>
<register/>
</node>
<node>
<name>MCSDR_BASIC</name>
<instance>
<name>MCSDR_BASIC</name>
<address>0x10c</address>
</instance>
<register/>
</node>
<node>
<name>MCSDR_T_REF</name>
<instance>
<name>MCSDR_T_REF</name>
<address>0x110</address>
</instance>
<register/>
</node>
<node>
<name>MCSDR_T_RFC</name>
<instance>
<name>MCSDR_T_RFC</name>
<address>0x114</address>
</instance>
<register/>
</node>
<node>
<name>MCSDR_T_MRD</name>
<instance>
<name>MCSDR_T_MRD</name>
<address>0x118</address>
</instance>
<register/>
</node>
<node>
<name>MCSDR_T_RP</name>
<instance>
<name>MCSDR_T_RP</name>
<address>0x120</address>
</instance>
<register/>
</node>
<node>
<name>MCSDR_T_RCD</name>
<instance>
<name>MCSDR_T_RCD</name>
<address>0x124</address>
</instance>
<register/>
</node>
<node>
<name>MCST0_T_CEWD</name>
<instance>
<name>MCST0_T_CEWD</name>
<address>0x200</address>
</instance>
<register/>
</node>
<node>
<name>MCST0_T_CE2WE</name>
<instance>
<name>MCST0_T_CE2WE</name>
<address>0x204</address>
</instance>
<register/>
</node>
<node>
<name>MCST0_WEWD</name>
<instance>
<name>MCST0_WEWD</name>
<address>0x208</address>
</instance>
<register/>
</node>
<node>
<name>MCST0_T_WE2CE</name>
<instance>
<name>MCST0_T_WE2CE</name>
<address>0x20c</address>
</instance>
<register/>
</node>
<node>
<name>MCST0_T_CEWDR</name>
<instance>
<name>MCST0_T_CEWDR</name>
<address>0x210</address>
</instance>
<register/>
</node>
<node>
<name>MCST0_T_CE2RD</name>
<instance>
<name>MCST0_T_CE2RD</name>
<address>0x214</address>
</instance>
<register/>
</node>
<node>
<name>MCST0_T_RDWD</name>
<instance>
<name>MCST0_T_RDWD</name>
<address>0x218</address>
</instance>
<register/>
</node>
<node>
<name>MCST0_T_RD2CE</name>
<instance>
<name>MCST0_T_RD2CE</name>
<address>0x21c</address>
</instance>
<register/>
</node>
<node>
<name>MCST0_BASIC</name>
<instance>
<name>MCST0_BASIC</name>
<address>0x220</address>
</instance>
<register/>
</node>
<node>
<name>MCST1_T_CEWD</name>
<instance>
<name>MCST1_T_CEWD</name>
<address>0x300</address>
</instance>
<register/>
</node>
<node>
<name>MCST1_T_CE2WE</name>
<instance>
<name>MCST1_T_CE2WE</name>
<address>0x304</address>
</instance>
<register/>
</node>
<node>
<name>MCST1_WEWD</name>
<instance>
<name>MCST1_WEWD</name>
<address>0x308</address>
</instance>
<register/>
</node>
<node>
<name>MCST1_T_WE2CE</name>
<instance>
<name>MCST1_T_WE2CE</name>
<address>0x30c</address>
</instance>
<register/>
</node>
<node>
<name>MCST1_T_CEWDR</name>
<instance>
<name>MCST1_T_CEWDR</name>
<address>0x310</address>
</instance>
<register/>
</node>
<node>
<name>MCST1_T_CE2RD</name>
<instance>
<name>MCST1_T_CE2RD</name>
<address>0x314</address>
</instance>
<register/>
</node>
<node>
<name>MCST1_T_RDWD</name>
<instance>
<name>MCST1_T_RDWD</name>
<address>0x318</address>
</instance>
<register/>
</node>
<node>
<name>MCST1_T_RD2CE</name>
<instance>
<name>MCST1_T_RD2CE</name>
<address>0x31c</address>
</instance>
<register/>
</node>
<node>
<name>MCST1_BASIC</name>
<instance>
<name>MCST1_BASIC</name>
<address>0x320</address>
</instance>
<register/>
</node>
</node>
<node>
<name>VIP</name>
<title>VIP Video Input Processor</title>
<desc>VIP Video Input Processor</desc>
<instance>
<name>VIP</name>
<address>0x180c0000</address>
</instance>
</node>
<node>
<name>NANDC</name>
<title>NAND Flash Controller</title>
<desc>NAND Flash Controller</desc>
<instance>
<name>NANDC</name>
<address>0x180e8000</address>
</instance>
<node>
<name>FMCTL</name>
<instance>
<name>FMCTL</name>
<address>0x0</address>
</instance>
<register/>
</node>
<node>
<name>FMWAIT</name>
<instance>
<name>FMWAIT</name>
<address>0x4</address>
</instance>
<register/>
</node>
<node>
<name>FLCTL</name>
<instance>
<name>FLCTL</name>
<address>0x8</address>
</instance>
<register/>
</node>
<node>
<name>BCHCTL</name>
<instance>
<name>BCHCTL</name>
<address>0xc</address>
</instance>
<register/>
</node>
<node>
<name>BCHST</name>
<instance>
<name>BCHST</name>
<address>0xd0</address>
</instance>
<register/>
</node>
<node>
<name>FLASH_DATAn</name>
<instance>
<name>FLASH_DATAn</name>
<range>
<first>0</first>
<count>4</count>
<base>0x200</base>
<stride>0x200</stride>
</range>
</instance>
<register/>
</node>
<node>
<name>ADDRn</name>
<instance>
<name>ADDRn</name>
<range>
<first>0</first>
<count>4</count>
<base>0x204</base>
<stride>0x200</stride>
</range>
</instance>
<register/>
</node>
<node>
<name>FLASH_CMDn</name>
<instance>
<name>FLASH_CMDn</name>
<range>
<first>0</first>
<count>4</count>
<base>0x208</base>
<stride>0x200</stride>
</range>
</instance>
<register/>
</node>
<node>
<name>PAGE_BUF</name>
<instance>
<name>PAGE_BUF</name>
<address>0xa00</address>
</instance>
<register/>
</node>
<node>
<name>SPARE_BUF</name>
<instance>
<name>SPARE_BUF</name>
<address>0x1200</address>
</instance>
<register/>
</node>
</node>
<node>
<name>LCDC</name>
<title>LCD Interface Controller</title>
<desc>LCD Interface Controller</desc>
<instance>
<name>LCDC</name>
<address>0x186e8000</address>
</instance>
<node>
<name>LCDC_CTRL</name>
<instance>
<name>LCDC_CTRL</name>
<address>0x0</address>
</instance>
<register>
<field>
<name>RESERVED15_14</name>
<position>14</position>
<width>2</width>
</field>
<field>
<name>ALPHA_24B</name>
<position>13</position>
</field>
<field>
<name>UVBUFEXCH</name>
<position>12</position>
</field>
<field>
<name>ALPHA</name>
<position>9</position>
<width>3</width>
</field>
<field>
<name>YMIX</name>
<position>8</position>
</field>
<field>
<name>MCU</name>
<position>7</position>
</field>
<field>
<name>RGB24B</name>
<position>6</position>
</field>
<field>
<name>START_EVEN</name>
<position>5</position>
</field>
<field>
<name>EVEN_EN</name>
<position>4</position>
</field>
<field>
<name>RGB_DUMMY</name>
<position>2</position>
<width>2</width>
<enum>
<name>PARALLEL</name>
<value>0x0</value>
</enum>
<enum>
<name>RESERVED</name>
<value>0x1</value>
</enum>
<enum>
<name>SERIAL_UPS501</name>
<value>0x2</value>
</enum>
<enum>
<name>SERIAL_UPS502</name>
<value>0x3</value>
</enum>
</field>
<field>
<name>ENABLE</name>
<position>1</position>
<enum>
<name>DISABLE</name>
<value>0x0</value>
</enum>
<enum>
<name>ENABLE</name>
<value>0x1</value>
</enum>
</field>
<field>
<name>STOP</name>
<position>0</position>
</field>
</register>
</node>
<node>
<name>MCU_CTRL</name>
<instance>
<name>MCU_CTRL</name>
<address>0x4</address>
</instance>
<register>
<field>
<name>RESERVED15</name>
<position>15</position>
</field>
<field>
<name>ALPHA_BASE</name>
<position>8</position>
<width>7</width>
</field>
<field>
<name>RESERVED1</name>
<position>7</position>
</field>
<field>
<name>ALPHA_BUF_EN</name>
<position>6</position>
</field>
<field>
<name>LCD_RS</name>
<position>5</position>
</field>
<field>
<name>RESERVED0</name>
<position>2</position>
<width>3</width>
</field>
<field>
<name>BUFF_START</name>
<position>1</position>
</field>
<field>
<name>BYPASS</name>
<position>0</position>
</field>
</register>
</node>
<node>
<name>HOR_PERIOD</name>
<instance>
<name>HOR_PERIOD</name>
<address>0x8</address>
</instance>
<register/>
</node>
<node>
<name>VERT_PERIOD</name>
<instance>
<name>VERT_PERIOD</name>
<address>0xc</address>
</instance>
<register/>
</node>
<node>
<name>HOR_PW</name>
<instance>
<name>HOR_PW</name>
<address>0x10</address>
</instance>
<register/>
</node>
<node>
<name>VERT_PW</name>
<instance>
<name>VERT_PW</name>
<address>0x14</address>
</instance>
<register/>
</node>
<node>
<name>HOR_BP</name>
<instance>
<name>HOR_BP</name>
<address>0x18</address>
</instance>
<register/>
</node>
<node>
<name>VERT_BP</name>
<instance>
<name>VERT_BP</name>
<address>0x1c</address>
</instance>
<register/>
</node>
<node>
<name>HOR_ACT</name>
<instance>
<name>HOR_ACT</name>
<address>0x20</address>
</instance>
<register/>
</node>
<node>
<name>VERT_ACT</name>
<instance>
<name>VERT_ACT</name>
<address>0x24</address>
</instance>
<register/>
</node>
<node>
<name>LINE0_YADDR</name>
<instance>
<name>LINE0_YADDR</name>
<address>0x28</address>
</instance>
<register/>
</node>
<node>
<name>LINE0_UVADDR</name>
<instance>
<name>LINE0_UVADDR</name>
<address>0x2c</address>
</instance>
<register/>
</node>
<node>
<name>LINE1_YADDR</name>
<instance>
<name>LINE1_YADDR</name>
<address>0x30</address>
</instance>
<register/>
</node>
<node>
<name>LINE1_UVADDR</name>
<instance>
<name>LINE1_UVADDR</name>
<address>0x34</address>
</instance>
<register/>
</node>
<node>
<name>LINE2_YADDR</name>
<instance>
<name>LINE2_YADDR</name>
<address>0x38</address>
</instance>
<register/>
</node>
<node>
<name>LINE2_UVADDR</name>
<instance>
<name>LINE2_UVADDR</name>
<address>0x3c</address>
</instance>
<register/>
</node>
<node>
<name>LINE3_YADDR</name>
<instance>
<name>LINE3_YADDR</name>
<address>0x40</address>
</instance>
<register/>
</node>
<node>
<name>LINE3_UVADDR</name>
<instance>
<name>LINE3_UVADDR</name>
<address>0x44</address>
</instance>
<register/>
</node>
<node>
<name>START_X</name>
<instance>
<name>START_X</name>
<address>0x48</address>
</instance>
<register/>
</node>
<node>
<name>START_Y</name>
<instance>
<name>START_Y</name>
<address>0x4c</address>
</instance>
<register/>
</node>
<node>
<name>DELTA_X</name>
<instance>
<name>DELTA_X</name>
<address>0x50</address>
</instance>
<register/>
</node>
<node>
<name>DELTA_Y</name>
<instance>
<name>DELTA_Y</name>
<address>0x54</address>
</instance>
<register/>
</node>
<node>
<name>LCDC_INTR_MASK</name>
<instance>
<name>LCDC_INTR_MASK</name>
<address>0x58</address>
</instance>
<register/>
</node>
<node>
<name>ALPHA_ALX</name>
<instance>
<name>ALPHA_ALX</name>
<address>0x5c</address>
</instance>
<register/>
</node>
<node>
<name>ALPHA_ATY</name>
<instance>
<name>ALPHA_ATY</name>
<address>0x60</address>
</instance>
<register/>
</node>
<node>
<name>ALPHA_ARX</name>
<instance>
<name>ALPHA_ARX</name>
<address>0x64</address>
</instance>
<register/>
</node>
<node>
<name>ALPHA_ABY</name>
<instance>
<name>ALPHA_ABY</name>
<address>0x68</address>
</instance>
<register/>
</node>
<node>
<name>ALPHA_BLX</name>
<instance>
<name>ALPHA_BLX</name>
<address>0x6c</address>
</instance>
<register/>
</node>
<node>
<name>ALPHA_BTY</name>
<instance>
<name>ALPHA_BTY</name>
<address>0x70</address>
</instance>
<register/>
</node>
<node>
<name>ALPHA_BRX</name>
<instance>
<name>ALPHA_BRX</name>
<address>0x74</address>
</instance>
<register/>
</node>
<node>
<name>ALPHA_BBY</name>
<instance>
<name>ALPHA_BBY</name>
<address>0x78</address>
</instance>
<register/>
</node>
<node>
<name>LCDC_STA</name>
<instance>
<name>LCDC_STA</name>
<address>0x7c</address>
</instance>
<register/>
</node>
<node>
<name>LCD_COMMAND</name>
<instance>
<name>LCD_COMMAND</name>
<address>0x1000</address>
</instance>
<register/>
</node>
<node>
<name>LCD_DATA</name>
<instance>
<name>LCD_DATA</name>
<address>0x1004</address>
</instance>
<register/>
</node>
<node>
<name>LCD_BUFF</name>
<instance>
<name>LCD_BUFF</name>
<address>0x2000</address>
</instance>
<register/>
</node>
</node>
<node>
<name>HSADC</name>
<title>High Speed ADC</title>
<desc>High Speed ADC</desc>
<instance>
<name>HSADC</name>
<address>0x186ec000</address>
</instance>
<node>
<name>DATA</name>
<instance>
<name>DATA</name>
<address>0x0</address>
</instance>
<register/>
</node>
<node>
<name>CTRL</name>
<instance>
<name>CTRL</name>
<address>0x4</address>
</instance>
<register/>
</node>
<node>
<name>IER</name>
<instance>
<name>IER</name>
<address>0x8</address>
</instance>
<register/>
</node>
<node>
<name>ISR</name>
<instance>
<name>ISR</name>
<address>0xc</address>
</instance>
<register/>
</node>
</node>
<node>
<name>DWDMA</name>
<title>DMA Controller</title>
<desc>DMA Controller</desc>
<instance>
<name>DWDMA</name>
<address>0x186f0000</address>
</instance>
<node>
<name>DWDMA_SARn</name>
<instance>
<name>DWDMA_SARn</name>
<range>
<first>0</first>
<count>4</count>
<base>0x0</base>
<stride>0x58</stride>
</range>
</instance>
<register>
<desc>Source address register</desc>
</register>
</node>
<node>
<name>DWDMA_DARn</name>
<instance>
<name>DWDMA_DARn</name>
<range>
<first>0</first>
<count>4</count>
<base>0x8</base>
<stride>0x58</stride>
</range>
</instance>
<register>
<desc>Destination address register</desc>
</register>
</node>
<node>
<name>DWDMA_LLPn</name>
<instance>
<name>DWDMA_LLPn</name>
<range>
<first>0</first>
<count>4</count>
<base>0x10</base>
<stride>0x58</stride>
</range>
</instance>
<register>
<desc>Linked List pointer register</desc>
</register>
</node>
<node>
<name>DWDMA_CTL_Ln</name>
<instance>
<name>DWDMA_CTL_Ln</name>
<range>
<first>0</first>
<count>4</count>
<base>0x18</base>
<stride>0x58</stride>
</range>
</instance>
<register>
<field>
<name>RESERVED31_29</name>
<position>29</position>
<width>3</width>
</field>
<field>
<name>LLP_SRC_EN</name>
<position>28</position>
</field>
<field>
<name>LLP_DST_EN</name>
<position>27</position>
</field>
<field>
<name>SMS</name>
<position>25</position>
<width>2</width>
</field>
<field>
<name>DMS</name>
<position>23</position>
<width>2</width>
</field>
<field>
<name>TT_FC</name>
<position>20</position>
<width>3</width>
<enum>
<name>MEM2MEM_DWDMA</name>
<desc>flow controller DWDMA_AHB_DMAC</desc>
<value>0x0</value>
</enum>
<enum>
<name>MEM2PERI_DWDMA</name>
<desc>flow controller DWDMA_AHB_DMAC</desc>
<value>0x1</value>
</enum>
<enum>
<name>PERI2MEM_DWDMA</name>
<desc>flow controller DWDMA_AHB_DMAC</desc>
<value>0x2</value>
</enum>
<enum>
<name>PERI2PERI_DWDMA</name>
<desc>flow controller DWDMA_AHB_DMAC</desc>
<value>0x3</value>
</enum>
<enum>
<name>PERI2MEM_PERI</name>
<desc>flow controller Peripheral</desc>
<value>0x4</value>
</enum>
<enum>
<name>PERI2PERI_SRC_PERI</name>
<desc>flow controller Source Peripheral</desc>
<value>0x5</value>
</enum>
<enum>
<name>MEM2PERI_PERI</name>
<desc>flow controller Peripheral</desc>
<value>0x6</value>
</enum>
<enum>
<name>PERI2PERI_DST_PERI</name>
<desc>flow controller Destination Peripheral</desc>
<value>0x7</value>
</enum>
</field>
<field>
<name>RESERVED19</name>
<position>19</position>
</field>
<field>
<name>DST_SCATTER_EN</name>
<position>18</position>
</field>
<field>
<name>SRC_GATHER_EN</name>
<position>17</position>
</field>
<field>
<name>SRC_MSIZE</name>
<desc>Number of data items to be transferred (of width CTLx.SRC_TR_WIDTH or CTLx.DST_TR_WIDTH)
</desc>
<position>14</position>
<width>3</width>
<enum>
<name>1</name>
<value>0x0</value>
</enum>
<enum>
<name>4</name>
<value>0x1</value>
</enum>
<enum>
<name>8</name>
<value>0x2</value>
</enum>
<enum>
<name>16</name>
<value>0x3</value>
</enum>
<enum>
<name>32</name>
<value>0x4</value>
</enum>
</field>
<field>
<name>DST_MSIZE</name>
<position>11</position>
<width>3</width>
<enum>
<name>1</name>
<value>0x0</value>
</enum>
<enum>
<name>4</name>
<value>0x1</value>
</enum>
<enum>
<name>8</name>
<value>0x2</value>
</enum>
<enum>
<name>16</name>
<value>0x3</value>
</enum>
<enum>
<name>32</name>
<value>0x4</value>
</enum>
</field>
<field>
<name>SINC</name>
<desc>Source Address Increment.</desc>
<position>9</position>
<width>2</width>
<enum>
<name>INCREMENT</name>
<value>0x0</value>
</enum>
<enum>
<name>DECREMENT</name>
<value>0x1</value>
</enum>
<enum>
<name>FIXED2</name>
<value>0x2</value>
</enum>
<enum>
<name>FIXED3</name>
<value>0x3</value>
</enum>
</field>
<field>
<name>DINC</name>
<position>7</position>
<width>2</width>
<enum>
<name>INCREMENT</name>
<value>0x0</value>
</enum>
<enum>
<name>DECREMENT</name>
<value>0x1</value>
</enum>
<enum>
<name>FIXED2</name>
<value>0x2</value>
</enum>
<enum>
<name>FIXED3</name>
<value>0x3</value>
</enum>
</field>
<field>
<name>SRC_TR_WIDTH</name>
<position>4</position>
<width>3</width>
<enum>
<name>BYTE</name>
<value>0x0</value>
</enum>
<enum>
<name>HALFWORD</name>
<value>0x1</value>
</enum>
<enum>
<name>WORD</name>
<value>0x2</value>
</enum>
</field>
<field>
<name>DST_TR_WIDTH</name>
<position>1</position>
<width>3</width>
<enum>
<name>BYTE</name>
<value>0x0</value>
</enum>
<enum>
<name>HALFWORD</name>
<value>0x1</value>
</enum>
<enum>
<name>WORD</name>
<value>0x2</value>
</enum>
</field>
<field>
<name>INT_EN</name>
<position>0</position>
</field>
</register>
</node>
<node>
<name>DWDMA_CTL_Hn</name>
<instance>
<name>DWDMA_CTL_Hn</name>
<range>
<first>0</first>
<count>4</count>
<base>0x1c</base>
<stride>0x58</stride>
</range>
</instance>
<register>
<field>
<name>RESERVED31_13</name>
<position>13</position>
<width>19</width>
</field>
<field>
<name>DONE</name>
<position>12</position>
</field>
<field>
<name>BLOCK_TS</name>
<position>0</position>
<width>12</width>
</field>
</register>
</node>
<node>
<name>DWDMA_SSTATn</name>
<instance>
<name>DWDMA_SSTATn</name>
<range>
<first>0</first>
<count>4</count>
<base>0x20</base>
<stride>0x58</stride>
</range>
</instance>
<register/>
</node>
<node>
<name>DWDMA_DSTATn</name>
<instance>
<name>DWDMA_DSTATn</name>
<range>
<first>0</first>
<count>4</count>
<base>0x28</base>
<stride>0x58</stride>
</range>
</instance>
<register/>
</node>
<node>
<name>DWDMA_SSTATARn</name>
<instance>
<name>DWDMA_SSTATARn</name>
<range>
<first>0</first>
<count>4</count>
<base>0x30</base>
<stride>0x58</stride>
</range>
</instance>
<register/>
</node>
<node>
<name>DWDMA_DSTATARn</name>
<instance>
<name>DWDMA_DSTATARn</name>
<range>
<first>0</first>
<count>4</count>
<base>0x38</base>
<stride>0x58</stride>
</range>
</instance>
<register/>
</node>
<node>
<name>DWDMA_CFG_Ln</name>
<instance>
<name>DWDMA_CFG_Ln</name>
<range>
<first>0</first>
<count>4</count>
<base>0x40</base>
<stride>0x58</stride>
</range>
</instance>
<register>
<field>
<name>RELOAD_DST</name>
<position>31</position>
</field>
<field>
<name>RELOAD_SRC</name>
<position>30</position>
</field>
<field>
<name>MAX_ABRST</name>
<position>20</position>
<width>10</width>
</field>
<field>
<name>SRC_HS_POL</name>
<desc>Source Handshaking Interface Polarity.</desc>
<position>19</position>
<enum>
<name>ACTIVE_HIGH</name>
<value>0x0</value>
</enum>
<enum>
<name>ACTIVE_LOW</name>
<value>0x1</value>
</enum>
</field>
<field>
<name>DST_HS_POL</name>
<desc>Destination Handshaking Interface Polarity.</desc>
<position>18</position>
<enum>
<name>ACTIVE_HIGH</name>
<value>0x0</value>
</enum>
<enum>
<name>ACTIVE_LOW</name>
<value>0x1</value>
</enum>
</field>
<field>
<name>LOCK_B</name>
<position>17</position>
</field>
<field>
<name>LOCK_CH</name>
<position>16</position>
</field>
<field>
<name>LOCK_B_L</name>
<position>14</position>
<width>2</width>
</field>
<field>
<name>LOCK_CH_L</name>
<position>12</position>
<width>2</width>
</field>
<field>
<name>HS_SEL_SRC</name>
<position>11</position>
<enum>
<name>HW</name>
<value>0x0</value>
</enum>
<enum>
<name>SW</name>
<value>0x1</value>
</enum>
</field>
<field>
<name>HS_SEL_DST</name>
<position>10</position>
<enum>
<name>HW</name>
<value>0x0</value>
</enum>
<enum>
<name>SW</name>
<value>0x1</value>
</enum>
</field>
<field>
<name>FIFO_EMPTY</name>
<desc>Indicates if there is data left in the channel FIFO.</desc>
<position>9</position>
<enum>
<name>NOT_EMPTY</name>
<value>0x0</value>
</enum>
<enum>
<name>EMPTY</name>
<value>0x1</value>
</enum>
</field>
<field>
<name>CH_SUSP</name>
<position>8</position>
<enum>
<name>SUSPEND</name>
<value>0x1</value>
</enum>
</field>
<field>
<name>CH_PRIOR</name>
<desc>Channel priority. A priority of 7 is the highest priority, and 0 is the lowest.
</desc>
<position>5</position>
<width>3</width>
</field>
<field>
<name>RESERVED4_0</name>
<position>0</position>
<width>5</width>
</field>
</register>
</node>
<node>
<name>DWDMA_CFG_Hn</name>
<instance>
<name>DWDMA_CFG_Hn</name>
<range>
<first>0</first>
<count>4</count>
<base>0x44</base>
<stride>0x58</stride>
</range>
</instance>
<register/>
</node>
<node>
<name>DWDMA_SGRn</name>
<instance>
<name>DWDMA_SGRn</name>
<range>
<first>0</first>
<count>4</count>
<base>0x48</base>
<stride>0x58</stride>
</range>
</instance>
<register>
<desc>Source Gather Register</desc>
</register>
</node>
<node>
<name>DWDMA_DSRn</name>
<instance>
<name>DWDMA_DSRn</name>
<range>
<first>0</first>
<count>4</count>
<base>0x50</base>
<stride>0x58</stride>
</range>
</instance>
<register/>
</node>
<node>
<name>RAW_TFR</name>
<instance>
<name>RAW_TFR</name>
<address>0x2c0</address>
</instance>
<register/>
</node>
<node>
<name>RAW_BLOCK</name>
<instance>
<name>RAW_BLOCK</name>
<address>0x2c8</address>
</instance>
<register/>
</node>
<node>
<name>RAW_SRCTRAN</name>
<instance>
<name>RAW_SRCTRAN</name>
<address>0x2d0</address>
</instance>
<register/>
</node>
<node>
<name>RAW_DSTTRAN</name>
<instance>
<name>RAW_DSTTRAN</name>
<address>0x2d8</address>
</instance>
<register/>
</node>
<node>
<name>RAW_ERR</name>
<instance>
<name>RAW_ERR</name>
<address>0x2e0</address>
</instance>
<register/>
</node>
<node>
<name>STATUS_TFR</name>
<instance>
<name>STATUS_TFR</name>
<address>0x2e8</address>
</instance>
<register/>
</node>
<node>
<name>STATUS_BLOCK</name>
<instance>
<name>STATUS_BLOCK</name>
<address>0x2f0</address>
</instance>
<register/>
</node>
<node>
<name>STATUS_SRCTRAN</name>
<instance>
<name>STATUS_SRCTRAN</name>
<address>0x2f8</address>
</instance>
<register/>
</node>
<node>
<name>STATUS_DSTTRAN</name>
<instance>
<name>STATUS_DSTTRAN</name>
<address>0x300</address>
</instance>
<register/>
</node>
<node>
<name>STATUS_ERR</name>
<instance>
<name>STATUS_ERR</name>
<address>0x308</address>
</instance>
<register/>
</node>
<node>
<name>MASK_TFR</name>
<instance>
<name>MASK_TFR</name>
<address>0x310</address>
</instance>
<register/>
</node>
<node>
<name>MASK_BLOCK</name>
<instance>
<name>MASK_BLOCK</name>
<address>0x318</address>
</instance>
<register/>
</node>
<node>
<name>MASK_SRCTRAN</name>
<instance>
<name>MASK_SRCTRAN</name>
<address>0x320</address>
</instance>
<register/>
</node>
<node>
<name>MASK_DSTTRAN</name>
<instance>
<name>MASK_DSTTRAN</name>
<address>0x328</address>
</instance>
<register/>
</node>
<node>
<name>MASK_ERR</name>
<instance>
<name>MASK_ERR</name>
<address>0x330</address>
</instance>
<register/>
</node>
<node>
<name>CLEAR_TFR</name>
<instance>
<name>CLEAR_TFR</name>
<address>0x338</address>
</instance>
<register/>
</node>
<node>
<name>CLEAR_BLOCK</name>
<instance>
<name>CLEAR_BLOCK</name>
<address>0x340</address>
</instance>
<register/>
</node>
<node>
<name>CLEAR_SRCTRAN</name>
<instance>
<name>CLEAR_SRCTRAN</name>
<address>0x348</address>
</instance>
<register/>
</node>
<node>
<name>CLEAR_DSTTRAN</name>
<instance>
<name>CLEAR_DSTTRAN</name>
<address>0x350</address>
</instance>
<register/>
</node>
<node>
<name>CLEAR_ERR</name>
<instance>
<name>CLEAR_ERR</name>
<address>0x358</address>
</instance>
<register/>
</node>
<node>
<name>STATUS_INT</name>
<instance>
<name>STATUS_INT</name>
<address>0x360</address>
</instance>
<register/>
</node>
<node>
<name>REQ_SRC</name>
<instance>
<name>REQ_SRC</name>
<address>0x368</address>
</instance>
<register/>
</node>
<node>
<name>REQ_DST</name>
<instance>
<name>REQ_DST</name>
<address>0x370</address>
</instance>
<register/>
</node>
<node>
<name>S_REQ_SRC</name>
<instance>
<name>S_REQ_SRC</name>
<address>0x378</address>
</instance>
<register/>
</node>
<node>
<name>S_REQ_DST</name>
<instance>
<name>S_REQ_DST</name>
<address>0x380</address>
</instance>
<register/>
</node>
<node>
<name>L_REQ_SRC</name>
<instance>
<name>L_REQ_SRC</name>
<address>0x388</address>
</instance>
<register/>
</node>
<node>
<name>L_REQ_DST</name>
<instance>
<name>L_REQ_DST</name>
<address>0x390</address>
</instance>
<register/>
</node>
<node>
<name>DMA_CFG</name>
<instance>
<name>DMA_CFG</name>
<address>0x398</address>
</instance>
<register>
<field>
<name>RESERVED31_1</name>
<position>1</position>
<width>31</width>
</field>
<field>
<name>DMA_EN</name>
<desc>Global DMA enable.</desc>
<position>0</position>
<enum>
<name>DISABLE</name>
<value>0x0</value>
</enum>
<enum>
<name>ENABLE</name>
<value>0x1</value>
</enum>
</field>
</register>
</node>
<node>
<name>DMA_CHEN</name>
<instance>
<name>DMA_CHEN</name>
<address>0x3a0</address>
</instance>
<register>
<desc>Channel enable register.</desc>
<field>
<name>RESERVED_31_12</name>
<position>12</position>
<width>20</width>
</field>
<field>
<name>CHANNEL_EN_WR_EN</name>
<desc>Channel enable write enable.</desc>
<position>8</position>
<width>4</width>
<enum>
<name>CH0_EN_WR_EN</name>
<value>0x1</value>
</enum>
<enum>
<name>CH1_EN_WR_EN</name>
<value>0x2</value>
</enum>
<enum>
<name>CH2_EN_WR_EN</name>
<value>0x4</value>
</enum>
<enum>
<name>CH3_EN_WR_EN</name>
<value>0x8</value>
</enum>
</field>
<field>
<name>RESERVED7_4</name>
<position>4</position>
<width>4</width>
</field>
<field>
<name>CHANNEL_EN</name>
<position>0</position>
<width>4</width>
<enum>
<name>CH0_EN</name>
<value>0x1</value>
</enum>
<enum>
<name>CH1_EN</name>
<value>0x2</value>
</enum>
<enum>
<name>CH2_EN</name>
<value>0x4</value>
</enum>
<enum>
<name>CH3_EN</name>
<value>0x8</value>
</enum>
</field>
</register>
</node>
</node>
<node>
<name>CACHE</name>
<title>CACHE Controller</title>
<desc>CACHE Controller</desc>
<instance>
<name>CACHE</name>
<address>0xefff0000</address>
</instance>
<node>
<name>DEVID</name>
<instance>
<name>DEVID</name>
<address>0x0</address>
</instance>
<register>
<field>
<name>CACHE_EN</name>
<position>31</position>
</field>
</register>
</node>
<node>
<name>CACHEOP</name>
<instance>
<name>CACHEOP</name>
<address>0x4</address>
</instance>
<register>
<field>
<name>ADDRESS</name>
<position>2</position>
<width>30</width>
</field>
<field>
<name>OPCODE</name>
<position>0</position>
<width>2</width>
<enum>
<name>NOP</name>
<value>0x0</value>
</enum>
<enum>
<name>INVALIDATE_SINGLE_ENTRY</name>
<value>0x1</value>
</enum>
<enum>
<name>INVALIDATE_WAY</name>
<value>0x2</value>
</enum>
</field>
</register>
</node>
<node>
<name>CACHELKDN</name>
<instance>
<name>CACHELKDN</name>
<address>0x8</address>
</instance>
<register>
<field>
<name>RESERVED31_2</name>
<position>2</position>
<width>30</width>
</field>
<field>
<name>WAY_SELECT</name>
<position>0</position>
<width>2</width>
<enum>
<name>LOCK_NONE</name>
<value>0x0</value>
</enum>
<enum>
<name>LOCK_WAY0</name>
<value>0x1</value>
</enum>
<enum>
<name>LOCK_WAY1</name>
<value>0x2</value>
</enum>
</field>
</register>
</node>
<node>
<name>MEMMAPA</name>
<instance>
<name>MEMMAPA</name>
<address>0x10</address>
</instance>
<register>
<field>
<name>MEMBASE</name>
<position>25</position>
<width>7</width>
</field>
<field>
<name>MAPSIZE</name>
<position>0</position>
<width>8</width>
<enum>
<name>MAP_128MB</name>
<value>0xf8</value>
</enum>
<enum>
<name>MAP_64MB</name>
<value>0xfc</value>
</enum>
<enum>
<name>MAP_32MB</name>
<value>0xfe</value>
</enum>
</field>
</register>
</node>
<node>
<name>MEMMAPB</name>
<instance>
<name>MEMMAPB</name>
<address>0x14</address>
</instance>
<register>
<field>
<name>MEMBASE</name>
<position>25</position>
<width>7</width>
</field>
<field>
<name>MAPSIZE</name>
<position>0</position>
<width>8</width>
<enum>
<name>MAP_128MB</name>
<value>0xf8</value>
</enum>
<enum>
<name>MAP_64MB</name>
<value>0xfc</value>
</enum>
<enum>
<name>MAP_32MB</name>
<value>0xfe</value>
</enum>
</field>
</register>
</node>
<node>
<name>MEMMAPC</name>
<instance>
<name>MEMMAPC</name>
<address>0x18</address>
</instance>
<register>
<field>
<name>MEMBASE</name>
<position>25</position>
<width>7</width>
</field>
<field>
<name>MAPSIZE</name>
<position>0</position>
<width>8</width>
<enum>
<name>MAP_128MB</name>
<value>0xf8</value>
</enum>
<enum>
<name>MAP_64MB</name>
<value>0xfc</value>
</enum>
<enum>
<name>MAP_32MB</name>
<value>0xfe</value>
</enum>
</field>
</register>
</node>
<node>
<name>MEMMAPD</name>
<instance>
<name>MEMMAPD</name>
<address>0x1c</address>
</instance>
<register>
<field>
<name>MEMBASE</name>
<position>25</position>
<width>7</width>
</field>
<field>
<name>MAPSIZE</name>
<position>0</position>
<width>8</width>
<enum>
<name>MAP_128MB</name>
<value>0xf8</value>
</enum>
<enum>
<name>MAP_64MB</name>
<value>0xfc</value>
</enum>
<enum>
<name>MAP_32MB</name>
<value>0xfe</value>
</enum>
</field>
</register>
</node>
<node>
<name>PFCNTRA_CTRL</name>
<instance>
<name>PFCNTRA_CTRL</name>
<address>0x20</address>
</instance>
<register/>
</node>
<node>
<name>PFCNTRA</name>
<instance>
<name>PFCNTRA</name>
<address>0x24</address>
</instance>
<register/>
</node>
<node>
<name>PFCNTRB_CTRL</name>
<instance>
<name>PFCNTRB_CTRL</name>
<address>0x28</address>
</instance>
<register/>
</node>
<node>
<name>PFCNTRB</name>
<instance>
<name>PFCNTRB</name>
<address>0x2c</address>
</instance>
<register/>
</node>
</node>
<node>
<name>PWM</name>
<title>PWM timer</title>
<desc>PWM timer</desc>
<instance>
<name>PWM</name>
<range>
<first>1</first>
<address>0x1802c000</address>
<address>0x1802c010</address>
<address>0x1802c020</address>
<address>0x1802c030</address>
</range>
</instance>
<node>
<name>PWMTn_CNTR</name>
<instance>
<name>PWMTn_CNTR</name>
<address>0x0</address>
</instance>
<register>
<field>
<name>TC</name>
<desc>Main PWM counter. Range 0 - ((2^32)-1)</desc>
<position>0</position>
<width>32</width>
</field>
</register>
</node>
<node>
<name>PWMTn_HRC</name>
<instance>
<name>PWMTn_HRC</name>
<address>0x4</address>
</instance>
<register>
<field>
<name>HR</name>
<desc>Hight reference/capture register</desc>
<position>0</position>
<width>32</width>
</field>
</register>
</node>
<node>
<name>PWMTn_LRC</name>
<instance>
<name>PWMTn_LRC</name>
<address>0x8</address>
</instance>
<register>
<field>
<name>TR</name>
<desc>PWM total reference/capture register</desc>
<position>0</position>
<width>32</width>
</field>
</register>
</node>
<node>
<name>PWMTn_CTRL</name>
<instance>
<name>PWMTn_CTRL</name>
<address>0xc</address>
</instance>
<register>
<field>
<name>RESERVED31_13</name>
<position>13</position>
<width>19</width>
</field>
<field>
<name>PRESCALE</name>
<position>9</position>
<width>4</width>
<enum>
<name>1_2th</name>
<value>0x0</value>
</enum>
<enum>
<name>1_4th</name>
<value>0x1</value>
</enum>
<enum>
<name>1_8th</name>
<value>0x2</value>
</enum>
<enum>
<name>1_16th</name>
<value>0x3</value>
</enum>
<enum>
<name>1_32th</name>
<value>0x4</value>
</enum>
<enum>
<name>1_64th</name>
<value>0x5</value>
</enum>
<enum>
<name>1_128th</name>
<value>0x6</value>
</enum>
<enum>
<name>1_256th</name>
<value>0x7</value>
</enum>
<enum>
<name>1_512th</name>
<value>0x8</value>
</enum>
<enum>
<name>1_1024th</name>
<value>0x9</value>
</enum>
<enum>
<name>1_2048th</name>
<value>0xa</value>
</enum>
<enum>
<name>1_4096th</name>
<value>0xb</value>
</enum>
<enum>
<name>1_8192th</name>
<value>0xc</value>
</enum>
<enum>
<name>1_16384th</name>
<value>0xd</value>
</enum>
<enum>
<name>1_32768th</name>
<value>0xe</value>
</enum>
<enum>
<name>1_65536th</name>
<value>0xf</value>
</enum>
</field>
<field>
<name>CAPTURE_EN</name>
<desc>Capture mode enable</desc>
<position>8</position>
<enum>
<name>DISABLE</name>
<value>0x0</value>
</enum>
<enum>
<name>ENABLE</name>
<value>0x1</value>
</enum>
</field>
<field>
<name>PWM_RST</name>
<position>7</position>
<enum>
<name>RESET</name>
<value>0x1</value>
</enum>
</field>
<field>
<name>INT_STS</name>
<desc>Interrupt status and clear bit. Write 1 to clear interrupt flag.</desc>
<position>6</position>
</field>
<field>
<name>INT_EN</name>
<desc>PWM timer interrupt enable/disable. PWM timer will assert an interrupt when PWMTx_CNTR value is equal to the value of PWMTx_LRC or PWMTx_HRC.
</desc>
<position>5</position>
<enum>
<name>DISABLE</name>
<value>0x0</value>
</enum>
<enum>
<name>ENABLE</name>
<value>0x1</value>
</enum>
</field>
<field>
<name>SINGLE_MOD</name>
<desc>In single mode PWMTx_CNTR is not increased anymore after it reaches value equal to the PWMTx_LRC value.
In periodic mode PWMTx_CNTR is restarted after it reaches value equal to the PWMTx_LRC value.
</desc>
<position>4</position>
<enum>
<name>PERIODIC</name>
<value>0x0</value>
</enum>
<enum>
<name>SINGLE</name>
<value>0x1</value>
</enum>
</field>
<field>
<name>PWM_OUT_EN</name>
<desc>PWM output enable/disable.</desc>
<position>3</position>
<enum>
<name>DISABLE</name>
<value>0x0</value>
</enum>
<enum>
<name>ENABLE</name>
<value>0x1</value>
</enum>
</field>
<field>
<name>RESERVED2_1</name>
<position>1</position>
<width>2</width>
</field>
<field>
<name>PWM_EN</name>
<desc>PWM timer enable/disable.</desc>
<position>0</position>
<enum>
<name>DISABLE</name>
<value>0x0</value>
</enum>
<enum>
<name>ENABLE</name>
<value>0x1</value>
</enum>
</field>
</register>
</node>
</node>
<node>
<name>TIMER</name>
<title>TIMER</title>
<desc>Timer module</desc>
<instance>
<name>TIMER</name>
<range>
<first>1</first>
<address>0x18000000</address>
<address>0x18000010</address>
<address>0x18000020</address>
</range>
</instance>
<node>
<name>TMRnLR</name>
<instance>
<name>TMRnLR</name>
<range>
<first>0</first>
<count>1</count>
<formula variable="n">n*0x10</formula>
</range>
</instance>
<register/>
</node>
<node>
<name>TMRnCVR</name>
<instance>
<name>TMRnCVR</name>
<range>
<first>0</first>
<count>1</count>
<formula variable="n">0x04+n*0x10</formula>
</range>
</instance>
<register/>
</node>
<node>
<name>TMRnCON</name>
<instance>
<name>TMRnCON</name>
<range>
<first>0</first>
<count>1</count>
<formula variable="n">0x08+n*0x10</formula>
</range>
</instance>
<register/>
</node>
</node>
<node>
<name>UART</name>
<title>UART</title>
<desc>UART</desc>
<instance>
<name>UART</name>
<range>
<first>1</first>
<address>0x18004000</address>
<address>0x18008000</address>
</range>
</instance>
<node>
<name>UARTn_RBR</name>
<instance>
<name>UARTn_RBR</name>
<range>
<first>0</first>
<count>2</count>
<base>0x0</base>
<stride>0x0</stride>
</range>
</instance>
<register/>
</node>
<node>
<name>UARTn_THR</name>
<instance>
<name>UARTn_THR</name>
<range>
<first>0</first>
<count>2</count>
<base>0x0</base>
<stride>0x0</stride>
</range>
</instance>
<register/>
</node>
<node>
<name>UARTn_DLL</name>
<instance>
<name>UARTn_DLL</name>
<range>
<first>0</first>
<count>2</count>
<base>0x0</base>
<stride>0x0</stride>
</range>
</instance>
<register/>
</node>
<node>
<name>UARTn_DLH</name>
<instance>
<name>UARTn_DLH</name>
<range>
<first>0</first>
<count>2</count>
<base>0x4</base>
<stride>0x0</stride>
</range>
</instance>
<register/>
</node>
<node>
<name>UARTn_IER</name>
<instance>
<name>UARTn_IER</name>
<range>
<first>0</first>
<count>2</count>
<base>0x4</base>
<stride>0x0</stride>
</range>
</instance>
<register/>
</node>
<node>
<name>UARTn_IIR</name>
<instance>
<name>UARTn_IIR</name>
<range>
<first>0</first>
<count>2</count>
<base>0x8</base>
<stride>0x0</stride>
</range>
</instance>
<register/>
</node>
<node>
<name>UARTn_FCR</name>
<instance>
<name>UARTn_FCR</name>
<range>
<first>0</first>
<count>2</count>
<base>0x8</base>
<stride>0x0</stride>
</range>
</instance>
<register/>
</node>
<node>
<name>UARTn_LCR</name>
<instance>
<name>UARTn_LCR</name>
<range>
<first>0</first>
<count>2</count>
<base>0xc</base>
<stride>0x0</stride>
</range>
</instance>
<register/>
</node>
<node>
<name>UARTn_MCR</name>
<instance>
<name>UARTn_MCR</name>
<range>
<first>0</first>
<count>2</count>
<base>0x10</base>
<stride>0x0</stride>
</range>
</instance>
<register/>
</node>
<node>
<name>UARTn_LSR</name>
<instance>
<name>UARTn_LSR</name>
<range>
<first>0</first>
<count>2</count>
<base>0x14</base>
<stride>0x0</stride>
</range>
</instance>
<register/>
</node>
<node>
<name>UARTn_MSR</name>
<instance>
<name>UARTn_MSR</name>
<range>
<first>0</first>
<count>2</count>
<base>0x18</base>
<stride>0x0</stride>
</range>
</instance>
<register/>
</node>
</node>
</soc>
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