f6789a7d73
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@19548 a1c6a512-1295-4272-9138-f99709370657
108 lines
2.8 KiB
C
108 lines
2.8 KiB
C
/***************************************************************************
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* __________ __ ___.
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* Open \______ \ ____ ____ | | _\_ |__ _______ ___
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* Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
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* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
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* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
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* \/ \/ \/ \/ \/
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* $Id$
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*
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* Copyright (C) 2007 by Greg White
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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*
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* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
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* KIND, either express or implied.
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*
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****************************************************************************/
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#ifndef SYSTEM_TARGET_H
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#define SYSTEM_TARGET_H
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#include "system-arm.h"
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#include "mmu-arm.h"
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#ifndef HAVE_ADJUSTABLE_CPU_FREQ
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/* TODO: implement CPU frequency scaling */
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#define CPUFREQ_DEFAULT CPU_FREQ
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#define CPUFREQ_NORMAL CPU_FREQ
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#define CPUFREQ_MAX CPU_FREQ
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#endif
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#if 0
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static inline void udelay(unsigned int usecs)
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{
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volatile signed int stop = EPITCNT1 - usecs;
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while ((signed int)EPITCNT1 > stop);
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}
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#endif
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void watchdog_init(unsigned int half_seconds);
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void watchdog_service(void);
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/* Prepare for transition to firmware */
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void system_prepare_fw_start(void);
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void tick_stop(void);
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void kernel_device_init(void);
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void imx31_regmod32(volatile uint32_t *reg_p, uint32_t value,
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uint32_t mask);
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void imx31_regset32(volatile uint32_t *reg_p, uint32_t mask);
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void imx31_regclr32(volatile uint32_t *reg_p, uint32_t mask);
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#define KDEV_INIT
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#define HAVE_INVALIDATE_ICACHE
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static inline void invalidate_icache(void)
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{
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asm volatile(
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/* Clean and invalidate entire data cache */
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"mcr p15, 0, %0, c7, c14, 0 \n"
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/* Invalidate entire instruction cache
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* Also flushes the branch target cache */
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"mcr p15, 0, %0, c7, c5, 0 \n"
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/* Data synchronization barrier */
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"mcr p15, 0, %0, c7, c10, 4 \n"
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/* Flush prefetch buffer */
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"mcr p15, 0, %0, c7, c5, 4 \n"
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: : "r"(0)
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);
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}
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#define HAVE_FLUSH_ICACHE
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static inline void flush_icache(void)
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{
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asm volatile (
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/* Clean entire data cache */
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"mcr p15, 0, %0, c7, c10, 0 \n"
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/* Data synchronization barrier */
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"mcr p15, 0, %0, c7, c10, 4 \n"
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: : "r"(0)
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);
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}
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struct ARM_REGS {
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int r0;
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int r1;
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int r2;
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int r3;
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int r4;
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int r5;
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int r6;
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int r7;
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int r8;
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int r9;
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int r10;
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int r11;
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int r12;
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int sp;
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int lr;
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int pc;
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int cpsr;
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} regs;
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inline void dumpregs(void);
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#endif /* SYSTEM_TARGET_H */
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