279dff1c21
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@28834 a1c6a512-1295-4272-9138-f99709370657
1050 lines
32 KiB
C
1050 lines
32 KiB
C
/***************************************************************************
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* __________ __ ___.
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* Open \______ \ ____ ____ | | _\_ |__ _______ ___
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* Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
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* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
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* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
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* \/ \/ \/ \/ \/
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* $Id$
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*
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* Copyright (C) 2006 Daniel Ankers
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* Copyright © 2008-2009 Rafaël Carré
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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*
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* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
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* KIND, either express or implied.
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*
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****************************************************************************/
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/* Driver for the ARM PL180 SD/MMC controller inside AS3525 SoC */
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#include "config.h" /* for HAVE_MULTIDRIVE & AMS_OF_SIZE */
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#include "fat.h"
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#include "thread.h"
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#include "led.h"
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#include "sdmmc.h"
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#include "system.h"
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#include "cpu.h"
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#include <stdio.h>
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#include <stdlib.h>
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#include <string.h>
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#include "gcc_extensions.h"
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#include "as3525.h"
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#include "pl180.h" /* SD controller */
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#include "pl081.h" /* DMA controller */
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#include "dma-target.h" /* DMA request lines */
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#include "clock-target.h"
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#include "panic.h"
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#ifdef HAVE_BUTTON_LIGHT
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#include "backlight-target.h"
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#endif
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#include "stdbool.h"
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#include "ata_idle_notify.h"
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#include "sd.h"
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#include "usb.h"
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/*#define LOGF_ENABLE*/
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#include "logf.h"
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#ifdef HAVE_HOTSWAP
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#include "disk.h"
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#endif
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//#define VERIFY_WRITE 1
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/* command flags */
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#define MCI_NO_RESP (0<<0)
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#define MCI_RESP (1<<0)
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#define MCI_LONG_RESP (1<<1)
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#define MCI_ACMD (1<<2)
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#define MCI_NOCRC (1<<3)
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/* ARM PL180 registers */
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#define MCI_POWER(i) (*(volatile unsigned char *) (pl180_base[i]+0x00))
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#define MCI_CLOCK(i) (*(volatile unsigned long *) (pl180_base[i]+0x04))
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#define MCI_ARGUMENT(i) (*(volatile unsigned long *) (pl180_base[i]+0x08))
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#define MCI_COMMAND(i) (*(volatile unsigned long *) (pl180_base[i]+0x0C))
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#define MCI_RESPCMD(i) (*(volatile unsigned long *) (pl180_base[i]+0x10))
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#define MCI_RESP0(i) (*(volatile unsigned long *) (pl180_base[i]+0x14))
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#define MCI_RESP1(i) (*(volatile unsigned long *) (pl180_base[i]+0x18))
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#define MCI_RESP2(i) (*(volatile unsigned long *) (pl180_base[i]+0x1C))
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#define MCI_RESP3(i) (*(volatile unsigned long *) (pl180_base[i]+0x20))
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#define MCI_DATA_TIMER(i) (*(volatile unsigned long *) (pl180_base[i]+0x24))
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#define MCI_DATA_LENGTH(i) (*(volatile unsigned short*) (pl180_base[i]+0x28))
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#define MCI_DATA_CTRL(i) (*(volatile unsigned char *) (pl180_base[i]+0x2C))
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#define MCI_DATA_CNT(i) (*(volatile unsigned short*) (pl180_base[i]+0x30))
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#define MCI_STATUS(i) (*(volatile unsigned long *) (pl180_base[i]+0x34))
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#define MCI_CLEAR(i) (*(volatile unsigned long *) (pl180_base[i]+0x38))
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#define MCI_MASK0(i) (*(volatile unsigned long *) (pl180_base[i]+0x3C))
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#define MCI_MASK1(i) (*(volatile unsigned long *) (pl180_base[i]+0x40))
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#define MCI_SELECT(i) (*(volatile unsigned long *) (pl180_base[i]+0x44))
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#define MCI_FIFO_CNT(i) (*(volatile unsigned long *) (pl180_base[i]+0x48))
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#define MCI_DATA_ERROR \
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( MCI_DATA_CRC_FAIL \
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| MCI_DATA_TIMEOUT \
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| MCI_TX_UNDERRUN \
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| MCI_RX_OVERRUN \
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| MCI_START_BIT_ERR)
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#define MCI_RESPONSE_ERROR \
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( MCI_CMD_TIMEOUT \
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| MCI_CMD_CRC_FAIL)
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#define MCI_FIFO(i) ((unsigned long *) (pl180_base[i]+0x80))
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/* volumes */
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#define INTERNAL_AS3525 0 /* embedded SD card */
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#define SD_SLOT_AS3525 1 /* SD slot if present */
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static const int pl180_base[NUM_DRIVES] = {
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NAND_FLASH_BASE
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#ifdef HAVE_MULTIDRIVE
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, SD_MCI_BASE
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#endif
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};
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static int sd_wait_for_tran_state(const int drive);
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static int sd_select_bank(signed char bank);
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static int sd_init_card(const int drive);
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static void init_pl180_controller(const int drive);
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#define BLOCKS_PER_BANK 0x7a7800u
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static tCardInfo card_info[NUM_DRIVES];
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/* maximum timeouts recommanded in the SD Specification v2.00 */
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#define SD_MAX_READ_TIMEOUT ((AS3525_PCLK_FREQ*(cpu_frequency==CPUFREQ_MAX?2:1)) / 1000 * 100) /* 100 ms */
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#define SD_MAX_WRITE_TIMEOUT ((AS3525_PCLK_FREQ*(cpu_frequency==CPUFREQ_MAX?2:1)) / 1000 * 250) /* 250 ms */
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/* for compatibility */
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static long last_disk_activity = -1;
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#define MIN_YIELD_PERIOD 5 /* ticks */
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static long next_yield = 0;
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static long sd_stack [(DEFAULT_STACK_SIZE*2 + 0x200)/sizeof(long)];
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static const char sd_thread_name[] = "ata/sd";
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static struct mutex sd_mtx;
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static struct event_queue sd_queue;
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bool sd_enabled = false;
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#if defined(HAVE_MULTIDRIVE)
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static bool hs_card = false;
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#define EXT_SD_BITS (1<<2)
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#endif
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static struct wakeup transfer_completion_signal;
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static volatile unsigned int transfer_error[NUM_VOLUMES];
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#define PL180_MAX_TRANSFER_ERRORS 10
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extern long cpu_frequency;
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#define UNALIGNED_NUM_SECTORS 10
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static unsigned char aligned_buffer[UNALIGNED_NUM_SECTORS* SD_BLOCK_SIZE] __attribute__((aligned(32))); /* align on cache line size */
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static unsigned char *uncached_buffer = AS3525_UNCACHED_ADDR(&aligned_buffer[0]);
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static inline void mci_delay(void) { udelay(1000) ; }
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static inline bool card_detect_target(void)
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{
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#if defined(HAVE_MULTIDRIVE)
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return !(GPIOA_PIN(2));
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#else
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return false;
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#endif
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}
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#ifdef HAVE_HOTSWAP
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static int sd1_oneshot_callback(struct timeout *tmo)
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{
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(void)tmo;
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/* This is called only if the state was stable for 300ms - check state
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* and post appropriate event. */
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if (card_detect_target())
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{
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queue_broadcast(SYS_HOTSWAP_INSERTED, 0);
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}
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else
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queue_broadcast(SYS_HOTSWAP_EXTRACTED, 0);
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return 0;
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}
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void sd_gpioa_isr(void)
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{
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static struct timeout sd1_oneshot;
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if (GPIOA_MIS & EXT_SD_BITS)
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timeout_register(&sd1_oneshot, sd1_oneshot_callback, (3*HZ/10), 0);
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/* acknowledge interrupt */
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GPIOA_IC = EXT_SD_BITS;
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}
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#endif /* HAVE_HOTSWAP */
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void INT_NAND(void)
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{
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const int status = MCI_STATUS(INTERNAL_AS3525);
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transfer_error[INTERNAL_AS3525] = status & MCI_DATA_ERROR;
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wakeup_signal(&transfer_completion_signal);
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MCI_CLEAR(INTERNAL_AS3525) = status;
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}
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#ifdef HAVE_MULTIDRIVE
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void INT_MCI0(void)
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{
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const int status = MCI_STATUS(SD_SLOT_AS3525);
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transfer_error[SD_SLOT_AS3525] = status & MCI_DATA_ERROR;
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wakeup_signal(&transfer_completion_signal);
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MCI_CLEAR(SD_SLOT_AS3525) = status;
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}
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#endif
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static bool send_cmd(const int drive, const int cmd, const int arg,
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const int flags, long *response)
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{
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int status;
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unsigned cmd_retries = 6;
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while(cmd_retries--)
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{
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if ((flags & MCI_ACMD) && /* send SD_APP_CMD before each try */
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!send_cmd(drive, SD_APP_CMD, card_info[drive].rca, MCI_RESP, response))
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return false;
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/* Clear old status flags */
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MCI_CLEAR(drive) = 0x7ff;
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/* Load command argument or clear if none */
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MCI_ARGUMENT(drive) = arg;
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/* Construct MCI_COMMAND & enable CPSM */
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MCI_COMMAND(drive) =
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/*b0:5*/ cmd
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/* b6 */| ((flags & (MCI_RESP|MCI_LONG_RESP)) ? MCI_COMMAND_RESPONSE : 0)
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/* b7 */| ((flags & MCI_LONG_RESP) ? MCI_COMMAND_LONG_RESPONSE : 0)
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/* b8 | MCI_COMMAND_INTERRUPT */
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/* b9 | MCI_COMMAND_PENDING */ /*Only used with stream data transfer*/
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/* b10*/| MCI_COMMAND_ENABLE; /* Enables CPSM */
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/* Wait while cmd completes then disable CPSM */
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while(MCI_STATUS(drive) & MCI_CMD_ACTIVE);
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MCI_COMMAND(drive) = 0;
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status = MCI_STATUS(drive);
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/* Handle command responses */
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if(flags & MCI_RESP) /* CMD expects response */
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{
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response[0] = MCI_RESP0(drive); /* Always prepare short response */
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if(status & MCI_RESPONSE_ERROR) {/* timeout or crc failure */
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if ((status & MCI_CMD_CRC_FAIL) &&
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(flags & MCI_NOCRC))
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break;
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logf("sd cmd error: drive %d cmd %d arg %08x sd_status %08x resp0 %08lx",
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drive, cmd, arg, status, response[0]);
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continue;
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}
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if((flags & MCI_RESP) &&
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!(flags & MCI_LONG_RESP) &&
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(response[0] & SD_R1_CARD_ERROR)) {
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logf("sd card error: drive %d cmd %d arg %08x r1 %08lx",
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drive, cmd, arg, response[0]);
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}
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if(status & MCI_CMD_RESP_END) /* Response passed CRC check */
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{
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if(flags & MCI_LONG_RESP)
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{ /* response[0] has already been read */
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response[1] = MCI_RESP1(drive);
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response[2] = MCI_RESP2(drive);
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response[3] = MCI_RESP3(drive);
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}
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return true;
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}
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}
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else if(status & MCI_CMD_SENT) /* CMD sent, no response required */
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return true;
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}
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return false;
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}
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#define MCI_FULLSPEED (MCI_CLOCK_ENABLE | MCI_CLOCK_BYPASS) /* MCLK */
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#define MCI_HALFSPEED (MCI_CLOCK_ENABLE) /* MCLK/2 */
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#define MCI_QUARTERSPEED (MCI_CLOCK_ENABLE | 1) /* MCLK/4 */
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#define MCI_IDENTSPEED (MCI_CLOCK_ENABLE | AS3525_SD_IDENT_DIV) /* IDENT */
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#define MCI_IDENTSPEED_BOOSTED (MCI_CLOCK_ENABLE | AS3525_SD_IDENT_DIV_BOOSTED)
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static int sd_init_card(const int drive)
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{
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unsigned long response;
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long init_timeout;
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bool sd_v2 = false;
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card_info[drive].rca = 0;
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/* MCLCK on and set to 400kHz ident frequency */
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if (cpu_frequency == CPUFREQ_MAX)
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MCI_CLOCK(drive) = MCI_IDENTSPEED_BOOSTED;
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else
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MCI_CLOCK(drive) = MCI_IDENTSPEED;
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/* 100 - 400kHz clock required for Identification Mode */
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/* Start of Card Identification Mode ************************************/
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/* CMD0 Go Idle */
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if(!send_cmd(drive, SD_GO_IDLE_STATE, 0, MCI_NO_RESP, NULL))
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return -1;
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mci_delay();
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/* CMD8 Check for v2 sd card. Must be sent before using ACMD41
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Non v2 cards will not respond to this command*/
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if(send_cmd(drive, SD_SEND_IF_COND, 0x1AA, MCI_RESP, &response))
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if((response & 0xFFF) == 0x1AA)
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sd_v2 = true;
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/* timeout for initialization is 1sec, from SD Specification 2.00 */
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init_timeout = current_tick + HZ;
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do {
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/* this timeout is the only valid error for this loop*/
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if(TIME_AFTER(current_tick, init_timeout))
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return -2;
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/* ACMD41 For v2 cards set HCS bit[30] & send host voltage range to all */
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send_cmd(drive, SD_APP_OP_COND, (0x00FF8000 | (sd_v2 ? 1<<30 : 0)),
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MCI_ACMD|MCI_NOCRC|MCI_RESP, &card_info[drive].ocr);
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} while(!(card_info[drive].ocr & (1<<31)));
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/* CMD2 send CID */
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if(!send_cmd(drive, SD_ALL_SEND_CID, 0, MCI_RESP|MCI_LONG_RESP,
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card_info[drive].cid))
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return -3;
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/* CMD3 send RCA */
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if(!send_cmd(drive, SD_SEND_RELATIVE_ADDR, 0, MCI_RESP,
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&card_info[drive].rca))
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return -4;
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/* End of Card Identification Mode ************************************/
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#ifdef HAVE_MULTIDRIVE /* The internal SDs are v1 */
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/* Try to switch V2 cards to HS timings, non HS seem to ignore this */
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if(sd_v2)
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{
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/* CMD7 w/rca: Select card to put it in TRAN state */
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if(!send_cmd(drive, SD_SELECT_CARD, card_info[drive].rca, MCI_RESP, &response))
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return -5;
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if(sd_wait_for_tran_state(drive))
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return -6;
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/* CMD6 */
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if(!send_cmd(drive, SD_SWITCH_FUNC, 0x80fffff1, MCI_NO_RESP, NULL))
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return -7;
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mci_delay();
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/* go back to STBY state so we can read csd */
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/* CMD7 w/rca=0: Deselect card to put it in STBY state */
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if(!send_cmd(drive, SD_DESELECT_CARD, 0, MCI_NO_RESP, NULL))
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return -8;
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mci_delay();
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}
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#endif /* HAVE_MULTIDRIVE */
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/* CMD9 send CSD */
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if(!send_cmd(drive, SD_SEND_CSD, card_info[drive].rca,
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MCI_RESP|MCI_LONG_RESP, card_info[drive].csd))
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return -9;
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sd_parse_csd(&card_info[drive]);
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#if defined(HAVE_MULTIDRIVE)
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hs_card = (card_info[drive].speed == 50000000);
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#endif
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/* Boost MCICLK to operating speed */
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if(drive == INTERNAL_AS3525)
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MCI_CLOCK(drive) = MCI_HALFSPEED; /* MCICLK = IDE_CLK/2 = 25 MHz */
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#if defined(HAVE_MULTIDRIVE)
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else
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{ /* PCLK = 31Mhz (62 boosted) MCI = 31Mhz(hs) or 15.5 */
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if (cpu_frequency == CPUFREQ_MAX )
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MCI_CLOCK(drive) = (hs_card ? MCI_HALFSPEED : MCI_QUARTERSPEED);
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else
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MCI_CLOCK(drive) = (hs_card ? MCI_FULLSPEED : MCI_HALFSPEED);
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}
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#endif
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/* CMD7 w/rca: Select card to put it in TRAN state */
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if(!send_cmd(drive, SD_SELECT_CARD, card_info[drive].rca, MCI_RESP, &response))
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return -10;
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#if 0 /* FIXME : it seems that reading fails on some models */
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/* Switch to to 4 bit widebus mode */
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if(sd_wait_for_tran_state(drive) < 0)
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return -11;
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/* ACMD42 */
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if(!send_cmd(drive, SD_SET_CLR_CARD_DETECT, 0, MCI_ACMD|MCI_RESP, &response))
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return -15;
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/* ACMD6 */
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if(!send_cmd(drive, SD_SET_BUS_WIDTH, 2, MCI_ACMD|MCI_RESP, &response))
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return -13;
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/* Now that card is widebus make controller aware */
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MCI_CLOCK(drive) |= MCI_CLOCK_WIDEBUS;
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#endif
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/*
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* enable bank switching
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* without issuing this command, we only have access to 1/4 of the blocks
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* of the first bank (0x1E9E00 blocks, which is the size reported in the
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* CSD register)
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*/
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if(drive == INTERNAL_AS3525)
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{
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const int ret = sd_select_bank(-1);
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if(ret < 0)
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return ret -16;
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/* CMD7 w/rca = 0: Unselect card to put it in STBY state */
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if(!send_cmd(drive, SD_SELECT_CARD, 0, MCI_NO_RESP, NULL))
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return -17;
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mci_delay();
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/* CMD9 send CSD again, so we got the correct number of blocks */
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if(!send_cmd(drive, SD_SEND_CSD, card_info[drive].rca,
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MCI_RESP|MCI_LONG_RESP, card_info[drive].csd))
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return -18;
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sd_parse_csd(&card_info[drive]);
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/* The OF is stored in the first blocks */
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card_info[INTERNAL_AS3525].numblocks -= AMS_OF_SIZE;
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/* CMD7 w/rca: Select card to put it in TRAN state */
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if(!send_cmd(drive, SD_SELECT_CARD, card_info[drive].rca, MCI_RESP, &response))
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return -19;
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}
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card_info[drive].initialized = 1;
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return 0;
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}
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static void sd_thread(void) NORETURN_ATTR;
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static void sd_thread(void)
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{
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struct queue_event ev;
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bool idle_notified = false;
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while (1)
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{
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queue_wait_w_tmo(&sd_queue, &ev, HZ);
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switch ( ev.id )
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{
|
|
#ifdef HAVE_HOTSWAP
|
|
case SYS_HOTSWAP_INSERTED:
|
|
case SYS_HOTSWAP_EXTRACTED:
|
|
{
|
|
int microsd_init = 1;
|
|
fat_lock(); /* lock-out FAT activity first -
|
|
prevent deadlocking via disk_mount that
|
|
would cause a reverse-order attempt with
|
|
another thread */
|
|
mutex_lock(&sd_mtx); /* lock-out card activity - direct calls
|
|
into driver that bypass the fat cache */
|
|
|
|
/* We now have exclusive control of fat cache and ata */
|
|
|
|
disk_unmount(SD_SLOT_AS3525); /* release "by force", ensure file
|
|
descriptors aren't leaked and any busy
|
|
ones are invalid if mounting */
|
|
|
|
/* Force card init for new card, re-init for re-inserted one or
|
|
* clear if the last attempt to init failed with an error. */
|
|
card_info[SD_SLOT_AS3525].initialized = 0;
|
|
|
|
if (ev.id == SYS_HOTSWAP_INSERTED)
|
|
{
|
|
sd_enable(true);
|
|
init_pl180_controller(SD_SLOT_AS3525);
|
|
microsd_init = sd_init_card(SD_SLOT_AS3525);
|
|
if (microsd_init < 0) /* initialisation failed */
|
|
panicf("microSD init failed : %d", microsd_init);
|
|
|
|
microsd_init = disk_mount(SD_SLOT_AS3525); /* 0 if fail */
|
|
}
|
|
|
|
/*
|
|
* Mount succeeded, or this was an EXTRACTED event,
|
|
* in both cases notify the system about the changed filesystems
|
|
*/
|
|
if (microsd_init)
|
|
queue_broadcast(SYS_FS_CHANGED, 0);
|
|
|
|
/* Access is now safe */
|
|
mutex_unlock(&sd_mtx);
|
|
fat_unlock();
|
|
sd_enable(false);
|
|
}
|
|
break;
|
|
#endif
|
|
case SYS_TIMEOUT:
|
|
if (TIME_BEFORE(current_tick, last_disk_activity+(3*HZ)))
|
|
{
|
|
idle_notified = false;
|
|
}
|
|
else
|
|
{
|
|
/* never let a timer wrap confuse us */
|
|
next_yield = current_tick;
|
|
|
|
if (!idle_notified)
|
|
{
|
|
call_storage_idle_notifys(false);
|
|
idle_notified = true;
|
|
}
|
|
}
|
|
break;
|
|
|
|
case SYS_USB_CONNECTED:
|
|
usb_acknowledge(SYS_USB_CONNECTED_ACK);
|
|
/* Wait until the USB cable is extracted again */
|
|
usb_wait_for_disconnect(&sd_queue);
|
|
|
|
break;
|
|
case SYS_USB_DISCONNECTED:
|
|
usb_acknowledge(SYS_USB_DISCONNECTED_ACK);
|
|
break;
|
|
}
|
|
}
|
|
}
|
|
|
|
#ifdef HAVE_MULTIDRIVE
|
|
void sd_set_boosted_divider(void)
|
|
{
|
|
if ( !sd_enabled )
|
|
return;
|
|
/* 62Mhz/2 - 62/4 */
|
|
MCI_CLOCK(SD_SLOT_AS3525) = (hs_card ?
|
|
MCI_HALFSPEED : MCI_QUARTERSPEED);
|
|
}
|
|
|
|
void sd_set_unboosted_divider(void)
|
|
{
|
|
if ( !sd_enabled )
|
|
return;
|
|
/* 31Mhz/1 - 31/2 */
|
|
MCI_CLOCK(SD_SLOT_AS3525) = (hs_card ?
|
|
MCI_FULLSPEED : MCI_HALFSPEED);
|
|
}
|
|
#endif
|
|
|
|
static void init_pl180_controller(const int drive)
|
|
{
|
|
MCI_COMMAND(drive) = MCI_DATA_CTRL(drive) = 0;
|
|
MCI_CLEAR(drive) = 0x7ff;
|
|
|
|
MCI_MASK0(drive) = MCI_DATA_ERROR | MCI_DATA_END;
|
|
MCI_MASK1(drive) = 0;
|
|
#ifdef HAVE_MULTIDRIVE
|
|
VIC_INT_ENABLE =
|
|
(drive == INTERNAL_AS3525) ? INTERRUPT_NAND : INTERRUPT_MCI0;
|
|
/* clear previous irq */
|
|
GPIOA_IC = EXT_SD_BITS;
|
|
/* enable edge detecting */
|
|
GPIOA_IS &= ~EXT_SD_BITS;
|
|
/* detect both raising and falling edges */
|
|
GPIOA_IBE |= EXT_SD_BITS;
|
|
/* enable the card detect interrupt */
|
|
GPIOA_IE |= EXT_SD_BITS;
|
|
|
|
#else
|
|
VIC_INT_ENABLE = INTERRUPT_NAND;
|
|
#endif
|
|
|
|
MCI_POWER(drive) = MCI_POWER_UP | (MCI_VDD_3_0); /* OF Setting */
|
|
mci_delay();
|
|
|
|
MCI_POWER(drive) |= MCI_POWER_ON;
|
|
mci_delay();
|
|
|
|
MCI_SELECT(drive) = 0;
|
|
|
|
/* Pl180 clocks get turned on at start of card init */
|
|
}
|
|
|
|
int sd_init(void)
|
|
{
|
|
int ret;
|
|
CGU_IDE = (1<<6) /* enable non AHB interface*/
|
|
| (AS3525_IDE_DIV << 2)
|
|
| AS3525_CLK_PLLA; /* clock source = PLLA */
|
|
|
|
bitset32(&CGU_PERI, CGU_NAF_CLOCK_ENABLE);
|
|
#ifdef HAVE_MULTIDRIVE
|
|
bitset32(&CGU_PERI, CGU_MCI_CLOCK_ENABLE);
|
|
bitclr32(&CCU_IO, 1<<3); /* bits 3:2 = 01, xpd is SD interface */
|
|
bitset32(&CCU_IO, 1<<2);
|
|
#endif
|
|
|
|
wakeup_init(&transfer_completion_signal);
|
|
|
|
init_pl180_controller(INTERNAL_AS3525);
|
|
ret = sd_init_card(INTERNAL_AS3525);
|
|
if(ret < 0)
|
|
return ret;
|
|
#ifdef HAVE_MULTIDRIVE
|
|
init_pl180_controller(SD_SLOT_AS3525);
|
|
#endif
|
|
|
|
/* init mutex */
|
|
mutex_init(&sd_mtx);
|
|
|
|
queue_init(&sd_queue, true);
|
|
create_thread(sd_thread, sd_stack, sizeof(sd_stack), 0,
|
|
sd_thread_name IF_PRIO(, PRIORITY_USER_INTERFACE) IF_COP(, CPU));
|
|
|
|
sd_enabled = true;
|
|
sd_enable(false);
|
|
|
|
return 0;
|
|
}
|
|
|
|
#ifdef HAVE_HOTSWAP
|
|
bool sd_removable(IF_MD_NONVOID(int drive))
|
|
{
|
|
return (drive==1);
|
|
}
|
|
|
|
bool sd_present(IF_MD_NONVOID(int drive))
|
|
{
|
|
return (drive == 0) ? true : card_detect_target();
|
|
}
|
|
#endif /* HAVE_HOTSWAP */
|
|
|
|
static int sd_wait_for_tran_state(const int drive)
|
|
{
|
|
unsigned long response = 0;
|
|
unsigned int timeout = current_tick + 5 * HZ;
|
|
|
|
while (1)
|
|
{
|
|
if(!send_cmd(drive, SD_SEND_STATUS, card_info[drive].rca, MCI_RESP,
|
|
&response))
|
|
return -1;
|
|
|
|
if (((response >> 9) & 0xf) == SD_TRAN)
|
|
return 0;
|
|
|
|
if(TIME_AFTER(current_tick, timeout))
|
|
return -2;
|
|
|
|
if (TIME_AFTER(current_tick, next_yield))
|
|
{
|
|
yield();
|
|
next_yield = current_tick + MIN_YIELD_PERIOD;
|
|
}
|
|
}
|
|
}
|
|
|
|
static int sd_select_bank(signed char bank)
|
|
{
|
|
int ret;
|
|
unsigned loops = 0;
|
|
|
|
memset(uncached_buffer, 0, 512);
|
|
if(bank == -1)
|
|
{ /* enable bank switching */
|
|
uncached_buffer[0] = 16;
|
|
uncached_buffer[1] = 1;
|
|
uncached_buffer[2] = 10;
|
|
}
|
|
else
|
|
uncached_buffer[0] = bank;
|
|
|
|
do {
|
|
if(loops++ > PL180_MAX_TRANSFER_ERRORS)
|
|
panicf("SD bank %d error : 0x%x", bank,
|
|
transfer_error[INTERNAL_AS3525]);
|
|
|
|
ret = sd_wait_for_tran_state(INTERNAL_AS3525);
|
|
if (ret < 0)
|
|
return ret - 2;
|
|
|
|
if(!send_cmd(INTERNAL_AS3525, SD_SWITCH_FUNC, 0x80ffffef, MCI_NO_RESP,
|
|
NULL))
|
|
return -1;
|
|
|
|
mci_delay();
|
|
|
|
if(!send_cmd(INTERNAL_AS3525, 35, 0, MCI_NO_RESP, NULL))
|
|
return -2;
|
|
|
|
mci_delay();
|
|
|
|
dma_retain();
|
|
/* we don't use the uncached buffer here, because we need the
|
|
* physical memory address for DMA transfers */
|
|
dma_enable_channel(0, AS3525_PHYSICAL_ADDR(&aligned_buffer[0]),
|
|
MCI_FIFO(INTERNAL_AS3525), DMA_PERI_SD,
|
|
DMAC_FLOWCTRL_PERI_MEM_TO_PERI, true, false, 0, DMA_S8, NULL);
|
|
|
|
MCI_DATA_TIMER(INTERNAL_AS3525) = SD_MAX_WRITE_TIMEOUT;
|
|
MCI_DATA_LENGTH(INTERNAL_AS3525) = 512;
|
|
MCI_DATA_CTRL(INTERNAL_AS3525) = (1<<0) /* enable */ |
|
|
(0<<1) /* transfer direction */ |
|
|
(1<<3) /* DMA */ |
|
|
(9<<4) /* 2^9 = 512 */ ;
|
|
|
|
/* Wakeup signal from NAND/MCIO isr on MCI_DATA_ERROR | MCI_DATA_END */
|
|
wakeup_wait(&transfer_completion_signal, TIMEOUT_BLOCK);
|
|
|
|
/* Wait for FIFO to empty, card may still be in PRG state */
|
|
while(MCI_STATUS(INTERNAL_AS3525) & MCI_TX_ACTIVE );
|
|
|
|
dma_release();
|
|
|
|
} while(transfer_error[INTERNAL_AS3525]);
|
|
|
|
card_info[INTERNAL_AS3525].current_bank = (bank == -1) ? 0 : bank;
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int sd_transfer_sectors(IF_MD2(int drive,) unsigned long start,
|
|
int count, void* buf, const bool write)
|
|
{
|
|
#ifndef HAVE_MULTIDRIVE
|
|
const int drive = 0;
|
|
#endif
|
|
int ret = 0;
|
|
unsigned loops = 0;
|
|
unsigned long response;
|
|
bool aligned = !((uintptr_t)buf & (CACHEALIGN_SIZE - 1));
|
|
|
|
sd_enable(true);
|
|
led(true);
|
|
|
|
if (card_info[drive].initialized <= 0)
|
|
{
|
|
ret = sd_init_card(drive);
|
|
if (!(card_info[drive].initialized))
|
|
goto sd_transfer_error_nodma;
|
|
}
|
|
|
|
if(count < 0) /* XXX: why is it signed ? */
|
|
{
|
|
ret = -20;
|
|
goto sd_transfer_error_nodma;
|
|
}
|
|
if((start+count) > card_info[drive].numblocks)
|
|
{
|
|
ret = -21;
|
|
goto sd_transfer_error_nodma;
|
|
}
|
|
|
|
/* skip SanDisk OF */
|
|
if (drive == INTERNAL_AS3525)
|
|
start += AMS_OF_SIZE;
|
|
|
|
last_disk_activity = current_tick;
|
|
|
|
dma_retain();
|
|
|
|
if(aligned)
|
|
{ /* direct transfer, indirect is always uncached */
|
|
if(write)
|
|
commit_dcache_range(buf, count * SECTOR_SIZE);
|
|
else
|
|
discard_dcache_range(buf, count * SECTOR_SIZE);
|
|
}
|
|
|
|
while(count)
|
|
{
|
|
/* 128 * 512 = 2^16, and doesn't fit in the 16 bits of DATA_LENGTH
|
|
* register, so we have to transfer maximum 127 sectors at a time. */
|
|
unsigned int transfer = (count >= 128) ? 127 : count; /* sectors */
|
|
void *dma_buf;
|
|
const int cmd =
|
|
write ? SD_WRITE_MULTIPLE_BLOCK : SD_READ_MULTIPLE_BLOCK;
|
|
unsigned long bank_start = start;
|
|
unsigned long status;
|
|
|
|
/* Only switch banks for internal storage */
|
|
if(drive == INTERNAL_AS3525)
|
|
{
|
|
unsigned int bank = 0;
|
|
while(bank_start >= BLOCKS_PER_BANK)
|
|
{
|
|
bank_start -= BLOCKS_PER_BANK;
|
|
bank++;
|
|
}
|
|
|
|
/* Switch bank if needed */
|
|
if(card_info[INTERNAL_AS3525].current_bank != bank)
|
|
{
|
|
ret = sd_select_bank(bank);
|
|
if (ret < 0)
|
|
{
|
|
ret -= 20;
|
|
goto sd_transfer_error;
|
|
}
|
|
}
|
|
|
|
/* Do not cross a bank boundary in a single transfer loop */
|
|
if((transfer + bank_start) > BLOCKS_PER_BANK)
|
|
transfer = BLOCKS_PER_BANK - bank_start;
|
|
}
|
|
|
|
/* Set bank_start to the correct unit (blocks or bytes) */
|
|
if(!(card_info[drive].ocr & (1<<30))) /* not SDHC */
|
|
bank_start *= SD_BLOCK_SIZE;
|
|
|
|
if(aligned)
|
|
{
|
|
dma_buf = AS3525_PHYSICAL_ADDR(buf);
|
|
}
|
|
else
|
|
{
|
|
dma_buf = AS3525_PHYSICAL_ADDR(&aligned_buffer[0]);
|
|
if(transfer > UNALIGNED_NUM_SECTORS)
|
|
transfer = UNALIGNED_NUM_SECTORS;
|
|
|
|
if(write)
|
|
memcpy(uncached_buffer, buf, transfer * SD_BLOCK_SIZE);
|
|
}
|
|
|
|
ret = sd_wait_for_tran_state(drive);
|
|
if (ret < 0)
|
|
{
|
|
ret -= 2*20;
|
|
goto sd_transfer_error;
|
|
}
|
|
|
|
if(!send_cmd(drive, cmd, bank_start, MCI_RESP, &response))
|
|
{
|
|
ret -= 3*20;
|
|
goto sd_transfer_error;
|
|
}
|
|
|
|
if(write)
|
|
{
|
|
dma_enable_channel(0, dma_buf, MCI_FIFO(drive),
|
|
(drive == INTERNAL_AS3525) ? DMA_PERI_SD : DMA_PERI_SD_SLOT,
|
|
DMAC_FLOWCTRL_PERI_MEM_TO_PERI, true, false, 0, DMA_S8, NULL);
|
|
|
|
/*Small delay for writes prevents data crc failures at lower freqs*/
|
|
#ifdef HAVE_MULTIDRIVE
|
|
if((drive == SD_SLOT_AS3525) && !hs_card)
|
|
{
|
|
int write_delay = 125;
|
|
while(write_delay--);
|
|
}
|
|
#endif
|
|
}
|
|
else
|
|
dma_enable_channel(0, MCI_FIFO(drive), dma_buf,
|
|
(drive == INTERNAL_AS3525) ? DMA_PERI_SD : DMA_PERI_SD_SLOT,
|
|
DMAC_FLOWCTRL_PERI_PERI_TO_MEM, false, true, 0, DMA_S8, NULL);
|
|
|
|
MCI_DATA_TIMER(drive) = write ?
|
|
SD_MAX_WRITE_TIMEOUT : SD_MAX_READ_TIMEOUT;
|
|
MCI_DATA_LENGTH(drive) = transfer * SD_BLOCK_SIZE;
|
|
MCI_DATA_CTRL(drive) = (1<<0) /* enable */ |
|
|
(!write<<1) /* transfer direction */ |
|
|
(1<<3) /* DMA */ |
|
|
(9<<4) /* 2^9 = 512 */ ;
|
|
|
|
/* Wakeup signal from NAND/MCIO isr on MCI_DATA_ERROR | MCI_DATA_END */
|
|
wakeup_wait(&transfer_completion_signal, TIMEOUT_BLOCK);
|
|
|
|
/* Wait for FIFO to empty, card may still be in PRG state for writes */
|
|
while(MCI_STATUS(drive) & MCI_TX_ACTIVE);
|
|
|
|
/*
|
|
* If the write aborted early due to a tx underrun, disable the
|
|
* dma channel here, otherwise there are still 4 words in the fifo
|
|
* and the retried write will get corrupted.
|
|
*/
|
|
dma_disable_channel(0);
|
|
|
|
last_disk_activity = current_tick;
|
|
|
|
if(!send_cmd(drive, SD_STOP_TRANSMISSION, 0, MCI_RESP, &status))
|
|
{
|
|
ret = -4*20;
|
|
goto sd_transfer_error;
|
|
}
|
|
|
|
if(!transfer_error[drive])
|
|
{
|
|
if(!write && !aligned)
|
|
memcpy(buf, uncached_buffer, transfer * SD_BLOCK_SIZE);
|
|
buf += transfer * SD_BLOCK_SIZE;
|
|
start += transfer;
|
|
count -= transfer;
|
|
loops = 0; /* reset errors counter */
|
|
}
|
|
else if(loops++ > PL180_MAX_TRANSFER_ERRORS)
|
|
panicf("SD Xfer %s err:0x%x Disk%d", (write? "write": "read"),
|
|
transfer_error[drive], drive);
|
|
}
|
|
|
|
sd_transfer_error:
|
|
|
|
dma_release();
|
|
|
|
sd_transfer_error_nodma:
|
|
|
|
led(false);
|
|
sd_enable(false);
|
|
|
|
if (ret) /* error */
|
|
card_info[drive].initialized = 0;
|
|
|
|
return ret;
|
|
}
|
|
|
|
int sd_read_sectors(IF_MD2(int drive,) unsigned long start, int count,
|
|
void* buf)
|
|
{
|
|
int ret;
|
|
|
|
mutex_lock(&sd_mtx);
|
|
ret = sd_transfer_sectors(IF_MD2(drive,) start, count, buf, false);
|
|
mutex_unlock(&sd_mtx);
|
|
|
|
return ret;
|
|
}
|
|
|
|
int sd_write_sectors(IF_MD2(int drive,) unsigned long start, int count,
|
|
const void* buf)
|
|
{
|
|
#ifdef VERIFY_WRITE
|
|
unsigned long saved_start = start;
|
|
int saved_count = count;
|
|
void *saved_buf = (void*)buf;
|
|
#endif
|
|
int ret;
|
|
|
|
mutex_lock(&sd_mtx);
|
|
|
|
ret = sd_transfer_sectors(IF_MD2(drive,) start, count, (void*)buf, true);
|
|
|
|
#ifdef VERIFY_WRITE
|
|
if (ret) {
|
|
/* write failed, no point in verifying */
|
|
mutex_unlock(&sd_mtx);
|
|
return ret;
|
|
}
|
|
|
|
count = saved_count;
|
|
buf = saved_buf;
|
|
start = saved_start;
|
|
while (count) {
|
|
int transfer = count;
|
|
if(transfer > UNALIGNED_NUM_SECTORS)
|
|
transfer = UNALIGNED_NUM_SECTORS;
|
|
|
|
sd_transfer_sectors(IF_MD2(drive,) start, transfer, aligned_buffer, false);
|
|
if (memcmp(buf, aligned_buffer, transfer * 512) != 0) {
|
|
/* try the write again in the hope to repair the damage */
|
|
sd_transfer_sectors(IF_MD2(drive,) saved_start, saved_count, saved_buf, true);
|
|
panicf("sd: verify failed: sec=%ld n=%d!", start, transfer);
|
|
}
|
|
|
|
buf += transfer * 512;
|
|
count -= transfer;
|
|
start += transfer;
|
|
}
|
|
#endif
|
|
|
|
mutex_unlock(&sd_mtx);
|
|
|
|
return ret;
|
|
}
|
|
|
|
long sd_last_disk_activity(void)
|
|
{
|
|
return last_disk_activity;
|
|
}
|
|
|
|
void sd_enable(bool on)
|
|
{
|
|
#if defined(HAVE_BUTTON_LIGHT) && defined(HAVE_MULTIDRIVE)
|
|
extern int buttonlight_is_on;
|
|
#endif
|
|
|
|
#if defined(HAVE_HOTSWAP) && defined (HAVE_ADJUSTABLE_CPU_VOLTAGE)
|
|
static bool cpu_boosted = false;
|
|
#endif
|
|
|
|
if (sd_enabled == on)
|
|
return; /* nothing to do */
|
|
|
|
sd_enabled = on;
|
|
|
|
if(on)
|
|
{
|
|
#if defined(HAVE_BUTTON_LIGHT) && defined(HAVE_MULTIDRIVE)
|
|
/* buttonlight AMSes need a bit of special handling for the buttonlight
|
|
* here due to the dual mapping of GPIOD and XPD */
|
|
bitset32(&CCU_IO, 1<<2); /* XPD is SD-MCI interface (b3:2 = 01) */
|
|
if (buttonlight_is_on)
|
|
GPIOD_DIR &= ~(1<<7);
|
|
else
|
|
_buttonlight_off();
|
|
#endif
|
|
|
|
#if defined(HAVE_HOTSWAP) && defined (HAVE_ADJUSTABLE_CPU_VOLTAGE)
|
|
if(card_detect_target()) /* If SD card present Boost cpu for voltage */
|
|
{
|
|
cpu_boosted = true;
|
|
cpu_boost(true);
|
|
}
|
|
#endif /* defined(HAVE_HOTSWAP) && defined (HAVE_ADJUSTABLE_CPU_VOLTAGE) */
|
|
}
|
|
else
|
|
{
|
|
#if defined(HAVE_HOTSWAP) && defined (HAVE_ADJUSTABLE_CPU_VOLTAGE)
|
|
if(cpu_boosted)
|
|
{
|
|
cpu_boost(false);
|
|
cpu_boosted = false;
|
|
}
|
|
#endif /* defined(HAVE_HOTSWAP) && defined (HAVE_ADJUSTABLE_CPU_VOLTAGE) */
|
|
|
|
#if defined(HAVE_BUTTON_LIGHT) && defined(HAVE_MULTIDRIVE)
|
|
bitclr32(&CCU_IO, 1<<2); /* XPD is general purpose IO (b3:2 = 00) */
|
|
if (buttonlight_is_on)
|
|
_buttonlight_on();
|
|
#endif
|
|
}
|
|
}
|
|
|
|
tCardInfo *card_get_info_target(int card_no)
|
|
{
|
|
return &card_info[card_no];
|
|
}
|
|
|
|
#ifdef CONFIG_STORAGE_MULTI
|
|
int sd_num_drives(int first_drive)
|
|
{
|
|
/* We don't care which logical drive number(s) we have been assigned */
|
|
(void)first_drive;
|
|
|
|
return NUM_DRIVES;
|
|
}
|
|
#endif /* CONFIG_STORAGE_MULTI */
|