258 lines
7.3 KiB
C
258 lines
7.3 KiB
C
/***************************************************************************
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* __________ __ ___.
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* Open \______ \ ____ ____ | | _\_ |__ _______ ___
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* Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
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* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
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* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
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* \/ \/ \/ \/ \/
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* $Id$
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*
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* Copyright (C) 2021 Aidan MacDonald
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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*
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* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
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* KIND, either express or implied.
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*
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****************************************************************************/
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#include "system.h"
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#include "clk-x1000.h"
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#include "x1000/cpm.h"
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#include "x1000/msc.h"
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#include "x1000/aic.h"
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static uint32_t pll_get(uint32_t pllreg, uint32_t onbit)
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{
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if((pllreg & (1 << onbit)) == 0)
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return 0;
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/* Both PLL registers share the same layout of N/M/OD bits.
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* The max multiplier is 128 and max EXCLK is 26 MHz, so the
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* multiplication should fit within 32 bits without overflow.
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*/
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uint32_t rate = X1000_EXCLK_FREQ;
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rate *= jz_vreadf(pllreg, CPM_APCR, PLLM) + 1;
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rate /= jz_vreadf(pllreg, CPM_APCR, PLLN) + 1;
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rate >>= jz_vreadf(pllreg, CPM_APCR, PLLOD);
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return rate;
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}
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static uint32_t sclk_a_get(void)
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{
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switch(jz_readf(CPM_CCR, SEL_SRC)) {
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case 1: return X1000_EXCLK_FREQ;
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case 2: return clk_get(X1000_CLK_APLL);
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default: return 0;
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}
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}
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static uint32_t ccr_get(uint32_t selbit, uint32_t divbit)
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{
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uint32_t reg = REG_CPM_CCR;
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uint32_t sel = (reg >> selbit) & 0x3;
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uint32_t div = (reg >> divbit) & 0xf;
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switch(sel) {
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case 1: return clk_get(X1000_CLK_SCLK_A) / (div + 1);
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case 2: return clk_get(X1000_CLK_MPLL) / (div + 1);
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default: return 0;
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}
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}
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static uint32_t ddr_get(void)
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{
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uint32_t reg = REG_CPM_DDRCDR;
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uint32_t div = jz_vreadf(reg, CPM_DDRCDR, CLKDIV);
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switch(jz_vreadf(reg, CPM_DDRCDR, CLKSRC)) {
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case 1: return clk_get(X1000_CLK_SCLK_A) / (div + 1);
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case 2: return clk_get(X1000_CLK_MPLL) / (div + 1);
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default: return 0;
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}
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}
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static uint32_t lcd_get(void)
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{
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if(jz_readf(CPM_CLKGR, LCD))
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return 0;
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uint32_t reg = REG_CPM_LPCDR;
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uint32_t rate;
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switch(jz_vreadf(reg, CPM_LPCDR, CLKSRC)) {
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case 0: rate = clk_get(X1000_CLK_SCLK_A); break;
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case 1: rate = clk_get(X1000_CLK_MPLL); break;
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default: return 0;
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}
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rate /= jz_vreadf(reg, CPM_LPCDR, CLKDIV) + 1;
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return rate;
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}
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static uint32_t msc_get(int msc)
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{
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if((msc == 0 && jz_readf(CPM_CLKGR, MSC0)) ||
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(msc == 1 && jz_readf(CPM_CLKGR, MSC1)))
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return 0;
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uint32_t reg = REG_CPM_MSC0CDR;
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uint32_t rate;
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switch(jz_vreadf(reg, CPM_MSC0CDR, CLKSRC)) {
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case 0: rate = clk_get(X1000_CLK_SCLK_A); break;
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case 1: rate = clk_get(X1000_CLK_MPLL); break;
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default: return 0;
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}
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uint32_t div;
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if(msc == 0)
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div = jz_readf(CPM_MSC0CDR, CLKDIV);
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else
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div = jz_readf(CPM_MSC1CDR, CLKDIV);
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rate /= 2 * (div + 1);
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rate >>= REG_MSC_CLKRT(msc);
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return rate;
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}
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static uint32_t i2s_mclk_get(void)
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{
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if(jz_readf(CPM_CLKGR, AIC))
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return 0;
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uint32_t reg = REG_CPM_I2SCDR;
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unsigned long long rate;
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if(jz_vreadf(reg, CPM_I2SCDR, CS) == 0)
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rate = X1000_EXCLK_FREQ;
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else {
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if(jz_vreadf(reg, CPM_I2SCDR, PCS) == 0)
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rate = clk_get(X1000_CLK_SCLK_A);
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else
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rate = clk_get(X1000_CLK_MPLL);
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rate *= jz_vreadf(reg, CPM_I2SCDR, DIV_M);
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rate /= jz_vreadf(reg, CPM_I2SCDR, DIV_N);
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}
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/* Clamp invalid setting to 32 bits */
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if(rate > 0xffffffffull)
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rate = 0xffffffff;
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return rate;
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}
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static uint32_t i2s_bclk_get(void)
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{
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return i2s_mclk_get() / (REG_AIC_I2SDIV + 1);
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}
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static uint32_t sfc_get(void)
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{
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if(jz_readf(CPM_CLKGR, SFC))
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return 0;
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uint32_t reg = REG_CPM_SSICDR;
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uint32_t rate;
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if(jz_vreadf(reg, CPM_SSICDR, SFC_CS) == 0)
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rate = clk_get(X1000_CLK_SCLK_A);
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else
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rate = clk_get(X1000_CLK_MPLL);
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rate /= jz_vreadf(reg, CPM_SSICDR, CLKDIV) + 1;
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return rate;
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}
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uint32_t clk_get(x1000_clk_t clk)
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{
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switch(clk) {
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case X1000_CLK_EXCLK: return X1000_EXCLK_FREQ;
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case X1000_CLK_APLL: return pll_get(REG_CPM_APCR, BP_CPM_APCR_ON);
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case X1000_CLK_MPLL: return pll_get(REG_CPM_MPCR, BP_CPM_MPCR_ON);
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case X1000_CLK_SCLK_A: return sclk_a_get();
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case X1000_CLK_CPU: return ccr_get(BP_CPM_CCR_SEL_CPLL, BP_CPM_CCR_CDIV);
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case X1000_CLK_L2CACHE: return ccr_get(BP_CPM_CCR_SEL_CPLL, BP_CPM_CCR_L2DIV);
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case X1000_CLK_AHB0: return ccr_get(BP_CPM_CCR_SEL_H0PLL, BP_CPM_CCR_H0DIV);
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case X1000_CLK_AHB2: return ccr_get(BP_CPM_CCR_SEL_H2PLL, BP_CPM_CCR_H2DIV);
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case X1000_CLK_PCLK: return ccr_get(BP_CPM_CCR_SEL_H2PLL, BP_CPM_CCR_PDIV);
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case X1000_CLK_DDR: return ddr_get();
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case X1000_CLK_LCD: return lcd_get();
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case X1000_CLK_MSC0: return msc_get(0);
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case X1000_CLK_MSC1: return msc_get(1);
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case X1000_CLK_I2S_MCLK: return i2s_mclk_get();
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case X1000_CLK_I2S_BCLK: return i2s_bclk_get();
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case X1000_CLK_SFC: return sfc_get();
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default: return 0;
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}
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}
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const char* clk_get_name(x1000_clk_t clk)
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{
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switch(clk) {
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#define CASE(x) case X1000_CLK_##x: return #x
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CASE(EXCLK);
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CASE(APLL);
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CASE(MPLL);
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CASE(SCLK_A);
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CASE(CPU);
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CASE(L2CACHE);
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CASE(AHB0);
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CASE(AHB2);
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CASE(PCLK);
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CASE(DDR);
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CASE(LCD);
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CASE(MSC0);
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CASE(MSC1);
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CASE(I2S_MCLK);
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CASE(I2S_BCLK);
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CASE(SFC);
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#undef CASE
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default:
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return "NONE";
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}
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}
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#define CCR_MUX_BITS jz_orm(CPM_CCR, SEL_SRC, SEL_CPLL, SEL_H0PLL, SEL_H2PLL)
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#define CSR_MUX_BITS jz_orm(CPM_CSR, SRC_MUX, CPU_MUX, AHB0_MUX, AHB2_MUX)
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#define CSR_DIV_BITS jz_orm(CPM_CSR, H2DIV_BUSY, H0DIV_BUSY, CDIV_BUSY)
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void clk_set_ccr_mux(uint32_t muxbits)
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{
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/* Set new mux configuration */
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uint32_t reg = REG_CPM_CCR;
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reg &= ~CCR_MUX_BITS;
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reg |= muxbits & CCR_MUX_BITS;
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REG_CPM_CCR = reg;
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/* Wait for mux change to complete */
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while((REG_CPM_CSR & CSR_MUX_BITS) != CSR_MUX_BITS);
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}
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void clk_set_ccr_div(int cpu, int l2, int ahb0, int ahb2, int pclk)
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{
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/* Set new divider configuration */
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jz_writef(CPM_CCR, CDIV(cpu - 1), L2DIV(l2 - 1),
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H0DIV(ahb0 - 1), H2DIV(ahb2 - 1), PDIV(pclk - 1),
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CE_CPU(1), CE_AHB0(1), CE_AHB2(1));
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/* Wait until divider change completes */
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while(REG_CPM_CSR & CSR_DIV_BITS);
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/* Disable CE bits after change */
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jz_writef(CPM_CCR, CE_CPU(0), CE_AHB0(0), CE_AHB2(0));
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}
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void clk_set_ddr(x1000_clk_t src, uint32_t div)
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{
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/* Write new configuration */
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jz_writef(CPM_DDRCDR, CE(1), CLKDIV(div - 1),
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CLKSRC(src == X1000_CLK_MPLL ? 2 : 1));
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/* Wait until mux and divider change are complete */
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while(jz_readf(CPM_CSR, DDR_MUX) == 0);
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while(jz_readf(CPM_DDRCDR, BUSY));
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/* Disable CE bit after change */
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jz_writef(CPM_DDRCDR, CE(0));
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}
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