99b2742cd0
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@12677 a1c6a512-1295-4272-9138-f99709370657
225 lines
6.7 KiB
C
225 lines
6.7 KiB
C
/***************************************************************************
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* __________ __ ___.
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* Open \______ \ ____ ____ | | _\_ |__ _______ ___
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* Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
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* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
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* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
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* \/ \/ \/ \/ \/
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* $Id$
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*
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* Copyright (C) 2005 Miika Pekkarinen
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*
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* All files in this archive are subject to the GNU General Public License.
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* See the file COPYING in the source tree root for full license agreement.
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*
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* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
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* KIND, either express or implied.
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*
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****************************************************************************/
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#ifndef _DSP_H
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#define _DSP_H
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#include <stdlib.h>
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#include <stdbool.h>
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#define NATIVE_FREQUENCY 44100
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enum
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{
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STEREO_INTERLEAVED = 0,
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STEREO_NONINTERLEAVED,
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STEREO_MONO,
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STEREO_NUM_MODES,
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};
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enum
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{
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CODEC_SET_FILEBUF_WATERMARK = 1,
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CODEC_SET_FILEBUF_CHUNKSIZE,
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CODEC_SET_FILEBUF_PRESEEK,
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DSP_SWITCH_CODEC,
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DSP_SET_FREQUENCY,
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DSP_SWITCH_FREQUENCY,
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DSP_SET_SAMPLE_DEPTH,
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DSP_SET_STEREO_MODE,
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DSP_RESET,
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DSP_FLUSH,
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DSP_SET_TRACK_GAIN,
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DSP_SET_ALBUM_GAIN,
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DSP_SET_TRACK_PEAK,
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DSP_SET_ALBUM_PEAK,
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DSP_CROSSFEED
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};
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enum {
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DSP_CALLBACK_SET_PRESCALE = 0,
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DSP_CALLBACK_SET_BASS,
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DSP_CALLBACK_SET_TREBLE,
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DSP_CALLBACK_SET_CHANNEL_CONFIG,
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DSP_CALLBACK_SET_STEREO_WIDTH
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};
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/* A bunch of fixed point assembler helper macros */
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#if defined(CPU_COLDFIRE) && !defined(SIMULATOR)
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/* These macros use the Coldfire EMAC extension and need the MACSR flags set
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* to fractional mode with no rounding.
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*/
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/* Multiply two S.31 fractional integers and return the sign bit and the
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* 31 most significant bits of the result.
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*/
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#define FRACMUL(x, y) \
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({ \
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long t; \
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asm ("mac.l %[a], %[b], %%acc0\n\t" \
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"movclr.l %%acc0, %[t]\n\t" \
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: [t] "=r" (t) : [a] "r" (x), [b] "r" (y)); \
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t; \
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})
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/* Multiply two S.31 fractional integers, and return the 32 most significant
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* bits after a shift left by the constant z. NOTE: Only works for shifts of
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* up to 8 on Coldfire!
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*/
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#define FRACMUL_SHL(x, y, z) \
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({ \
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long t, t2; \
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asm ("mac.l %[a], %[b], %%acc0\n\t" \
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"moveq.l %[d], %[t]\n\t" \
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"move.l %%accext01, %[t2]\n\t" \
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"and.l %[mask], %[t2]\n\t" \
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"lsr.l %[t], %[t2]\n\t" \
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"movclr.l %%acc0, %[t]\n\t" \
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"asl.l %[c], %[t]\n\t" \
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"or.l %[t2], %[t]\n\t" \
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: [t] "=&d" (t), [t2] "=&d" (t2) \
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: [a] "r" (x), [b] "r" (y), [mask] "d" (0xff), \
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[c] "i" ((z)), [d] "i" (8 - (z))); \
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t; \
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})
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/* Multiply one S.31-bit and one S8.23 fractional integer and return the
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* sign bit and the 31 most significant bits of the result. Load next value
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* to multiply with into x from s (and increase s); x must contain the
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* initial value.
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*/
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#define FRACMUL_8_LOOP(x, y, s, d) \
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{ \
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long t, t2; \
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asm volatile ("mac.l %[a], %[b], (%[src])+, %[a], %%acc0\n\t" \
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"move.l %%accext01, %[t2]\n\t" \
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"movclr.l %%acc0, %[t]\n\t" \
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"asl.l #8, %[t]\n\t" \
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"move.b %[t2], %[t]\n\t" \
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"move.l %[t], (%[dst])+\n\t" \
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: [a] "+r" (x), [src] "+a" (s), [dst] "+a" (d), \
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[t] "=r" (t), [t2] "=r" (t2) \
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: [b] "r" (y)); \
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}
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#define ACC(acc, x, y) \
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(void)acc; \
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asm ("mac.l %[a], %[b], %%acc0" \
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: : [a] "i,r" (x), [b] "i,r" (y));
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#define GET_ACC(acc) \
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({ \
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long t; \
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(void)acc; \
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asm ("movclr.l %%acc0, %[t]" \
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: [t] "=r" (t)); \
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t; \
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})
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#define ACC_INIT(acc, x, y) ACC(acc, x, y)
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#elif defined(CPU_ARM) && !defined(SIMULATOR)
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/* Multiply two S.31 fractional integers and return the sign bit and the
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* 31 most significant bits of the result.
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*/
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#define FRACMUL(x, y) \
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({ \
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long t, t2; \
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asm ("smull %[t], %[t2], %[a], %[b]\n\t" \
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"mov %[t2], %[t2], asl #1\n\t" \
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"orr %[t], %[t2], %[t], lsr #31\n\t" \
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: [t] "=&r" (t), [t2] "=&r" (t2) \
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: [a] "r" (x), [b] "r" (y)); \
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t; \
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})
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/* Multiply two S.31 fractional integers, and return the 32 most significant
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* bits after a shift left by the constant z.
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*/
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#define FRACMUL_SHL(x, y, z) \
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({ \
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long t, t2; \
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asm ("smull %[t], %[t2], %[a], %[b]\n\t" \
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"mov %[t2], %[t2], asl %[c]\n\t" \
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"orr %[t], %[t2], %[t], lsr %[d]\n\t" \
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: [t] "=&r" (t), [t2] "=&r" (t2) \
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: [a] "r" (x), [b] "r" (y), \
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[c] "M" ((z) + 1), [d] "M" (31 - (z))); \
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t; \
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})
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#define ACC_INIT(acc, x, y) acc = FRACMUL(x, y)
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#define ACC(acc, x, y) acc += FRACMUL(x, y)
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#define GET_ACC(acc) acc
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/* Multiply one S.31-bit and one S8.23 fractional integer and store the
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* sign bit and the 31 most significant bits of the result to d (and
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* increase d). Load next value to multiply with into x from s (and
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* increase s); x must contain the initial value.
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*/
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#define FRACMUL_8_LOOP(x, y, s, d) \
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({ \
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long t, t2; \
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asm volatile ("smull %[t], %[t2], %[a], %[b]\n\t" \
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"mov %[t2], %[t2], asl #9\n\t" \
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"orr %[d], %[t2], %[t], lsr #23\n\t" \
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: [d] "=&r" (*(d)++), [t] "=&r" (t), [t2] "=&r" (t2) \
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: [a] "r" (x), [b] "r" (y)); \
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x = *(s)++; \
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})
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#else
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#define ACC_INIT(acc, x, y) acc = FRACMUL(x, y)
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#define ACC(acc, x, y) acc += FRACMUL(x, y)
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#define GET_ACC(acc) acc
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#define FRACMUL(x, y) (long) (((((long long) (x)) * ((long long) (y))) >> 31))
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#define FRACMUL_SHL(x, y, z) \
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((long)(((((long long) (x)) * ((long long) (y))) >> (31 - (z)))))
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#define FRACMUL_8_LOOP(x, y, s, d) \
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({ \
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long t = x; \
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x = *(s)++; \
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*(d)++ = (long) (((((long long) (t)) * ((long long) (y))) >> 23)); \
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})
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#endif
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#define DIV64(x, y, z) (long)(((long long)(x) << (z))/(y))
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int dsp_process(char *dest, const char *src[], int count);
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int dsp_input_count(int count);
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int dsp_output_count(int count);
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int dsp_stereo_mode(void);
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bool dsp_configure(int setting, intptr_t value);
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void dsp_set_replaygain(void);
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void dsp_set_crossfeed(bool enable);
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void dsp_set_crossfeed_direct_gain(int gain);
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void dsp_set_crossfeed_cross_params(long lf_gain, long hf_gain, long cutoff);
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void dsp_set_eq(bool enable);
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void dsp_set_eq_precut(int precut);
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void dsp_set_eq_coefs(int band);
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void sound_set_pitch(int r);
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int sound_get_pitch(void);
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int dsp_callback(int msg, intptr_t param);
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void dsp_set_channel_config(int value);
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void dsp_set_stereo_width(int value);
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void dsp_dither_enable(bool enable);
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#endif
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