cdbf33adf7
* add mas35xx driver for all mas35xx targets. Later mas35xx code from sound.c will move to this new driver git-svn-id: svn://svn.rockbox.org/rockbox/trunk@13464 a1c6a512-1295-4272-9138-f99709370657
139 lines
6.1 KiB
C
139 lines
6.1 KiB
C
/***************************************************************************
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* __________ __ ___.
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* Open \______ \ ____ ____ | | _\_ |__ _______ ___
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* Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
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* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
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* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
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* \/ \/ \/ \/ \/
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* $Id$
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*
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* Copyright (C) 2005 by Christian Gmeiner
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*
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* All files in this archive are subject to the GNU General Public License.
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* See the file COPYING in the source tree root for full license agreement.
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*
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* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
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* KIND, either express or implied.
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*
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****************************************************************************/
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#ifndef _TLV320_H_
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#define _TLV320_H_
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#define VOLUME_MIN -730
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#define VOLUME_MAX 60
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#include "audiohw.h"
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extern int tenthdb2master(int db);
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/*** definitions ***/
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extern void audiohw_init(void);
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extern void audiohw_reset(void);
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/**
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* Sets internal sample rate for DAC and ADC relative to MCLK
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* Selection for frequency:
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* Fs: tlv: with:
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* 11025: 0 = MCLK/2 MCLK/2 SCLK, LRCK: Audio Clk / 16
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* 22050: 0 = MCLK/2 MCLK SCLK, LRCK: Audio Clk / 8
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* 44100: 1 = MCLK MCLK SCLK, LRCK: Audio Clk / 4 (default)
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* 88200: 2 = MCLK*2 MCLK SCLK, LRCK: Audio Clk / 2
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*/
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extern void audiohw_set_frequency(unsigned fsel);
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extern void audiohw_enable_output(bool enable);
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extern void audiohw_set_headphone_vol(int vol_l, int vol_r);
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extern void audiohw_set_recvol(int left, int right, int type);
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extern void audiohw_mute(bool mute);
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extern void audiohw_close(void);
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extern void audiohw_enable_recording(bool source_mic);
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extern void audiohw_disable_recording(void);
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extern void audiohw_set_monitor(bool enable);
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#define HEADPHONE_MUTE 0x30 /* 0110000 = -73db */
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/* ToDo: samplerates */
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/* registers */
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/* REG_LLIV: Left line input channel volume control */
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#define REG_LLIV 0x0
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#define LLIV_LRS (1 << 8) /* simultaneous volume/mute update */
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#define LLIV_LIM (1 << 7) /* Left line input mute */
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#define LLIV_LIV(x) ((x) & 0x1f)/* Left line input volume control */
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/* REG_RLIV: Right line input channel volume control */
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#define REG_RLIV 0x1
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#define RLIV_RLS (1 << 8) /* simultaneous volume/mute update */
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#define RLIV_RIM (1 << 7) /* Right line input mute */
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#define RLIV_RIV(x) ((x) & 0x1f)/* Right line input volume control */
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/* REG_LHV: Left Channel Headphone Volume Control */
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#define REG_LHV 0x2
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#define LHV_LRS (1 << 8) /* simultaneous volume/mute update */
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#define LHV_LZC (1 << 7) /* Left-channel zero-cross detect */
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#define LHV_LHV(x) ((x) & 0x7f)/* Left headphone volume control */
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/* REG_RHV: Right Channel Headphone Volume Control */
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#define REG_RHV 0x3
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#define RHV_LRS (1 << 8) /* simultaneous volume/mute update */
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#define RHV_RZC (1 << 7) /* Right-channel zero-cross detect */
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#define RHV_RHV(x) ((x) & 0x7f)/* Right headphone volume control */
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/* REG_AAP: Analog Audio Path Control */
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#define REG_AAP 0x4
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#define AAP_DAC (1 << 4) /* DAC select */
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#define AAP_BYPASS (1 << 3) /* bypass */
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#define AAP_INSEL (1 << 2) /* Input select for ADC */
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#define AAP_MICM (1 << 1) /* Microphone mute */
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#define AAP_MICB (1 << 0) /* Microphone boost */
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/* REG_DAP: Digital Audio Path Control */
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#define REG_DAP 0x5
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#define DAP_DACM (1 << 3) /* DAC soft mute */
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#define DAP_DEEMP_32 (1 << 1) /* De-emphasis control: 32 kHz */
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#define DAP_DEEMP_44 (2 << 1) /* De-emphasis control: 44.1 kHz */
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#define DAP_DEEMP_48 (3 << 1) /* De-emphasis control: 48 kHz */
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#define DAP_ADCHP (1 << 0) /* ADC high-pass filter */
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/* REG_PC: Power Down Control */
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#define REG_PC 0x6
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#define PC_OFF (1 << 7) /* Device power */
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#define PC_CLK (1 << 6) /* Clock */
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#define PC_OSC (1 << 5) /* Oscillator */
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#define PC_OUT (1 << 4) /* Outputs */
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#define PC_DAC (1 << 3) /* DAC */
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#define PC_ADC (1 << 2) /* ADC */
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#define PC_MIC (1 << 1) /* Microphone input */
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#define PC_LINE (1 << 0) /* Line input */
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/* REG_DAIF: Digital Audio Interface Format */
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#define REG_DAIF 0x7
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#define DAIF_MS (1 << 6) /* Master/slave mode */
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#define DAIF_LRSWAP (1 << 5) /* DAC left/right swap */
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#define DAIF_LRP (1 << 4) /* DAC left/right phase */
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#define DAIF_IWL_16 (0 << 2) /* Input bit length: 16 bit */
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#define DAIF_IWL_20 (1 << 2) /* Input bit length: 20 bit */
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#define DAIF_IWL_24 (2 << 2) /* Input bit length: 24 bit */
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#define DAIF_IWL_32 (3 << 2) /* Input bit length: 32 bit */
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#define DAIF_FOR_DSP (3 << 0) /* Data format: DSP */
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#define DAIF_FOR_I2S (2 << 0) /* Data format: I2S */
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#define DAIF_FOR_MSBL (1 << 0) /* Data format: MSB first, left aligned */
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#define DAIF_FOR_MSBR (0 << 0) /* Data format: MSB first, right aligned */
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/* REG_SRC: Sample Rate Control */
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#define REG_SRC 0x8
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#define SRC_CLKIN (1 << 6) /* Clock input divider */
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#define SRC_CLKOUT (1 << 7) /* Clock output divider */
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/*#define SRC_SR ()*/
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#define SRC_BOSR (1 << 1) /* Base oversampling rate, depends on SRC_USB */
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#define SRC_USB (1 << 0) /* Clock mode select */
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/* REG_DIA: Digital Interface Activation */
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#define REG_DIA 0x9
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#define DIA_ACT (1 << 0) /* Activate interface */
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/* REG_RR: Reset Register */
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#define REG_RR 0xf
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#define RR_RESET 0 /* Reset */
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#endif /*_TLV320_H_*/
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