rockbox/firmware/target/arm/imx233/boot.lds
Solomon Peachy cd9906847b arm: Fix PortalPlayer linker scripts with binutils 2.21+
For reasons that are still unclear, the 'ncbss' region was overlapping
the "audiobuffer" when linked with 2.21, but okay with 2.20.

Fixed it by making the audiobuffer explcitly use the current position
instead of relying on it being implicit.

With this change, portalplayer-based targets generate working binaries
when built with binutils 2.21 or newer.

This bug also theoretically affects imx233/imx31 targets as they
also have NOCACHE_BASE games in their linker scripts, but I lack
access to one to test with.

Change-Id: Idb38ab20f03599b9ed3d4bc0eafe519f38677438
2020-07-05 03:34:30 +00:00

97 lines
2.2 KiB
Text

#include "config.h"
#include "cpu.h"
ENTRY(start)
OUTPUT_FORMAT(elf32-littlearm)
OUTPUT_ARCH(arm)
STARTUP(target/arm/imx233/crt0.o)
/* Leave a hole at the beginning of the RAM to load the firmware */
#define RAM_HOLE 1024 * 1024
/* Make a difference between virtual and physical address so that we can use
* the resulting elf file with the elftosb tools which loads at the *physical*
* address */
MEMORY
{
IRAM : ORIGIN = IRAM_ORIG, LENGTH = IRAM_SIZE
DRAM : ORIGIN = CACHED_DRAM_ADDR + RAM_HOLE, LENGTH = DRAM_SIZE - TTB_SIZE - FRAME_SIZE - RAM_HOLE
UDRAM : ORIGIN = UNCACHED_DRAM_ADDR + RAM_HOLE, LENGTH = DRAM_SIZE - TTB_SIZE - FRAME_SIZE - RAM_HOLE
}
SECTIONS
{
loadaddress = UNCACHED_DRAM_ADDR;
_loadaddress = UNCACHED_DRAM_ADDR;
loadaddressend = UNCACHED_DRAM_ADDR + RAM_HOLE;
_loadaddressend = UNCACHED_DRAM_ADDR + RAM_HOLE;
.dramcopystart (NOLOAD) :
{
_dramcopystart = .;
} > DRAM
.text :
{
*(.text*)
*(.data*)
*(.rodata*)
} > DRAM
.itext :
{
_iramstart = .; // always 0
KEEP(*(.vectors));// otherwise there are no references to it and the linker strip it
*(.icode*)
*(.irodata*)
*(.idata*)
_iramend = .;
} > IRAM AT> DRAM
_iramcopy = LOADADDR(.itext);
.dramcopyend (NOLOAD) :
{
_dramcopyend = .;
} > DRAM
.ibss (NOLOAD) :
{
_iedata = .;
*(.qharray)
*(.ibss*)
_iend = .;
} > IRAM
.stack (NOLOAD) :
{
*(.stack)
stackbegin = .;
. += 0x2000;
stackend = .;
} > DRAM
/* physical address of the stack */
crt0_tmpstack_phys = stackend - CACHED_DRAM_ADDR + UNCACHED_DRAM_ADDR;
/* treat .bss and .ncbss as a single section */
.bss (NOLOAD) :
{
_edata = .;
*(.bss*);
} > DRAM
/* align on cache size boundary to avoid mixing cached and noncached stuff */
.ncbss . - CACHED_DRAM_ADDR + UNCACHED_DRAM_ADDR (NOLOAD) :
{
. = ALIGN(CACHEALIGN_SIZE);
*(.ncbss*)
. = ALIGN(CACHEALIGN_SIZE);
} AT> DRAM
.bssendadr . (NOLOAD) :
{
_end = .;
} > DRAM
}